asmjit 0.2.0 → 0.2.1

data/ext/asmjit/asmjit/src/asmjit/core/archcommons.h

@@ -0,0 +1,229 @@
+// This file is part of AsmJit project <https://asmjit.com>
+//
+// See asmjit.h or LICENSE.md for license and copyright information
+// SPDX-License-Identifier: Zlib
+
+#ifndef ASMJIT_CORE_ARCHCOMMONS_H_INCLUDED
+#define ASMJIT_CORE_ARCHCOMMONS_H_INCLUDED
+
+// This file provides architecture-specific classes that are required in the core library. For example Imm operand
+// allows to be created from arm::Shift in a const-expr way, so the arm::Shift must be provided. So this header file
+// provides everything architecture-specific that is used by the Core API.
+
+#include "../core/globals.h"
+
+ASMJIT_BEGIN_SUB_NAMESPACE(arm)
+
+//! \addtogroup asmjit_arm
+//! \{
+
+//! Condition code (both AArch32 & AArch64).
+//!
+//! \note This enumeration doesn't match condition code that is used in AArch32/AArch64 opcodes. In general this
+//! condition code is encoded as `(cc - 2) & 0xF` so that `kAL` condition code is zero and encoded as 0xE in opcode.
+//! This makes it easier to use a condition code as an instruction modifier that defaults to 'al'.
+enum class CondCode : uint8_t {
+  kAL             = 0x00u,      //!< (no condition code) (always)
+  kNA             = 0x01u,      //!< (not available)     (special)
+  kEQ             = 0x02u,      //!<        Z==1         (any_sign ==)
+  kNE             = 0x03u,      //!<        Z==0         (any_sign !=)
+  kCS             = 0x04u,      //!< C==1                (unsigned >=)
+  kHS             = 0x04u,      //!< C==1                (unsigned >=)
+  kCC             = 0x05u,      //!< C==0                (unsigned < )
+  kLO             = 0x05u,      //!< C==0                (unsigned < )
+  kMI             = 0x06u,      //!<               N==1  (is negative)
+  kPL             = 0x07u,      //!<               N==0  (is positive or zero)
+  kVS             = 0x08u,      //!<               V==1  (is overflow)
+  kVC             = 0x09u,      //!<               V==0  (no overflow)
+  kHI             = 0x0Au,      //!< C==1 & Z==0         (unsigned > )
+  kLS             = 0x0Bu,      //!< C==0 | Z==1         (unsigned <=)
+  kGE             = 0x0Cu,      //!<               N==V  (signed   >=)
+  kLT             = 0x0Du,      //!<               N!=V  (signed   < )
+  kGT             = 0x0Eu,      //!<        Z==0 & N==V  (signed   > )
+  kLE             = 0x0Fu,      //!<        Z==1 | N!=V  (signed   <=)
+
+  kSign           = kMI,        //!< Sign.
+  kNotSign        = kPL,        //!< Not sign.
+
+  kOverflow       = kVS,        //!< Signed overflow.
+  kNotOverflow    = kVC,        //!< Not signed overflow.
+
+  kEqual          = kEQ,        //!< Equal     `a == b`.
+  kNotEqual       = kNE,        //!< Not Equal `a != b`.
+
+  kZero           = kEQ,        //!< Zero (alias to equal).
+  kNotZero        = kNE,        //!< Not Zero (alias to Not Equal).
+
+  kNegative       = kMI,        //!< Negative.
+  kPositive       = kPL,        //!< Positive or zero.
+
+  kSignedLT       = kLT,        //!< Signed    `a <  b`.
+  kSignedLE       = kLE,        //!< Signed    `a <= b`.
+  kSignedGT       = kGT,        //!< Signed    `a >  b`.
+  kSignedGE       = kGE,        //!< Signed    `a >= b`.
+
+  kUnsignedLT     = kLO,        //!< Unsigned  `a <  b`.
+  kUnsignedLE     = kLS,        //!< Unsigned  `a <= b`.
+  kUnsignedGT     = kHI,        //!< Unsigned  `a >  b`.
+  kUnsignedGE     = kHS,        //!< Unsigned  `a >= b`.
+
+  kAlways         = kAL,        //!< No condition code (always).
+
+  kMaxValue       = 0x0Fu       //!< Maximum value of `CondCode`.
+};
+
+//! Negates a condition code.
+static inline constexpr CondCode negateCond(CondCode cond) noexcept { return CondCode(uint8_t(cond) ^ uint8_t(1)); }
+
+//! Data type that can be encoded with the instruction (AArch32 only).
+enum class DataType : uint32_t {
+  //! No data type specified (default for all general purpose instructions).
+  kNone = 0,
+  //! 8-bit signed integer, specified as `.s8` in assembly.
+  kS8 = 1,
+  //! 16-bit signed integer, specified as `.s16` in assembly.
+  kS16 = 2,
+  //! 32-bit signed integer, specified as `.s32` in assembly.
+  kS32 = 3,
+  //! 64-bit signed integer, specified as `.s64` in assembly.
+  kS64 = 4,
+  //! 8-bit unsigned integer, specified as `.u8` in assembly.
+  kU8 = 5,
+  //! 16-bit unsigned integer, specified as `.u16` in assembly.
+  kU16 = 6,
+  //! 32-bit unsigned integer, specified as `.u32` in assembly.
+  kU32 = 7,
+  //! 64-bit unsigned integer, specified as `.u64` in assembly.
+  kU64 = 8,
+  //! 16-bit floating point (half precision), specified as `.f16` in assembly.
+  kF16 = 10,
+  //! 32-bit floating point (single precision), specified as `.f32` in assembly.
+  kF32 = 11,
+  //! 64-bit floating point (double precision), specified as `.f64` in assembly.
+  kF64 = 12,
+  //! 8-bit polynomial.
+  kP8 = 13,
+  //! 64-bit polynomial.
+  kP64 = 15,
+
+  //! Maximum value of `DataType`.
+  kMaxValue = 15
+};
+
+//! Shift operation predicate (ARM) describes either SHIFT or EXTEND operation.
+//!
+//! \note The constants are AsmJit specific. The first 5 values describe real constants on ARM32 and AArch64 hardware,
+//! however, the addition constants that describe extend modes are specific to AsmJit and would be translated to the
+//! AArch64 specific constants by the assembler.
+enum class ShiftOp : uint32_t {
+  //! Shift left logical operation (default).
+  //!
+  //! Available to all ARM architectures.
+  kLSL = 0x00u,
+
+  //! Shift right logical operation.
+  //!
+  //! Available to all ARM architectures.
+  kLSR = 0x01u,
+
+  //! Shift right arithmetic operation.
+  //!
+  //! Available to all ARM architectures.
+  kASR = 0x02u,
+
+  //! Rotate right operation (AArch32 only).
+  kROR = 0x03u,
+
+  //! Rotate right with carry operation (encoded as `ShiftOp::kROR` with zero) (AArch32 only).
+  kRRX = 0x04u,
+
+  //! Shift left by filling low order bits with ones.
+  kMSL = 0x05u,
+
+  //! UXTN extend register operation (AArch64 only).
+  kUXTB = 0x06u,
+  //! UXTH extend register operation (AArch64 only).
+  kUXTH = 0x07u,
+  //! UXTW extend register operation (AArch64 only).
+  kUXTW = 0x08u,
+  //! UXTX extend register operation (AArch64 only).
+  kUXTX = 0x09u,
+
+  //! SXTB extend register operation (AArch64 only).
+  kSXTB = 0x0Au,
+  //! SXTH extend register operation (AArch64 only).
+  kSXTH = 0x0Bu,
+  //! SXTW extend register operation (AArch64 only).
+  kSXTW = 0x0Cu,
+  //! SXTX extend register operation (AArch64 only).
+  kSXTX = 0x0Du
+
+  // NOTE: 0xE and 0xF are used by memory operand to specify POST|PRE offset mode.
+};
+
+//! Represents ARM immediate shift operation type and value.
+class Shift {
+public:
+  //! Shift operation.
+  ShiftOp _op;
+  //! Shift Value.
+  uint32_t _value;
+
+  //! Default constructed Shift is not initialized.
+  inline Shift() noexcept = default;
+
+  //! Copy constructor (default)
+  constexpr Shift(const Shift& other) noexcept = default;
+
+  //! Constructs Shift from operation `op` and shift `value`.
+  constexpr Shift(ShiftOp op, uint32_t value) noexcept
+    : _op(op),
+      _value(value) {}
+
+  //! Returns the shift operation.
+  constexpr ShiftOp op() const noexcept { return _op; }
+  //! Sets shift operation to `op`.
+  inline void setOp(ShiftOp op) noexcept { _op = op; }
+
+  //! Returns the shift smount.
+  constexpr uint32_t value() const noexcept { return _value; }
+  //! Sets shift amount to `value`.
+  inline void setValue(uint32_t value) noexcept { _value = value; }
+};
+
+//! Constructs a `LSL #value` shift (logical shift left).
+static constexpr Shift lsl(uint32_t value) noexcept { return Shift(ShiftOp::kLSL, value); }
+//! Constructs a `LSR #value` shift (logical shift right).
+static constexpr Shift lsr(uint32_t value) noexcept { return Shift(ShiftOp::kLSR, value); }
+//! Constructs a `ASR #value` shift (arithmetic shift right).
+static constexpr Shift asr(uint32_t value) noexcept { return Shift(ShiftOp::kASR, value); }
+//! Constructs a `ROR #value` shift (rotate right).
+static constexpr Shift ror(uint32_t value) noexcept { return Shift(ShiftOp::kROR, value); }
+//! Constructs a `RRX` shift (rotate with carry by 1).
+static constexpr Shift rrx() noexcept { return Shift(ShiftOp::kRRX, 0); }
+//! Constructs a `MSL #value` shift (logical shift left filling ones).
+static constexpr Shift msl(uint32_t value) noexcept { return Shift(ShiftOp::kMSL, value); }
+
+//! Constructs a `UXTB #value` extend and shift (unsigned byte extend).
+static constexpr Shift uxtb(uint32_t value) noexcept { return Shift(ShiftOp::kUXTB, value); }
+//! Constructs a `UXTH #value` extend and shift (unsigned hword extend).
+static constexpr Shift uxth(uint32_t value) noexcept { return Shift(ShiftOp::kUXTH, value); }
+//! Constructs a `UXTW #value` extend and shift (unsigned word extend).
+static constexpr Shift uxtw(uint32_t value) noexcept { return Shift(ShiftOp::kUXTW, value); }
+//! Constructs a `UXTX #value` extend and shift (unsigned dword extend).
+static constexpr Shift uxtx(uint32_t value) noexcept { return Shift(ShiftOp::kUXTX, value); }
+
+//! Constructs a `SXTB #value` extend and shift (signed byte extend).
+static constexpr Shift sxtb(uint32_t value) noexcept { return Shift(ShiftOp::kSXTB, value); }
+//! Constructs a `SXTH #value` extend and shift (signed hword extend).
+static constexpr Shift sxth(uint32_t value) noexcept { return Shift(ShiftOp::kSXTH, value); }
+//! Constructs a `SXTW #value` extend and shift (signed word extend).
+static constexpr Shift sxtw(uint32_t value) noexcept { return Shift(ShiftOp::kSXTW, value); }
+//! Constructs a `SXTX #value` extend and shift (signed dword extend).
+static constexpr Shift sxtx(uint32_t value) noexcept { return Shift(ShiftOp::kSXTX, value); }
+
+//! \}
+
+ASMJIT_END_SUB_NAMESPACE
+
+#endif // ASMJIT_CORE_ARCHCOMMONS_H_INCLUDED

data/ext/asmjit/asmjit/src/asmjit/core/archtraits.cpp

@@ -0,0 +1,160 @@
+// This file is part of AsmJit project <https://asmjit.com>
+//
+// See asmjit.h or LICENSE.md for license and copyright information
+// SPDX-License-Identifier: Zlib
+
+#include "../core/api-build_p.h"
+#include "../core/archtraits.h"
+#include "../core/misc_p.h"
+
+#if !defined(ASMJIT_NO_X86)
+  #include "../x86/x86archtraits_p.h"
+#endif
+
+#if !defined(ASMJIT_NO_AARCH64)
+  #include "../arm/a64archtraits_p.h"
+#endif
+
+ASMJIT_BEGIN_NAMESPACE
+
+static const constexpr ArchTraits noArchTraits = {
+  // SP/FP/LR/PC.
+  0xFF, 0xFF, 0xFF, 0xFF,
+
+  // Reserved,
+  { 0, 0, 0 },
+
+  // HW stack alignment.
+  0,
+
+  // Min/Max stack offset.
+  0, 0,
+
+  // ISA features [Gp, Vec, Other0, Other1].
+  {{
+    InstHints::kNoHints,
+    InstHints::kNoHints,
+    InstHints::kNoHints,
+    InstHints::kNoHints
+  }},
+
+  // RegTypeToSignature.
+  #define V(index) OperandSignature{0}
+  {{ ASMJIT_LOOKUP_TABLE_32(V, 0) }},
+  #undef V
+
+  // RegTypeToTypeId.
+  #define V(index) TypeId::kVoid
+  {{ ASMJIT_LOOKUP_TABLE_32(V, 0) }},
+  #undef V
+
+  // TypeIdToRegType.
+  #define V(index) RegType::kNone
+  {{ ASMJIT_LOOKUP_TABLE_32(V, 0) }},
+  #undef V
+
+  // Word names of 8-bit, 16-bit, 32-bit, and 64-bit quantities.
+  {
+    ArchTypeNameId::kByte,
+    ArchTypeNameId::kHalf,
+    ArchTypeNameId::kWord,
+    ArchTypeNameId::kQuad
+  }
+};
+
+ASMJIT_VARAPI const ArchTraits _archTraits[uint32_t(Arch::kMaxValue) + 1] = {
+  // No architecture.
+  noArchTraits,
+
+  // X86/X86 architectures.
+#if !defined(ASMJIT_NO_X86)
+  x86::x86ArchTraits,
+  x86::x64ArchTraits,
+#else
+  noArchTraits,
+  noArchTraits,
+#endif
+
+  // RISCV32/RISCV64 architectures.
+  noArchTraits,
+  noArchTraits,
+
+  // ARM architecture
+  noArchTraits,
+
+  // AArch64 architecture.
+#if !defined(ASMJIT_NO_AARCH64)
+  a64::a64ArchTraits,
+#else
+  noArchTraits,
+#endif
+
+  // ARM/Thumb architecture.
+  noArchTraits,
+
+  // Reserved.
+  noArchTraits,
+
+  // MIPS32/MIPS64
+  noArchTraits,
+  noArchTraits
+};
+
+ASMJIT_FAVOR_SIZE Error ArchUtils::typeIdToRegSignature(Arch arch, TypeId typeId, TypeId* typeIdOut, OperandSignature* regSignatureOut) noexcept {
+  const ArchTraits& archTraits = ArchTraits::byArch(arch);
+
+  // TODO: Remove this, should never be used like this.
+  // Passed RegType instead of TypeId?
+  if (uint32_t(typeId) <= uint32_t(RegType::kMaxValue))
+    typeId = archTraits.regTypeToTypeId(RegType(uint32_t(typeId)));
+
+  if (ASMJIT_UNLIKELY(!TypeUtils::isValid(typeId)))
+    return DebugUtils::errored(kErrorInvalidTypeId);
+
+  // First normalize architecture dependent types.
+  if (TypeUtils::isAbstract(typeId)) {
+    bool is32Bit = Environment::is32Bit(arch);
+    if (typeId == TypeId::kIntPtr)
+      typeId = is32Bit ? TypeId::kInt32 : TypeId::kInt64;
+    else
+      typeId = is32Bit ? TypeId::kUInt32 : TypeId::kUInt64;
+  }
+
+  // Type size helps to construct all groups of registers.
+  // TypeId is invalid if the size is zero.
+  uint32_t size = TypeUtils::sizeOf(typeId);
+  if (ASMJIT_UNLIKELY(!size))
+    return DebugUtils::errored(kErrorInvalidTypeId);
+
+  if (ASMJIT_UNLIKELY(typeId == TypeId::kFloat80))
+    return DebugUtils::errored(kErrorInvalidUseOfF80);
+
+  RegType regType = RegType::kNone;
+  if (TypeUtils::isBetween(typeId, TypeId::_kBaseStart, TypeId::_kVec32Start)) {
+    regType = archTraits._typeIdToRegType[uint32_t(typeId) - uint32_t(TypeId::_kBaseStart)];
+    if (regType == RegType::kNone) {
+      if (typeId == TypeId::kInt64 || typeId == TypeId::kUInt64)
+        return DebugUtils::errored(kErrorInvalidUseOfGpq);
+      else
+        return DebugUtils::errored(kErrorInvalidTypeId);
+    }
+  }
+  else {
+    if (size <= 8 && archTraits._regSignature[RegType::kVec64].isValid())
+      regType = RegType::kVec64;
+    else if (size <= 16 && archTraits._regSignature[RegType::kVec128].isValid())
+      regType = RegType::kVec128;
+    else if (size == 32 && archTraits._regSignature[RegType::kVec256].isValid())
+      regType = RegType::kVec256;
+    else if (archTraits._regSignature[RegType::kVec512].isValid())
+      regType = RegType::kVec512;
+    else
+      return DebugUtils::errored(kErrorInvalidTypeId);
+  }
+
+  *typeIdOut = typeId;
+  *regSignatureOut = archTraits.regTypeToSignature(regType);
+  return kErrorOk;
+}
+
+ASMJIT_END_NAMESPACE

data/ext/asmjit/asmjit/src/asmjit/core/archtraits.h

@@ -0,0 +1,290 @@
+// This file is part of AsmJit project <https://asmjit.com>
+//
+// See asmjit.h or LICENSE.md for license and copyright information
+// SPDX-License-Identifier: Zlib
+
+#ifndef ASMJIT_CORE_ARCHTRAITS_H_INCLUDED
+#define ASMJIT_CORE_ARCHTRAITS_H_INCLUDED
+
+#include "../core/operand.h"
+#include "../core/support.h"
+#include "../core/type.h"
+
+ASMJIT_BEGIN_NAMESPACE
+
+//! \addtogroup asmjit_core
+//! \{
+
+//! Instruction set architecture (ISA).
+enum class Arch : uint8_t {
+  //! Unknown or uninitialized ISA.
+  kUnknown = 0,
+
+  //! 32-bit X86 ISA.
+  kX86 = 1,
+  //! 64-bit X86 ISA also known as X64, X86_64, and AMD64.
+  kX64 = 2,
+
+  //! 32-bit RISC-V ISA.
+  kRISCV32 = 3,
+  //! 64-bit RISC-V ISA.
+  kRISCV64 = 4,
+
+  //! 32-bit ARM ISA (little endian).
+  kARM = 5,
+  //! 64-bit ARM ISA in (little endian).
+  kAArch64 = 6,
+  //! 32-bit ARM ISA in Thumb mode (little endian).
+  kThumb = 7,
+
+  // 8 is not used at the moment, even numbers are 64-bit architectures.
+
+  //! 32-bit MIPS ISA in (little endian).
+  kMIPS32_LE = 9,
+  //! 64-bit MIPS ISA in (little endian).
+  kMIPS64_LE = 10,
+
+  //! 32-bit ARM ISA (big endian).
+  kARM_BE = 11,
+  //! 64-bit ARM ISA in (big endian).
+  kAArch64_BE = 12,
+  //! 32-bit ARM ISA in Thumb mode (big endian).
+  kThumb_BE = 13,
+
+  // 14 is not used at the moment, even numbers are 64-bit architectures.
+
+  //! 32-bit MIPS ISA in (big endian).
+  kMIPS32_BE = 15,
+  //! 64-bit MIPS ISA in (big endian).
+  kMIPS64_BE = 16,
+
+  //! Maximum value of `Arch`.
+  kMaxValue = kMIPS64_BE,
+
+  //! Mask used by 32-bit ISAs (odd are 32-bit, even are 64-bit).
+  k32BitMask = 0x01,
+  //! First big-endian architecture.
+  kBigEndian = kARM_BE,
+
+  //! ISA detected at compile-time (ISA of the host).
+  kHost =
+#if defined(_DOXYGEN)
+    DETECTED_AT_COMPILE_TIME
+#else
+    ASMJIT_ARCH_X86 == 32 ? kX86 :
+    ASMJIT_ARCH_X86 == 64 ? kX64 :
+
+    ASMJIT_ARCH_ARM == 32 && ASMJIT_ARCH_LE ? kARM :
+    ASMJIT_ARCH_ARM == 32 && ASMJIT_ARCH_BE ? kARM_BE :
+    ASMJIT_ARCH_ARM == 64 && ASMJIT_ARCH_LE ? kAArch64 :
+    ASMJIT_ARCH_ARM == 64 && ASMJIT_ARCH_BE ? kAArch64_BE :
+
+    ASMJIT_ARCH_MIPS == 32 && ASMJIT_ARCH_LE ? kMIPS32_LE :
+    ASMJIT_ARCH_MIPS == 32 && ASMJIT_ARCH_BE ? kMIPS32_BE :
+    ASMJIT_ARCH_MIPS == 64 && ASMJIT_ARCH_LE ? kMIPS64_LE :
+    ASMJIT_ARCH_MIPS == 64 && ASMJIT_ARCH_BE ? kMIPS64_BE :
+
+    kUnknown
+#endif
+};
+
+//! Sub-architecture.
+enum class SubArch : uint8_t {
+  //! Unknown or uninitialized architecture sub-type.
+  kUnknown = 0,
+
+  //! Maximum value of `SubArch`.
+  kMaxValue = kUnknown,
+
+  //! Sub-architecture detected at compile-time (sub-architecture of the host).
+  kHost =
+#if defined(_DOXYGEN)
+    DETECTED_AT_COMPILE_TIME
+#else
+    kUnknown
+#endif
+};
+
+//! Identifier used to represent names of different data types across architectures.
+enum class ArchTypeNameId : uint8_t {
+  //! Describes 'db' (X86/X86_64 convention, always 8-bit quantity).
+  kDB = 0,
+  //! Describes 'dw' (X86/X86_64 convention, always 16-bit word).
+  kDW,
+  //! Describes 'dd' (X86/X86_64 convention, always 32-bit word).
+  kDD,
+  //! Describes 'dq' (X86/X86_64 convention, always 64-bit word).
+  kDQ,
+  //! Describes 'byte' (always 8-bit quantity).
+  kByte,
+  //! Describes 'half' (most likely 16-bit word).
+  kHalf,
+  //! Describes 'word' (either 16-bit or 32-bit word).
+  kWord,
+  //! Describes 'hword' (most likely 16-bit word).
+  kHWord,
+  //! Describes 'dword' (either 32-bit or 64-bit word).
+  kDWord,
+  //! Describes 'qword' (64-bit word).
+  kQWord,
+  //! Describes 'xword' (64-bit word).
+  kXWord,
+  //! Describes 'short' (always 16-bit word).
+  kShort,
+  //! Describes 'long' (most likely 32-bit word).
+  kLong,
+  //! Describes 'quad' (64-bit word).
+  kQuad,
+
+  //! Maximum value of `ArchTypeNameId`.
+  kMaxValue = kQuad
+};
+
+//! Instruction feature hints for each register group provided by \ref ArchTraits.
+//!
+//! Instruction feature hints describe miscellaneous instructions provided by the architecture that can be used by
+//! register allocator to make certain things simpler - like register swaps or emitting register push/pop sequences.
+//!
+//! \remarks Instruction feature hints are only defined for register groups that can be used with \ref
+//! asmjit_compiler infrastructure. Register groups that are not managed by Compiler are not provided by
+//! \ref ArchTraits and cannot be queried.
+enum class InstHints : uint8_t {
+  //! No feature hints.
+  kNoHints = 0,
+
+  //! Architecture supports a register swap by using a single instruction.
+  kRegSwap = 0x01u,
+  //! Architecture provides push/pop instructions.
+  kPushPop = 0x02u
+};
+ASMJIT_DEFINE_ENUM_FLAGS(InstHints)
+
+//! Architecture traits used by Function API and Compiler's register allocator.
+struct ArchTraits {
+  //! \name Members
+  //! \{
+
+  //! Stack pointer register id.
+  uint8_t _spRegId;
+  //! Frame pointer register id.
+  uint8_t _fpRegId;
+  //! Link register id.
+  uint8_t _linkRegId;
+  //! Instruction pointer (or program counter) register id, if accessible.
+  uint8_t _ipRegId;
+
+  // Reserved.
+  uint8_t _reserved[3];
+  //! Hardware stack alignment requirement.
+  uint8_t _hwStackAlignment;
+
+  //! Minimum addressable offset on stack guaranteed for all instructions.
+  uint32_t _minStackOffset;
+  //! Maximum addressable offset on stack depending on specific instruction.
+  uint32_t _maxStackOffset;
+
+  //! Flags for each virtual register group.
+  Support::Array<InstHints, Globals::kNumVirtGroups> _instHints;
+
+  //! Maps register type into a signature, that provides group, size and can be used to construct register operands.
+  Support::Array<OperandSignature, uint32_t(RegType::kMaxValue) + 1> _regSignature;
+  //! Maps a register to type-id, see \ref TypeId.
+  Support::Array<TypeId, uint32_t(RegType::kMaxValue) + 1> _regTypeToTypeId;
+  //! Maps scalar TypeId values (from TypeId::_kIdBaseStart) to register types, see \ref TypeId.
+  Support::Array<RegType, 32> _typeIdToRegType;
+
+  //! Word name identifiers of 8-bit, 16-bit, 32-biit, and 64-bit quantities that appear in formatted text.
+  ArchTypeNameId _typeNameIdTable[4];
+
+  //! \}
+
+  //! \name Accessors
+  //! \{
+
+  //! Returns stack pointer register id.
+  inline uint32_t spRegId() const noexcept { return _spRegId; }
+  //! Returns stack frame register id.
+  inline uint32_t fpRegId() const noexcept { return _fpRegId; }
+  //! Returns link register id, if the architecture provides it.
+  inline uint32_t linkRegId() const noexcept { return _linkRegId; }
+  //! Returns instruction pointer register id, if the architecture provides it.
+  inline uint32_t ipRegId() const noexcept { return _ipRegId; }
+
+  //! Returns a hardware stack alignment requirement.
+  //!
+  //! \note This is a hardware constraint. Architectures that don't constrain it would return the lowest alignment
+  //! (1), however, some architectures may constrain the alignment, for example AArch64 requires 16-byte alignment.
+  inline uint32_t hwStackAlignment() const noexcept { return _hwStackAlignment; }
+
+  //! Tests whether the architecture provides link register, which is used across function calls. If the link
+  //! register is not provided then a function call pushes the return address on stack (X86/X64).
+  inline bool hasLinkReg() const noexcept { return _linkRegId != BaseReg::kIdBad; }
+
+  //! Returns minimum addressable offset on stack guaranteed for all instructions.
+  inline uint32_t minStackOffset() const noexcept { return _minStackOffset; }
+  //! Returns maximum addressable offset on stack depending on specific instruction.
+  inline uint32_t maxStackOffset() const noexcept { return _maxStackOffset; }
+
+  //! Returns ISA flags of the given register `group`.
+  inline InstHints instFeatureHints(RegGroup group) const noexcept { return _instHints[group]; }
+  //! Tests whether the given register `group` has the given `flag` set.
+  inline bool hasInstHint(RegGroup group, InstHints feature) const noexcept { return Support::test(_instHints[group], feature); }
+  //! Tests whether the ISA provides register swap instruction for the given register `group`.
+  inline bool hasInstRegSwap(RegGroup group) const noexcept { return hasInstHint(group, InstHints::kRegSwap); }
+  //! Tests whether the ISA provides push/pop instructions for the given register `group`.
+  inline bool hasInstPushPop(RegGroup group) const noexcept { return hasInstHint(group, InstHints::kPushPop); }
+
+  inline bool hasRegType(RegType type) const noexcept {
+    return type <= RegType::kMaxValue && _regSignature[type].isValid();
+  }
+
+  //! Returns an operand signature from the given register `type` of this architecture.
+  inline OperandSignature regTypeToSignature(RegType type) const noexcept { return _regSignature[type]; }
+  //! Returns a register from the given register `type` of this architecture.
+  inline RegGroup regTypeToGroup(RegType type) const noexcept { return _regSignature[type].regGroup(); }
+  //! Returns a register size the given register `type` of this architecture.
+  inline uint32_t regTypeToSize(RegType type) const noexcept { return _regSignature[type].size(); }
+  //! Returns a corresponding `TypeId` from the given register `type` of this architecture.
+  inline TypeId regTypeToTypeId(RegType type) const noexcept { return _regTypeToTypeId[type]; }
+
+  //! Returns a table of ISA word names that appear in formatted text. Word names are ISA dependent.
+  //!
+  //! The index of this table is log2 of the size:
+  //!   - [0] 8-bits
+  //!   - [1] 16-bits
+  //!   - [2] 32-bits
+  //!   - [3] 64-bits
+  inline const ArchTypeNameId* typeNameIdTable() const noexcept { return _typeNameIdTable; }
+
+  //! Returns an ISA word name identifier of the given `index`, see \ref typeNameIdTable() for more details.
+  inline ArchTypeNameId typeNameIdByIndex(uint32_t index) const noexcept { return _typeNameIdTable[index]; }
+
+  //! \}
+
+  //! \name Statics
+  //! \{
+
+  //! Returns a const reference to `ArchTraits` for the given architecture `arch`.
+  static inline const ArchTraits& byArch(Arch arch) noexcept;
+
+  //! \}
+};
+
+ASMJIT_VARAPI const ArchTraits _archTraits[uint32_t(Arch::kMaxValue) + 1];
+
+//! \cond
+inline const ArchTraits& ArchTraits::byArch(Arch arch) noexcept { return _archTraits[uint32_t(arch)]; }
+//! \endcond
+
+//! Architecture utilities.
+namespace ArchUtils {
+
+ASMJIT_API Error typeIdToRegSignature(Arch arch, TypeId typeId, TypeId* typeIdOut, OperandSignature* regSignatureOut) noexcept;
+
+} // {ArchUtils}
+
+//! \}
+
+ASMJIT_END_NAMESPACE
+
+#endif // ASMJIT_CORE_ARCHTRAITS_H_INCLUDED