asmjit 0.2.0 → 0.2.1

data/ext/asmjit/asmjit/src/asmjit/arm/a64rapass_p.h

@@ -0,0 +1,105 @@
+// This file is part of AsmJit project <https://asmjit.com>
+//
+// See asmjit.h or LICENSE.md for license and copyright information
+// SPDX-License-Identifier: Zlib
+
+#ifndef ASMJIT_ARM_A64RAPASS_P_H_INCLUDED
+#define ASMJIT_ARM_A64RAPASS_P_H_INCLUDED
+
+#include "../core/api-config.h"
+#ifndef ASMJIT_NO_COMPILER
+
+#include "../core/compiler.h"
+#include "../core/rabuilders_p.h"
+#include "../core/rapass_p.h"
+#include "../arm/a64assembler.h"
+#include "../arm/a64compiler.h"
+#include "../arm/a64emithelper_p.h"
+
+ASMJIT_BEGIN_SUB_NAMESPACE(a64)
+
+//! \cond INTERNAL
+//! \addtogroup asmjit_a64
+//! \{
+
+//! ARM register allocation pass.
+//!
+//! Takes care of generating function prologs and epilogs, and also performs
+//! register allocation.
+class ARMRAPass : public BaseRAPass {
+public:
+  ASMJIT_NONCOPYABLE(ARMRAPass)
+  typedef BaseRAPass Base;
+
+  EmitHelper _emitHelper;
+
+  //! \name Construction & Destruction
+  //! \{
+
+  ARMRAPass() noexcept;
+  virtual ~ARMRAPass() noexcept;
+
+  //! \}
+
+  //! \name Accessors
+  //! \{
+
+  //! Returns the compiler casted to `arm::Compiler`.
+  inline Compiler* cc() const noexcept { return static_cast<Compiler*>(_cb); }
+
+  //! Returns emit helper.
+  inline EmitHelper* emitHelper() noexcept { return &_emitHelper; }
+
+  //! \}
+
+  //! \name Events
+  //! \{
+
+  void onInit() noexcept override;
+  void onDone() noexcept override;
+
+  //! \}
+
+  //! \name CFG
+  //! \{
+
+  Error buildCFG() noexcept override;
+
+  //! \}
+
+  //! \name Rewrite
+  //! \{
+
+  Error _rewrite(BaseNode* first, BaseNode* stop) noexcept override;
+
+  //! \}
+
+  //! \name Prolog & Epilog
+  //! \{
+
+  Error updateStackFrame() noexcept override;
+
+  //! \}
+
+  //! \name Emit Helpers
+  //! \{
+
+  Error emitMove(uint32_t workId, uint32_t dstPhysId, uint32_t srcPhysId) noexcept override;
+  Error emitSwap(uint32_t aWorkId, uint32_t aPhysId, uint32_t bWorkId, uint32_t bPhysId) noexcept override;
+
+  Error emitLoad(uint32_t workId, uint32_t dstPhysId) noexcept override;
+  Error emitSave(uint32_t workId, uint32_t srcPhysId) noexcept override;
+
+  Error emitJump(const Label& label) noexcept override;
+  Error emitPreCall(InvokeNode* invokeNode) noexcept override;
+
+  //! \}
+};
+
+//! \}
+//! \endcond
+
+ASMJIT_END_SUB_NAMESPACE
+
+#endif // !ASMJIT_NO_COMPILER
+#endif // ASMJIT_ARM_A64RAPASS_P_H_INCLUDED

data/ext/asmjit/asmjit/src/asmjit/arm/a64utils.h

@@ -0,0 +1,179 @@
+// This file is part of AsmJit project <https://asmjit.com>
+//
+// See asmjit.h or LICENSE.md for license and copyright information
+// SPDX-License-Identifier: Zlib
+
+#ifndef ASMJIT_ARM_A64UTILS_H_INCLUDED
+#define ASMJIT_ARM_A64UTILS_H_INCLUDED
+
+#include "../arm/a64globals.h"
+
+ASMJIT_BEGIN_SUB_NAMESPACE(a64)
+
+//! \addtogroup asmjit_a64
+//! \{
+
+//! Public utilities and helpers for targeting AArch64 architecture.
+namespace Utils {
+
+//! Decomposed fields of a logical immediate value (AArch64).
+struct LogicalImm {
+  uint32_t n;
+  uint32_t s;
+  uint32_t r;
+};
+
+//! Encodes the given `imm` value of the given `width` to a logical immediate value represented as N, S, and R fields
+//! and writes these fields to `out`.
+//!
+//! Encoding Table:
+//!
+//! ```
+//! +---+--------+--------+------+
+//! | N |  ImmS  |  ImmR  | Size |
+//! +---+--------+--------+------+
+//! | 1 | ssssss | rrrrrr |  64  |
+//! | 0 | 0sssss | .rrrrr |  32  |
+//! | 0 | 10ssss | ..rrrr |  16  |
+//! | 0 | 110sss | ...rrr |  8   |
+//! | 0 | 1110ss | ....rr |  4   |
+//! | 0 | 11110s | .....r |  2   |
+//! +---+--------+--------+------+
+//! ```
+ASMJIT_MAYBE_UNUSED
+static bool encodeLogicalImm(uint64_t imm, uint32_t width, a64::Utils::LogicalImm* out) noexcept {
+  // Determine the element width, which must be 2, 4, 8, 16, 32, or 64 bits.
+  do {
+    width /= 2;
+    uint64_t mask = (uint64_t(1) << width) - 1u;
+    if ((imm & mask) != ((imm >> width) & mask)) {
+      width *= 2;
+      break;
+    }
+  } while (width > 2);
+
+  // Patterns of all zeros and all ones are not encodable.
+  uint64_t lsbMask = Support::lsbMask<uint64_t>(width);
+  imm &= lsbMask;
+
+  if (imm == 0 || imm == lsbMask)
+    return false;
+
+  // Inspect the pattern and get the most important bit indexes.
+  //
+  //         oIndex <-+      +-> zIndex
+  //                  |      |
+  // |..zeros..|oCount|zCount|..ones..|
+  // |000000000|111111|000000|11111111|
+
+  uint32_t zIndex = Support::ctz(~imm);
+  uint64_t zImm = imm ^ ((uint64_t(1) << zIndex) - 1);
+  uint32_t zCount = (zImm ? Support::ctz(zImm) : width) - zIndex;
+
+  uint32_t oIndex = zIndex + zCount;
+  uint64_t oImm = ~(zImm ^ Support::lsbMask<uint64_t>(oIndex));
+  uint32_t oCount = (oImm ? Support::ctz(oImm) : width) - (oIndex);
+
+  // Verify whether the bit-pattern is encodable.
+  uint64_t mustBeZero = oImm ^ ~Support::lsbMask<uint64_t>(oIndex + oCount);
+  if (mustBeZero != 0 || (zIndex > 0 && width - (oIndex + oCount) != 0))
+    return false;
+
+  out->n = width == 64;
+  out->s = (oCount + zIndex - 1) | (Support::neg(width * 2) & 0x3F);
+  out->r = width - oIndex;
+  return true;
+}
+
+//! Returns true if the given `imm` value is encodable as a logical immediate. The `width` argument describes the
+//! width of the operation, and must be either 32 or 64. This function can be used to test whether an immediate
+//! value can be used with AND, ANDS, BIC, BICS, EON, EOR, ORN, and ORR instruction.
+ASMJIT_MAYBE_UNUSED
+static inline bool isLogicalImm(uint64_t imm, uint32_t width) noexcept {
+  LogicalImm dummy;
+  return encodeLogicalImm(imm, width, &dummy);
+}
+
+//! Returns true if the given `imm` value is a byte mask. Byte mask has each byte part of the value set to either
+//! 0x00 or 0xFF. Some ARM instructions accept immediates that form a byte-mask and this function can be used to
+//! verify that the immediate is encodable before using the value.
+template<typename T>
+static inline bool isByteMaskImm8(const T& imm) noexcept {
+  constexpr T kMask = T(0x0101010101010101 & Support::allOnes<T>());
+  return imm == (imm & kMask) * T(255);
+}
+
+//! \cond
+//! A generic implementation that checjs whether a floating point value can be converted to ARM Imm8.
+template<typename T, uint32_t kNumBBits, uint32_t kNumCDEFGHBits, uint32_t kNumZeroBits>
+static inline bool isFPImm8Generic(T val) noexcept {
+  constexpr uint32_t kAllBsMask = Support::lsbMask<uint32_t>(kNumBBits);
+  constexpr uint32_t kB0Pattern = Support::bitMask(kNumBBits - 1);
+  constexpr uint32_t kB1Pattern = kAllBsMask ^ kB0Pattern;
+
+  T immZ = val & Support::lsbMask<T>(kNumZeroBits);
+  uint32_t immB = uint32_t(val >> (kNumZeroBits + kNumCDEFGHBits)) & kAllBsMask;
+
+  // ImmZ must be all zeros and ImmB must either be B0 or B1 pattern.
+  return immZ == 0 && (immB == kB0Pattern || immB == kB1Pattern);
+}
+//! \endcond
+
+//! Returns true if the given half precision floating point `val` can be encoded as ARM IMM8 value, which represents
+//! a limited set of floating point immediate values, which can be used with FMOV instruction.
+//!
+//! The floating point must have bits distributed in the following way:
+//!
+//! ```
+//! [aBbbcdef|gh000000]
+//! ```
+static inline bool isFP16Imm8(uint32_t val) noexcept { return isFPImm8Generic<uint32_t, 3, 6, 6>(val); }
+
+//! Returns true if the given single precision floating point `val` can be encoded as ARM IMM8 value, which represents
+//! a limited set of floating point immediate values, which can be used with FMOV instruction.
+//!
+//! The floating point must have bits distributed in the following way:
+//!
+//! ```
+//! [aBbbbbbc|defgh000|00000000|00000000]
+//! ```
+static inline bool isFP32Imm8(uint32_t val) noexcept { return isFPImm8Generic<uint32_t, 6, 6, 19>(val); }
+//! \overload
+static inline bool isFP32Imm8(float val) noexcept { return isFP32Imm8(Support::bitCast<uint32_t>(val)); }
+
+//! Returns true if the given double precision floating point `val` can be encoded as ARM IMM8 value, which represents
+//! a limited set of floating point immediate values, which can be used with FMOV instruction.
+//!
+//! The floating point must have bits distributed in the following way:
+//!
+//! ```
+//! [aBbbbbbb|bbcdefgh|00000000|00000000|00000000|00000000|00000000|00000000]
+//! ```
+static inline bool isFP64Imm8(uint64_t val) noexcept { return isFPImm8Generic<uint64_t, 9, 6, 48>(val); }
+//! \overload
+static inline bool isFP64Imm8(double val) noexcept { return isFP64Imm8(Support::bitCast<uint64_t>(val)); }
+
+//! \cond
+template<typename T, uint32_t kNumBBits, uint32_t kNumCDEFGHBits, uint32_t kNumZeroBits>
+static inline uint32_t encodeFPToImm8Generic(T val) noexcept {
+  uint32_t bits = uint32_t(val >> kNumZeroBits);
+  return ((bits >> (kNumBBits + kNumCDEFGHBits - 7)) & 0x80u) | (bits & 0x7F);
+}
+//! \endcond
+
+//! Encodes a double precision floating point value into IMM8 format.
+//!
+//! \note This function expects that `isFP64Imm8(val) == true` so it doesn't perform any checks of the value and just
+//! rearranges some bits into Imm8 order.
+static inline uint32_t encodeFP64ToImm8(uint64_t val) noexcept { return encodeFPToImm8Generic<uint64_t, 9, 6, 48>(val); }
+//! \overload
+static inline uint32_t encodeFP64ToImm8(double val) noexcept { return encodeFP64ToImm8(Support::bitCast<uint64_t>(val)); }
+
+} // {Utils}
+
+//! \}
+
+ASMJIT_END_SUB_NAMESPACE
+
+#endif // ASMJIT_ARM_A64UTILS_H_INCLUDED
+

data/ext/asmjit/asmjit/src/asmjit/arm/armformatter.cpp

@@ -0,0 +1,143 @@
+// This file is part of AsmJit project <https://asmjit.com>
+//
+// See asmjit.h or LICENSE.md for license and copyright information
+// SPDX-License-Identifier: Zlib
+
+#include "../core/api-build_p.h"
+#ifndef ASMJIT_NO_LOGGING
+
+#include "../core/misc_p.h"
+#include "../core/support.h"
+#include "../arm/armformatter_p.h"
+#include "../arm/armoperand.h"
+#include "../arm/a64instapi_p.h"
+#include "../arm/a64instdb_p.h"
+
+#ifndef ASMJIT_NO_COMPILER
+  #include "../core/compiler.h"
+#endif
+
+ASMJIT_BEGIN_SUB_NAMESPACE(arm)
+
+// arm::FormatterInternal - Format Feature
+// =======================================
+
+Error FormatterInternal::formatFeature(String& sb, uint32_t featureId) noexcept {
+  // @EnumStringBegin{"enum": "CpuFeatures::ARM", "output": "sFeature", "strip": "k"}@
+  static const char sFeatureString[] =
+    "None\0"
+    "THUMB\0"
+    "THUMBv2\0"
+    "ARMv6\0"
+    "ARMv7\0"
+    "ARMv8a\0"
+    "ARMv8_1a\0"
+    "ARMv8_2a\0"
+    "ARMv8_3a\0"
+    "ARMv8_4a\0"
+    "ARMv8_5a\0"
+    "ARMv8_6a\0"
+    "ARMv8_7a\0"
+    "VFPv2\0"
+    "VFPv3\0"
+    "VFPv4\0"
+    "VFP_D32\0"
+    "AES\0"
+    "ALTNZCV\0"
+    "ASIMD\0"
+    "BF16\0"
+    "BTI\0"
+    "CPUID\0"
+    "CRC32\0"
+    "DGH\0"
+    "DIT\0"
+    "DOTPROD\0"
+    "EDSP\0"
+    "FCMA\0"
+    "FJCVTZS\0"
+    "FLAGM\0"
+    "FP16CONV\0"
+    "FP16FML\0"
+    "FP16FULL\0"
+    "FRINT\0"
+    "I8MM\0"
+    "IDIVA\0"
+    "IDIVT\0"
+    "LSE\0"
+    "MTE\0"
+    "RCPC_IMMO\0"
+    "RDM\0"
+    "PMU\0"
+    "PMULL\0"
+    "RNG\0"
+    "SB\0"
+    "SHA1\0"
+    "SHA2\0"
+    "SHA3\0"
+    "SHA512\0"
+    "SM3\0"
+    "SM4\0"
+    "SSBS\0"
+    "SVE\0"
+    "SVE_BF16\0"
+    "SVE_F32MM\0"
+    "SVE_F64MM\0"
+    "SVE_I8MM\0"
+    "SVE_PMULL\0"
+    "SVE2\0"
+    "SVE2_AES\0"
+    "SVE2_BITPERM\0"
+    "SVE2_SHA3\0"
+    "SVE2_SM4\0"
+    "TME\0"
+    "<Unknown>\0";
+
+  static const uint16_t sFeatureIndex[] = {
+    0, 5, 11, 19, 25, 31, 38, 47, 56, 65, 74, 83, 92, 101, 107, 113, 119, 127,
+    131, 139, 145, 150, 154, 160, 166, 170, 174, 182, 187, 192, 200, 206, 215,
+    223, 232, 238, 243, 249, 255, 259, 263, 273, 277, 281, 287, 291, 294, 299,
+    304, 309, 316, 320, 324, 329, 333, 342, 352, 362, 371, 381, 386, 395, 408,
+    418, 427, 431
+  };
+  // @EnumStringEnd@
+
+  return sb.append(sFeatureString + sFeatureIndex[Support::min<uint32_t>(featureId, uint32_t(CpuFeatures::ARM::kMaxValue) + 1)]);
+}
+
+// arm::FormatterInternal - Format Constants
+// =========================================
+
+ASMJIT_FAVOR_SIZE Error FormatterInternal::formatCondCode(String& sb, CondCode cc) noexcept {
+  static const char condCodeData[] =
+    "al\0" "na\0"
+    "eq\0" "ne\0"
+    "cs\0" "cc\0" "mi\0" "pl\0" "vs\0" "vc\0"
+    "hi\0" "ls\0" "ge\0" "lt\0" "gt\0" "le\0"
+    "<Unknown>";
+  return sb.append(condCodeData + Support::min<uint32_t>(uint32_t(cc), 16u) * 3);
+}
+
+ASMJIT_FAVOR_SIZE Error FormatterInternal::formatShiftOp(String& sb, ShiftOp shiftOp) noexcept {
+  const char* str = "<Unknown>";
+  switch (shiftOp) {
+    case ShiftOp::kLSL: str = "lsl"; break;
+    case ShiftOp::kLSR: str = "lsr"; break;
+    case ShiftOp::kASR: str = "asr"; break;
+    case ShiftOp::kROR: str = "ror"; break;
+    case ShiftOp::kRRX: str = "rrx"; break;
+    case ShiftOp::kMSL: str = "msl"; break;
+    case ShiftOp::kUXTB: str = "uxtb"; break;
+    case ShiftOp::kUXTH: str = "uxth"; break;
+    case ShiftOp::kUXTW: str = "uxtw"; break;
+    case ShiftOp::kUXTX: str = "uxtx"; break;
+    case ShiftOp::kSXTB: str = "sxtb"; break;
+    case ShiftOp::kSXTH: str = "sxth"; break;
+    case ShiftOp::kSXTW: str = "sxtw"; break;
+    case ShiftOp::kSXTX: str = "sxtx"; break;
+  }
+  return sb.append(str);
+}
+
+ASMJIT_END_SUB_NAMESPACE
+
+#endif // !ASMJIT_NO_LOGGING

data/ext/asmjit/asmjit/src/asmjit/arm/armformatter_p.h

@@ -0,0 +1,44 @@
+// This file is part of AsmJit project <https://asmjit.com>
+//
+// See asmjit.h or LICENSE.md for license and copyright information
+// SPDX-License-Identifier: Zlib
+
+#ifndef ASMJIT_ARM_ARMFORMATTER_P_H_INCLUDED
+#define ASMJIT_ARM_ARMFORMATTER_P_H_INCLUDED
+
+#include "../core/api-config.h"
+#ifndef ASMJIT_NO_LOGGING
+
+#include "../core/formatter.h"
+#include "../core/string.h"
+#include "../arm/armglobals.h"
+
+ASMJIT_BEGIN_SUB_NAMESPACE(arm)
+
+//! \cond INTERNAL
+//! \addtogroup asmjit_arm
+//! \{
+
+namespace FormatterInternal {
+
+Error ASMJIT_CDECL formatFeature(
+  String& sb,
+  uint32_t featureId) noexcept;
+
+Error ASMJIT_CDECL formatCondCode(
+  String& sb,
+  CondCode cc) noexcept;
+
+Error ASMJIT_CDECL formatShiftOp(
+  String& sb,
+  ShiftOp shiftOp) noexcept;
+
+} // {FormatterInternal}
+
+//! \}
+//! \endcond
+
+ASMJIT_END_SUB_NAMESPACE
+
+#endif // !ASMJIT_NO_LOGGING
+#endif // ASMJIT_ARM_ARMFORMATTER_P_H_INCLUDED

data/ext/asmjit/asmjit/src/asmjit/arm/armglobals.h

@@ -0,0 +1,21 @@
+// This file is part of AsmJit project <https://asmjit.com>
+//
+// See asmjit.h or LICENSE.md for license and copyright information
+// SPDX-License-Identifier: Zlib
+
+#ifndef ASMJIT_ARM_ARMGLOBALS_H_INCLUDED
+#define ASMJIT_ARM_ARMGLOBALS_H_INCLUDED
+
+#include "../core/archcommons.h"
+#include "../core/inst.h"
+
+//! \namespace asmjit::arm
+//! \ingroup asmjit_arm
+//!
+//! API shared between AArch32 & AArch64 backends.
+
+ASMJIT_BEGIN_SUB_NAMESPACE(arm)
+
+ASMJIT_END_SUB_NAMESPACE
+
+#endif // ASMJIT_ARM_ARMGLOBALS_H_INCLUDED