amaterasu 0.6.0
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- checksums.yaml +7 -0
- data/.gitignore +14 -0
- data/.rspec +1 -0
- data/.rubocop.yml +54 -0
- data/Gemfile +32 -0
- data/Gemfile.lock +267 -0
- data/LICENSE +21 -0
- data/README.md +115 -0
- data/Steepfile +7 -0
- data/exe/amaterasu +23 -0
- data/lib/amaterasu/cartridge/mbc1.rb +56 -0
- data/lib/amaterasu/cartridge/rom.rb +118 -0
- data/lib/amaterasu/cartridge.rb +68 -0
- data/lib/amaterasu/cli.rb +60 -0
- data/lib/amaterasu/emulator.rb +121 -0
- data/lib/amaterasu/game_boy/apu.rb +12 -0
- data/lib/amaterasu/game_boy/bus.rb +161 -0
- data/lib/amaterasu/game_boy/cpu/instructions/adc.rb +64 -0
- data/lib/amaterasu/game_boy/cpu/instructions/add16.rb +73 -0
- data/lib/amaterasu/game_boy/cpu/instructions/add8.rb +63 -0
- data/lib/amaterasu/game_boy/cpu/instructions/and.rb +62 -0
- data/lib/amaterasu/game_boy/cpu/instructions/base.rb +38 -0
- data/lib/amaterasu/game_boy/cpu/instructions/call.rb +48 -0
- data/lib/amaterasu/game_boy/cpu/instructions/cb_bit.rb +52 -0
- data/lib/amaterasu/game_boy/cpu/instructions/cb_res.rb +49 -0
- data/lib/amaterasu/game_boy/cpu/instructions/cb_rl.rb +70 -0
- data/lib/amaterasu/game_boy/cpu/instructions/cb_rlc.rb +68 -0
- data/lib/amaterasu/game_boy/cpu/instructions/cb_rr.rb +70 -0
- data/lib/amaterasu/game_boy/cpu/instructions/cb_rrc.rb +68 -0
- data/lib/amaterasu/game_boy/cpu/instructions/cb_set.rb +51 -0
- data/lib/amaterasu/game_boy/cpu/instructions/cb_sla.rb +69 -0
- data/lib/amaterasu/game_boy/cpu/instructions/cb_sra.rb +71 -0
- data/lib/amaterasu/game_boy/cpu/instructions/cb_srl.rb +69 -0
- data/lib/amaterasu/game_boy/cpu/instructions/cb_swap.rb +67 -0
- data/lib/amaterasu/game_boy/cpu/instructions/cp.rb +61 -0
- data/lib/amaterasu/game_boy/cpu/instructions/daa.rb +59 -0
- data/lib/amaterasu/game_boy/cpu/instructions/dec.rb +64 -0
- data/lib/amaterasu/game_boy/cpu/instructions/di.rb +21 -0
- data/lib/amaterasu/game_boy/cpu/instructions/ei.rb +19 -0
- data/lib/amaterasu/game_boy/cpu/instructions/halt.rb +19 -0
- data/lib/amaterasu/game_boy/cpu/instructions/inc.rb +64 -0
- data/lib/amaterasu/game_boy/cpu/instructions/jp.rb +54 -0
- data/lib/amaterasu/game_boy/cpu/instructions/jr.rb +45 -0
- data/lib/amaterasu/game_boy/cpu/instructions/ld16.rb +79 -0
- data/lib/amaterasu/game_boy/cpu/instructions/ld8.rb +210 -0
- data/lib/amaterasu/game_boy/cpu/instructions/ldh.rb +61 -0
- data/lib/amaterasu/game_boy/cpu/instructions/misc.rb +53 -0
- data/lib/amaterasu/game_boy/cpu/instructions/nop.rb +19 -0
- data/lib/amaterasu/game_boy/cpu/instructions/or.rb +56 -0
- data/lib/amaterasu/game_boy/cpu/instructions/pop.rb +39 -0
- data/lib/amaterasu/game_boy/cpu/instructions/push.rb +43 -0
- data/lib/amaterasu/game_boy/cpu/instructions/ret.rb +70 -0
- data/lib/amaterasu/game_boy/cpu/instructions/rotate.rb +120 -0
- data/lib/amaterasu/game_boy/cpu/instructions/rst.rb +33 -0
- data/lib/amaterasu/game_boy/cpu/instructions/sbc.rb +64 -0
- data/lib/amaterasu/game_boy/cpu/instructions/stop.rb +19 -0
- data/lib/amaterasu/game_boy/cpu/instructions/sub.rb +63 -0
- data/lib/amaterasu/game_boy/cpu/instructions/xor.rb +60 -0
- data/lib/amaterasu/game_boy/cpu/instructions.rb +600 -0
- data/lib/amaterasu/game_boy/cpu/registers.rb +264 -0
- data/lib/amaterasu/game_boy/cpu.rb +232 -0
- data/lib/amaterasu/game_boy/dma.rb +114 -0
- data/lib/amaterasu/game_boy/interrupts.rb +108 -0
- data/lib/amaterasu/game_boy/joypad.rb +127 -0
- data/lib/amaterasu/game_boy/oam/sprite.rb +106 -0
- data/lib/amaterasu/game_boy/oam.rb +29 -0
- data/lib/amaterasu/game_boy/ppu/modes/disabled.rb +29 -0
- data/lib/amaterasu/game_boy/ppu/modes/h_blank.rb +45 -0
- data/lib/amaterasu/game_boy/ppu/modes/oam_scan.rb +93 -0
- data/lib/amaterasu/game_boy/ppu/modes/rendering/bg_win_fetcher.rb +204 -0
- data/lib/amaterasu/game_boy/ppu/modes/rendering/pixel_emitter.rb +83 -0
- data/lib/amaterasu/game_boy/ppu/modes/rendering/pixel_fifo.rb +70 -0
- data/lib/amaterasu/game_boy/ppu/modes/rendering/sprite_fetcher.rb +140 -0
- data/lib/amaterasu/game_boy/ppu/modes/rendering.rb +108 -0
- data/lib/amaterasu/game_boy/ppu/modes/v_blank.rb +43 -0
- data/lib/amaterasu/game_boy/ppu/modes.rb +22 -0
- data/lib/amaterasu/game_boy/ppu/registers/lcd_control.rb +57 -0
- data/lib/amaterasu/game_boy/ppu/registers/lcd_status.rb +88 -0
- data/lib/amaterasu/game_boy/ppu/registers.rb +131 -0
- data/lib/amaterasu/game_boy/ppu.rb +207 -0
- data/lib/amaterasu/game_boy/ram.rb +70 -0
- data/lib/amaterasu/game_boy/serial.rb +91 -0
- data/lib/amaterasu/game_boy/timer.rb +230 -0
- data/lib/amaterasu/game_boy/vram/tile.rb +68 -0
- data/lib/amaterasu/game_boy/vram/tile_data.rb +52 -0
- data/lib/amaterasu/game_boy/vram/tile_map.rb +71 -0
- data/lib/amaterasu/game_boy/vram.rb +51 -0
- data/lib/amaterasu/hal/console.rb +23 -0
- data/lib/amaterasu/hal/sdl2/bindings.rb +59 -0
- data/lib/amaterasu/hal/sdl2.rb +127 -0
- data/lib/amaterasu/utils/bit_ops.rb +22 -0
- data/lib/amaterasu.rb +13 -0
- data/sig/akane/cartridge/rom.rbs +29 -0
- data/sig/akane/cartridge.rbs +12 -0
- data/sig/akane/cli.rbs +16 -0
- data/sig/akane/emulator.rbs +19 -0
- data/sig/akane/game_boy/apu.rbs +7 -0
- data/sig/akane/game_boy/bus.rbs +25 -0
- data/sig/akane/game_boy/cpu/instructions/adc.rbs +18 -0
- data/sig/akane/game_boy/cpu/instructions/add16.rbs +19 -0
- data/sig/akane/game_boy/cpu/instructions/add8.rbs +18 -0
- data/sig/akane/game_boy/cpu/instructions/and.rbs +18 -0
- data/sig/akane/game_boy/cpu/instructions/base.rbs +20 -0
- data/sig/akane/game_boy/cpu/instructions/call.rbs +18 -0
- data/sig/akane/game_boy/cpu/instructions/cb_bit.rbs +20 -0
- data/sig/akane/game_boy/cpu/instructions/cb_res.rbs +19 -0
- data/sig/akane/game_boy/cpu/instructions/cb_rl.rbs +21 -0
- data/sig/akane/game_boy/cpu/instructions/cb_rlc.rbs +21 -0
- data/sig/akane/game_boy/cpu/instructions/cb_rr.rbs +21 -0
- data/sig/akane/game_boy/cpu/instructions/cb_rrc.rbs +21 -0
- data/sig/akane/game_boy/cpu/instructions/cb_set.rbs +20 -0
- data/sig/akane/game_boy/cpu/instructions/cb_sla.rbs +21 -0
- data/sig/akane/game_boy/cpu/instructions/cb_sra.rbs +21 -0
- data/sig/akane/game_boy/cpu/instructions/cb_srl.rbs +21 -0
- data/sig/akane/game_boy/cpu/instructions/cb_swap.rbs +21 -0
- data/sig/akane/game_boy/cpu/instructions/cp.rbs +18 -0
- data/sig/akane/game_boy/cpu/instructions/daa.rbs +17 -0
- data/sig/akane/game_boy/cpu/instructions/dec.rbs +19 -0
- data/sig/akane/game_boy/cpu/instructions/di.rbs +13 -0
- data/sig/akane/game_boy/cpu/instructions/ei.rbs +13 -0
- data/sig/akane/game_boy/cpu/instructions/halt.rbs +13 -0
- data/sig/akane/game_boy/cpu/instructions/inc.rbs +19 -0
- data/sig/akane/game_boy/cpu/instructions/jp.rbs +18 -0
- data/sig/akane/game_boy/cpu/instructions/jr.rbs +18 -0
- data/sig/akane/game_boy/cpu/instructions/ld16.rbs +18 -0
- data/sig/akane/game_boy/cpu/instructions/ld8.rbs +31 -0
- data/sig/akane/game_boy/cpu/instructions/ldh.rbs +23 -0
- data/sig/akane/game_boy/cpu/instructions/misc.rbs +20 -0
- data/sig/akane/game_boy/cpu/instructions/nop.rbs +13 -0
- data/sig/akane/game_boy/cpu/instructions/or.rbs +18 -0
- data/sig/akane/game_boy/cpu/instructions/pop.rbs +17 -0
- data/sig/akane/game_boy/cpu/instructions/push.rbs +18 -0
- data/sig/akane/game_boy/cpu/instructions/ret.rbs +20 -0
- data/sig/akane/game_boy/cpu/instructions/rotate.rbs +23 -0
- data/sig/akane/game_boy/cpu/instructions/rst.rbs +17 -0
- data/sig/akane/game_boy/cpu/instructions/sbc.rbs +19 -0
- data/sig/akane/game_boy/cpu/instructions/stop.rbs +13 -0
- data/sig/akane/game_boy/cpu/instructions/sub.rbs +18 -0
- data/sig/akane/game_boy/cpu/instructions/xor.rbs +19 -0
- data/sig/akane/game_boy/cpu/instructions.rbs +12 -0
- data/sig/akane/game_boy/cpu/registers.rbs +56 -0
- data/sig/akane/game_boy/cpu.rbs +39 -0
- data/sig/akane/game_boy/interrupts.rbs +28 -0
- data/sig/akane/game_boy/joypad.rbs +25 -0
- data/sig/akane/game_boy/oam/sprite.rbs +30 -0
- data/sig/akane/game_boy/ppu/modes/disabled.rbs +17 -0
- data/sig/akane/game_boy/ppu/modes/h_blank.rbs +20 -0
- data/sig/akane/game_boy/ppu/modes/oam_scan.rbs +28 -0
- data/sig/akane/game_boy/ppu/modes/rendering.rbs +26 -0
- data/sig/akane/game_boy/ppu/modes/v_blank.rbs +20 -0
- data/sig/akane/game_boy/ppu/modes.rbs +13 -0
- data/sig/akane/game_boy/ppu.rbs +59 -0
- data/sig/akane/game_boy/ram.rbs +16 -0
- data/sig/akane/game_boy/serial.rbs +21 -0
- data/sig/akane/game_boy/timer.rbs +30 -0
- data/sig/akane/utils/bit_ops.rbs +11 -0
- data/sig/akane.rbs +3 -0
- metadata +226 -0
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# frozen_string_literal: true
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# rubocop:disable Metrics/MethodLength, Metrics/ModuleLength
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module Amaterasu
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module GameBoy
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class Cpu
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# Responsible to group all instruction types and load the CPU instructions array.
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module Instructions
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def self.load_base_instructions(cpu:)
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instructions = Array.new(256)
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# Opcodes 0x00 - 0x0F
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instructions[0x00] = Nop.new(cpu:)
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instructions[0x01] = Ld16.new(cpu:, target: :bc, source: :imm16)
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instructions[0x02] = Ld8.new(cpu:, target: :mem_bc, source: :a)
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instructions[0x03] = Inc.new(cpu:, operand: :bc)
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instructions[0x04] = Inc.new(cpu:, operand: :b)
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instructions[0x05] = Dec.new(cpu:, operand: :b)
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instructions[0x06] = Ld8.new(cpu:, target: :b, source: :imm8)
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instructions[0x07] = Rotate.new(cpu:, operation: :rlca)
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instructions[0x08] = Ld16.new(cpu:, target: :mem_imm16, source: :sp)
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instructions[0x09] = Add16.new(cpu:, target: :hl, source: :bc)
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instructions[0x0A] = Ld8.new(cpu:, target: :a, source: :mem_bc)
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instructions[0x0B] = Dec.new(cpu:, operand: :bc)
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instructions[0x0C] = Inc.new(cpu:, operand: :c)
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instructions[0x0D] = Dec.new(cpu:, operand: :c)
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instructions[0x0E] = Ld8.new(cpu:, target: :c, source: :imm8)
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instructions[0x0F] = Rotate.new(cpu:, operation: :rrca)
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# Opcodes 0x10 - 0x1F
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instructions[0x10] = Stop.new(cpu:)
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instructions[0x11] = Ld16.new(cpu:, target: :de, source: :imm16)
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instructions[0x12] = Ld8.new(cpu:, target: :mem_de, source: :a)
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instructions[0x13] = Inc.new(cpu:, operand: :de)
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instructions[0x14] = Inc.new(cpu:, operand: :d)
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instructions[0x15] = Dec.new(cpu:, operand: :d)
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instructions[0x16] = Ld8.new(cpu:, target: :d, source: :imm8)
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instructions[0x17] = Rotate.new(cpu:, operation: :rla)
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instructions[0x18] = Jr.new(cpu:)
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instructions[0x19] = Add16.new(cpu:, target: :hl, source: :de)
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instructions[0x1A] = Ld8.new(cpu:, target: :a, source: :mem_de)
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instructions[0x1B] = Dec.new(cpu:, operand: :de)
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instructions[0x1C] = Inc.new(cpu:, operand: :e)
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instructions[0x1D] = Dec.new(cpu:, operand: :e)
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instructions[0x1E] = Ld8.new(cpu:, target: :e, source: :imm8)
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instructions[0x1F] = Rotate.new(cpu:, operation: :rra)
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# Opcodes 0x20 - 0x2F
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instructions[0x20] = Jr.new(cpu:, condition: :nz)
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instructions[0x21] = Ld16.new(cpu:, target: :hl, source: :imm16)
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instructions[0x22] = Ld8.new(cpu:, target: :mem_hli, source: :a)
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instructions[0x23] = Inc.new(cpu:, operand: :hl)
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instructions[0x24] = Inc.new(cpu:, operand: :h)
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instructions[0x25] = Dec.new(cpu:, operand: :h)
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instructions[0x26] = Ld8.new(cpu:, target: :h, source: :imm8)
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instructions[0x27] = Daa.new(cpu:)
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instructions[0x28] = Jr.new(cpu:, condition: :z)
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instructions[0x29] = Add16.new(cpu:, target: :hl, source: :hl)
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instructions[0x2A] = Ld8.new(cpu:, target: :a, source: :mem_hli)
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instructions[0x2B] = Dec.new(cpu:, operand: :hl)
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instructions[0x2C] = Inc.new(cpu:, operand: :l)
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instructions[0x2D] = Dec.new(cpu:, operand: :l)
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instructions[0x2E] = Ld8.new(cpu:, target: :l, source: :imm8)
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instructions[0x2F] = Misc.new(cpu:, operation: :cpl)
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# Opcodes 0x30 - 0x3F
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instructions[0x30] = Jr.new(cpu:, condition: :nc)
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instructions[0x31] = Ld16.new(cpu:, target: :sp, source: :imm16)
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instructions[0x32] = Ld8.new(cpu:, target: :mem_hld, source: :a)
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instructions[0x33] = Inc.new(cpu:, operand: :sp)
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instructions[0x34] = Inc.new(cpu:, operand: :mem_hl)
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instructions[0x35] = Dec.new(cpu:, operand: :mem_hl)
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instructions[0x36] = Ld8.new(cpu:, target: :mem_hl, source: :imm8)
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instructions[0x37] = Misc.new(cpu:, operation: :scf)
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instructions[0x38] = Jr.new(cpu:, condition: :c)
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instructions[0x39] = Add16.new(cpu:, target: :hl, source: :sp)
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instructions[0x3A] = Ld8.new(cpu:, target: :a, source: :mem_hld)
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instructions[0x3B] = Dec.new(cpu:, operand: :sp)
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instructions[0x3C] = Inc.new(cpu:, operand: :a)
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instructions[0x3D] = Dec.new(cpu:, operand: :a)
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instructions[0x3E] = Ld8.new(cpu:, target: :a, source: :imm8)
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instructions[0x3F] = Misc.new(cpu:, operation: :ccf)
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# Opcodes 0x40 - 0x4F
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instructions[0x40] = Ld8.new(cpu:, target: :b, source: :b)
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instructions[0x41] = Ld8.new(cpu:, target: :b, source: :c)
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instructions[0x42] = Ld8.new(cpu:, target: :b, source: :d)
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instructions[0x43] = Ld8.new(cpu:, target: :b, source: :e)
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instructions[0x44] = Ld8.new(cpu:, target: :b, source: :h)
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instructions[0x45] = Ld8.new(cpu:, target: :b, source: :l)
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instructions[0x46] = Ld8.new(cpu:, target: :b, source: :mem_hl)
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instructions[0x47] = Ld8.new(cpu:, target: :b, source: :a)
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instructions[0x48] = Ld8.new(cpu:, target: :c, source: :b)
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instructions[0x49] = Ld8.new(cpu:, target: :c, source: :c)
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instructions[0x4A] = Ld8.new(cpu:, target: :c, source: :d)
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instructions[0x4B] = Ld8.new(cpu:, target: :c, source: :e)
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instructions[0x4C] = Ld8.new(cpu:, target: :c, source: :h)
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instructions[0x4D] = Ld8.new(cpu:, target: :c, source: :l)
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instructions[0x4E] = Ld8.new(cpu:, target: :c, source: :mem_hl)
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instructions[0x4F] = Ld8.new(cpu:, target: :c, source: :a)
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# Opcodes 0x50 - 0x5F
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instructions[0x50] = Ld8.new(cpu:, target: :d, source: :b)
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instructions[0x51] = Ld8.new(cpu:, target: :d, source: :c)
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instructions[0x52] = Ld8.new(cpu:, target: :d, source: :d)
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instructions[0x53] = Ld8.new(cpu:, target: :d, source: :e)
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107
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+
instructions[0x54] = Ld8.new(cpu:, target: :d, source: :h)
|
|
108
|
+
instructions[0x55] = Ld8.new(cpu:, target: :d, source: :l)
|
|
109
|
+
instructions[0x56] = Ld8.new(cpu:, target: :d, source: :mem_hl)
|
|
110
|
+
instructions[0x57] = Ld8.new(cpu:, target: :d, source: :a)
|
|
111
|
+
instructions[0x58] = Ld8.new(cpu:, target: :e, source: :b)
|
|
112
|
+
instructions[0x59] = Ld8.new(cpu:, target: :e, source: :c)
|
|
113
|
+
instructions[0x5A] = Ld8.new(cpu:, target: :e, source: :d)
|
|
114
|
+
instructions[0x5B] = Ld8.new(cpu:, target: :e, source: :e)
|
|
115
|
+
instructions[0x5C] = Ld8.new(cpu:, target: :e, source: :h)
|
|
116
|
+
instructions[0x5D] = Ld8.new(cpu:, target: :e, source: :l)
|
|
117
|
+
instructions[0x5E] = Ld8.new(cpu:, target: :e, source: :mem_hl)
|
|
118
|
+
instructions[0x5F] = Ld8.new(cpu:, target: :e, source: :a)
|
|
119
|
+
|
|
120
|
+
# Opcodes 0x60 - 0x6F
|
|
121
|
+
instructions[0x60] = Ld8.new(cpu:, target: :h, source: :b)
|
|
122
|
+
instructions[0x61] = Ld8.new(cpu:, target: :h, source: :c)
|
|
123
|
+
instructions[0x62] = Ld8.new(cpu:, target: :h, source: :d)
|
|
124
|
+
instructions[0x63] = Ld8.new(cpu:, target: :h, source: :e)
|
|
125
|
+
instructions[0x64] = Ld8.new(cpu:, target: :h, source: :h)
|
|
126
|
+
instructions[0x65] = Ld8.new(cpu:, target: :h, source: :l)
|
|
127
|
+
instructions[0x66] = Ld8.new(cpu:, target: :h, source: :mem_hl)
|
|
128
|
+
instructions[0x67] = Ld8.new(cpu:, target: :h, source: :a)
|
|
129
|
+
instructions[0x68] = Ld8.new(cpu:, target: :l, source: :b)
|
|
130
|
+
instructions[0x69] = Ld8.new(cpu:, target: :l, source: :c)
|
|
131
|
+
instructions[0x6A] = Ld8.new(cpu:, target: :l, source: :d)
|
|
132
|
+
instructions[0x6B] = Ld8.new(cpu:, target: :l, source: :e)
|
|
133
|
+
instructions[0x6C] = Ld8.new(cpu:, target: :l, source: :h)
|
|
134
|
+
instructions[0x6D] = Ld8.new(cpu:, target: :l, source: :l)
|
|
135
|
+
instructions[0x6E] = Ld8.new(cpu:, target: :l, source: :mem_hl)
|
|
136
|
+
instructions[0x6F] = Ld8.new(cpu:, target: :l, source: :a)
|
|
137
|
+
|
|
138
|
+
# Opcodes 0x70 - 0x7F
|
|
139
|
+
instructions[0x70] = Ld8.new(cpu:, target: :mem_hl, source: :b)
|
|
140
|
+
instructions[0x71] = Ld8.new(cpu:, target: :mem_hl, source: :c)
|
|
141
|
+
instructions[0x72] = Ld8.new(cpu:, target: :mem_hl, source: :d)
|
|
142
|
+
instructions[0x73] = Ld8.new(cpu:, target: :mem_hl, source: :e)
|
|
143
|
+
instructions[0x74] = Ld8.new(cpu:, target: :mem_hl, source: :h)
|
|
144
|
+
instructions[0x75] = Ld8.new(cpu:, target: :mem_hl, source: :l)
|
|
145
|
+
instructions[0x76] = Halt.new(cpu:)
|
|
146
|
+
instructions[0x77] = Ld8.new(cpu:, target: :mem_hl, source: :a)
|
|
147
|
+
instructions[0x78] = Ld8.new(cpu:, target: :a, source: :b)
|
|
148
|
+
instructions[0x79] = Ld8.new(cpu:, target: :a, source: :c)
|
|
149
|
+
instructions[0x7A] = Ld8.new(cpu:, target: :a, source: :d)
|
|
150
|
+
instructions[0x7B] = Ld8.new(cpu:, target: :a, source: :e)
|
|
151
|
+
instructions[0x7C] = Ld8.new(cpu:, target: :a, source: :h)
|
|
152
|
+
instructions[0x7D] = Ld8.new(cpu:, target: :a, source: :l)
|
|
153
|
+
instructions[0x7E] = Ld8.new(cpu:, target: :a, source: :mem_hl)
|
|
154
|
+
instructions[0x7F] = Ld8.new(cpu:, target: :a, source: :a)
|
|
155
|
+
|
|
156
|
+
# Opcodes 0x80 - 0x8F
|
|
157
|
+
instructions[0x80] = Add8.new(cpu:, source: :b)
|
|
158
|
+
instructions[0x81] = Add8.new(cpu:, source: :c)
|
|
159
|
+
instructions[0x82] = Add8.new(cpu:, source: :d)
|
|
160
|
+
instructions[0x83] = Add8.new(cpu:, source: :e)
|
|
161
|
+
instructions[0x84] = Add8.new(cpu:, source: :h)
|
|
162
|
+
instructions[0x85] = Add8.new(cpu:, source: :l)
|
|
163
|
+
instructions[0x86] = Add8.new(cpu:, source: :mem_hl)
|
|
164
|
+
instructions[0x87] = Add8.new(cpu:, source: :a)
|
|
165
|
+
instructions[0x88] = Adc.new(cpu:, source: :b)
|
|
166
|
+
instructions[0x89] = Adc.new(cpu:, source: :c)
|
|
167
|
+
instructions[0x8A] = Adc.new(cpu:, source: :d)
|
|
168
|
+
instructions[0x8B] = Adc.new(cpu:, source: :e)
|
|
169
|
+
instructions[0x8C] = Adc.new(cpu:, source: :h)
|
|
170
|
+
instructions[0x8D] = Adc.new(cpu:, source: :l)
|
|
171
|
+
instructions[0x8E] = Adc.new(cpu:, source: :mem_hl)
|
|
172
|
+
instructions[0x8F] = Adc.new(cpu:, source: :a)
|
|
173
|
+
|
|
174
|
+
# Opcodes 0x90 - 0x9F
|
|
175
|
+
instructions[0x90] = Sub.new(cpu:, source: :b)
|
|
176
|
+
instructions[0x91] = Sub.new(cpu:, source: :c)
|
|
177
|
+
instructions[0x92] = Sub.new(cpu:, source: :d)
|
|
178
|
+
instructions[0x93] = Sub.new(cpu:, source: :e)
|
|
179
|
+
instructions[0x94] = Sub.new(cpu:, source: :h)
|
|
180
|
+
instructions[0x95] = Sub.new(cpu:, source: :l)
|
|
181
|
+
instructions[0x96] = Sub.new(cpu:, source: :mem_hl)
|
|
182
|
+
instructions[0x97] = Sub.new(cpu:, source: :a)
|
|
183
|
+
instructions[0x98] = Sbc.new(cpu:, source: :b)
|
|
184
|
+
instructions[0x99] = Sbc.new(cpu:, source: :c)
|
|
185
|
+
instructions[0x9A] = Sbc.new(cpu:, source: :d)
|
|
186
|
+
instructions[0x9B] = Sbc.new(cpu:, source: :e)
|
|
187
|
+
instructions[0x9C] = Sbc.new(cpu:, source: :h)
|
|
188
|
+
instructions[0x9D] = Sbc.new(cpu:, source: :l)
|
|
189
|
+
instructions[0x9E] = Sbc.new(cpu:, source: :mem_hl)
|
|
190
|
+
instructions[0x9F] = Sbc.new(cpu:, source: :a)
|
|
191
|
+
|
|
192
|
+
# Opcodes 0xA0 - 0xAF
|
|
193
|
+
instructions[0xA0] = And.new(cpu:, source: :b)
|
|
194
|
+
instructions[0xA1] = And.new(cpu:, source: :c)
|
|
195
|
+
instructions[0xA2] = And.new(cpu:, source: :d)
|
|
196
|
+
instructions[0xA3] = And.new(cpu:, source: :e)
|
|
197
|
+
instructions[0xA4] = And.new(cpu:, source: :h)
|
|
198
|
+
instructions[0xA5] = And.new(cpu:, source: :l)
|
|
199
|
+
instructions[0xA6] = And.new(cpu:, source: :mem_hl)
|
|
200
|
+
instructions[0xA7] = And.new(cpu:, source: :a)
|
|
201
|
+
instructions[0xA8] = Xor.new(cpu:, source: :b)
|
|
202
|
+
instructions[0xA9] = Xor.new(cpu:, source: :c)
|
|
203
|
+
instructions[0xAA] = Xor.new(cpu:, source: :d)
|
|
204
|
+
instructions[0xAB] = Xor.new(cpu:, source: :e)
|
|
205
|
+
instructions[0xAC] = Xor.new(cpu:, source: :h)
|
|
206
|
+
instructions[0xAD] = Xor.new(cpu:, source: :l)
|
|
207
|
+
instructions[0xAE] = Xor.new(cpu:, source: :mem_hl)
|
|
208
|
+
instructions[0xAF] = Xor.new(cpu:, source: :a)
|
|
209
|
+
|
|
210
|
+
# Opcodes 0xB0 - 0xBF
|
|
211
|
+
instructions[0xB0] = Or.new(cpu:, source: :b)
|
|
212
|
+
instructions[0xB1] = Or.new(cpu:, source: :c)
|
|
213
|
+
instructions[0xB2] = Or.new(cpu:, source: :d)
|
|
214
|
+
instructions[0xB3] = Or.new(cpu:, source: :e)
|
|
215
|
+
instructions[0xB4] = Or.new(cpu:, source: :h)
|
|
216
|
+
instructions[0xB5] = Or.new(cpu:, source: :l)
|
|
217
|
+
instructions[0xB6] = Or.new(cpu:, source: :mem_hl)
|
|
218
|
+
instructions[0xB7] = Or.new(cpu:, source: :a)
|
|
219
|
+
instructions[0xB8] = Cp.new(cpu:, source: :b)
|
|
220
|
+
instructions[0xB9] = Cp.new(cpu:, source: :c)
|
|
221
|
+
instructions[0xBA] = Cp.new(cpu:, source: :d)
|
|
222
|
+
instructions[0xBB] = Cp.new(cpu:, source: :e)
|
|
223
|
+
instructions[0xBC] = Cp.new(cpu:, source: :h)
|
|
224
|
+
instructions[0xBD] = Cp.new(cpu:, source: :l)
|
|
225
|
+
instructions[0xBE] = Cp.new(cpu:, source: :mem_hl)
|
|
226
|
+
instructions[0xBF] = Cp.new(cpu:, source: :a)
|
|
227
|
+
|
|
228
|
+
# Opcodes 0xC0 - 0xCF
|
|
229
|
+
instructions[0xC0] = Ret.new(cpu:, condition: :nz)
|
|
230
|
+
instructions[0xC1] = Pop.new(cpu:, reg16: :bc)
|
|
231
|
+
instructions[0xC2] = Jp.new(cpu:, location: :imm16, condition: :nz)
|
|
232
|
+
instructions[0xC3] = Jp.new(cpu:, location: :imm16)
|
|
233
|
+
instructions[0xC4] = Call.new(cpu:, condition: :nz)
|
|
234
|
+
instructions[0xC5] = Push.new(cpu:, reg16: :bc)
|
|
235
|
+
instructions[0xC6] = Add8.new(cpu:, source: :imm8)
|
|
236
|
+
instructions[0xC7] = Rst.new(cpu:, vector: 0x00)
|
|
237
|
+
instructions[0xC8] = Ret.new(cpu:, condition: :z)
|
|
238
|
+
instructions[0xC9] = Ret.new(cpu:)
|
|
239
|
+
instructions[0xCA] = Jp.new(cpu:, location: :imm16, condition: :z)
|
|
240
|
+
# instructions[0xCB] => Handled in the cpu decode_instruction.
|
|
241
|
+
instructions[0xCC] = Call.new(cpu:, condition: :z)
|
|
242
|
+
instructions[0xCD] = Call.new(cpu:)
|
|
243
|
+
instructions[0xCE] = Adc.new(cpu:, source: :imm8)
|
|
244
|
+
instructions[0xCF] = Rst.new(cpu:, vector: 0x08)
|
|
245
|
+
|
|
246
|
+
# Opcodes 0xD0 - 0xDF
|
|
247
|
+
instructions[0xD0] = Ret.new(cpu:, condition: :nc)
|
|
248
|
+
instructions[0xD1] = Pop.new(cpu:, reg16: :de)
|
|
249
|
+
instructions[0xD2] = Jp.new(cpu:, location: :imm16, condition: :nc)
|
|
250
|
+
instructions[0xD3] = nil # not implemented in the Game Boy
|
|
251
|
+
instructions[0xD4] = Call.new(cpu:, condition: :nc)
|
|
252
|
+
instructions[0xD5] = Push.new(cpu:, reg16: :de)
|
|
253
|
+
instructions[0xD6] = Sub.new(cpu:, source: :imm8)
|
|
254
|
+
instructions[0xD7] = Rst.new(cpu:, vector: 0x10)
|
|
255
|
+
instructions[0xD8] = Ret.new(cpu:, condition: :c)
|
|
256
|
+
instructions[0xD9] = Ret.new(cpu:, enable_ime: true)
|
|
257
|
+
instructions[0xDA] = Jp.new(cpu:, location: :imm16, condition: :c)
|
|
258
|
+
instructions[0xDB] = nil # not implemented in the Game Boy
|
|
259
|
+
instructions[0xDC] = Call.new(cpu:, condition: :c)
|
|
260
|
+
instructions[0xDD] = nil # not implemented in the Game Boy
|
|
261
|
+
instructions[0xDE] = Sbc.new(cpu:, source: :imm8)
|
|
262
|
+
instructions[0xDF] = Rst.new(cpu:, vector: 0x18)
|
|
263
|
+
|
|
264
|
+
# Opcodes 0xE0 - 0xEF
|
|
265
|
+
instructions[0xE0] = Ldh.new(cpu:, target: :mem_unsig8, source: :a)
|
|
266
|
+
instructions[0xE1] = Pop.new(cpu:, reg16: :hl)
|
|
267
|
+
instructions[0xE2] = Ldh.new(cpu:, target: :mem_c, source: :a)
|
|
268
|
+
instructions[0xE3] = nil # not implemented in the Game Boy
|
|
269
|
+
instructions[0xE4] = nil # not implemented in the Game Boy
|
|
270
|
+
instructions[0xE5] = Push.new(cpu:, reg16: :hl)
|
|
271
|
+
instructions[0xE6] = And.new(cpu:, source: :imm8)
|
|
272
|
+
instructions[0xE7] = Rst.new(cpu:, vector: 0x20)
|
|
273
|
+
instructions[0xE8] = Add16.new(cpu:, target: :sp, source: :sig8)
|
|
274
|
+
instructions[0xE9] = Jp.new(cpu:, location: :hl)
|
|
275
|
+
instructions[0xEA] = Ld8.new(cpu:, target: :mem_imm16, source: :a)
|
|
276
|
+
instructions[0xEB] = nil # not implemented in the Game Boy
|
|
277
|
+
instructions[0xEC] = nil # not implemented in the Game Boy
|
|
278
|
+
instructions[0xED] = nil # not implemented in the Game Boy
|
|
279
|
+
instructions[0xEE] = Xor.new(cpu:, source: :imm8)
|
|
280
|
+
instructions[0xEF] = Rst.new(cpu:, vector: 0x28)
|
|
281
|
+
|
|
282
|
+
# Opcodes 0xF0 - 0xFF
|
|
283
|
+
instructions[0xF0] = Ldh.new(cpu:, target: :a, source: :mem_unsig8)
|
|
284
|
+
instructions[0xF1] = Pop.new(cpu:, reg16: :af)
|
|
285
|
+
instructions[0xF2] = Ldh.new(cpu:, target: :a, source: :mem_c)
|
|
286
|
+
instructions[0xF3] = Di.new(cpu:)
|
|
287
|
+
instructions[0xF4] = nil # not implemented in the Game Boy
|
|
288
|
+
instructions[0xF5] = Push.new(cpu:, reg16: :af)
|
|
289
|
+
instructions[0xF6] = Or.new(cpu:, source: :imm8)
|
|
290
|
+
instructions[0xF7] = Rst.new(cpu:, vector: 0x30)
|
|
291
|
+
instructions[0xF8] = Ld16.new(cpu:, target: :hl, source: :sp_plus_sig8)
|
|
292
|
+
instructions[0xF9] = Ld16.new(cpu:, target: :sp, source: :hl)
|
|
293
|
+
instructions[0xFA] = Ld8.new(cpu:, target: :a, source: :mem_imm16)
|
|
294
|
+
instructions[0xFB] = Ei.new(cpu:)
|
|
295
|
+
instructions[0xFC] = nil # not implemented in the Game Boy
|
|
296
|
+
instructions[0xFD] = nil # not implemented in the Game Boy
|
|
297
|
+
instructions[0xFE] = Cp.new(cpu:, source: :imm8)
|
|
298
|
+
instructions[0xFF] = Rst.new(cpu:, vector: 0x38)
|
|
299
|
+
|
|
300
|
+
instructions.freeze
|
|
301
|
+
end
|
|
302
|
+
|
|
303
|
+
def self.load_cb_instructions(cpu:)
|
|
304
|
+
cb_instructions = Array.new(256)
|
|
305
|
+
|
|
306
|
+
# Opcodes 0x00 -> 0x0F
|
|
307
|
+
cb_instructions[0x00] = CbRlc.new(cpu:, target: :b)
|
|
308
|
+
cb_instructions[0x01] = CbRlc.new(cpu:, target: :c)
|
|
309
|
+
cb_instructions[0x02] = CbRlc.new(cpu:, target: :d)
|
|
310
|
+
cb_instructions[0x03] = CbRlc.new(cpu:, target: :e)
|
|
311
|
+
cb_instructions[0x04] = CbRlc.new(cpu:, target: :h)
|
|
312
|
+
cb_instructions[0x05] = CbRlc.new(cpu:, target: :l)
|
|
313
|
+
cb_instructions[0x06] = CbRlc.new(cpu:, target: :mem_hl)
|
|
314
|
+
cb_instructions[0x07] = CbRlc.new(cpu:, target: :a)
|
|
315
|
+
cb_instructions[0x08] = CbRrc.new(cpu:, target: :b)
|
|
316
|
+
cb_instructions[0x09] = CbRrc.new(cpu:, target: :c)
|
|
317
|
+
cb_instructions[0x0A] = CbRrc.new(cpu:, target: :d)
|
|
318
|
+
cb_instructions[0x0B] = CbRrc.new(cpu:, target: :e)
|
|
319
|
+
cb_instructions[0x0C] = CbRrc.new(cpu:, target: :h)
|
|
320
|
+
cb_instructions[0x0D] = CbRrc.new(cpu:, target: :l)
|
|
321
|
+
cb_instructions[0x0E] = CbRrc.new(cpu:, target: :mem_hl)
|
|
322
|
+
cb_instructions[0x0F] = CbRrc.new(cpu:, target: :a)
|
|
323
|
+
|
|
324
|
+
# Opcodes 0x10 -> 0x1F
|
|
325
|
+
cb_instructions[0x10] = CbRl.new(cpu:, target: :b)
|
|
326
|
+
cb_instructions[0x11] = CbRl.new(cpu:, target: :c)
|
|
327
|
+
cb_instructions[0x12] = CbRl.new(cpu:, target: :d)
|
|
328
|
+
cb_instructions[0x13] = CbRl.new(cpu:, target: :e)
|
|
329
|
+
cb_instructions[0x14] = CbRl.new(cpu:, target: :h)
|
|
330
|
+
cb_instructions[0x15] = CbRl.new(cpu:, target: :l)
|
|
331
|
+
cb_instructions[0x16] = CbRl.new(cpu:, target: :mem_hl)
|
|
332
|
+
cb_instructions[0x17] = CbRl.new(cpu:, target: :a)
|
|
333
|
+
cb_instructions[0x18] = CbRr.new(cpu:, target: :b)
|
|
334
|
+
cb_instructions[0x19] = CbRr.new(cpu:, target: :c)
|
|
335
|
+
cb_instructions[0x1A] = CbRr.new(cpu:, target: :d)
|
|
336
|
+
cb_instructions[0x1B] = CbRr.new(cpu:, target: :e)
|
|
337
|
+
cb_instructions[0x1C] = CbRr.new(cpu:, target: :h)
|
|
338
|
+
cb_instructions[0x1D] = CbRr.new(cpu:, target: :l)
|
|
339
|
+
cb_instructions[0x1E] = CbRr.new(cpu:, target: :mem_hl)
|
|
340
|
+
cb_instructions[0x1F] = CbRr.new(cpu:, target: :a)
|
|
341
|
+
|
|
342
|
+
# Opcodes 0x20 -> 0x2F
|
|
343
|
+
cb_instructions[0x20] = CbSla.new(cpu:, target: :b)
|
|
344
|
+
cb_instructions[0x21] = CbSla.new(cpu:, target: :c)
|
|
345
|
+
cb_instructions[0x22] = CbSla.new(cpu:, target: :d)
|
|
346
|
+
cb_instructions[0x23] = CbSla.new(cpu:, target: :e)
|
|
347
|
+
cb_instructions[0x24] = CbSla.new(cpu:, target: :h)
|
|
348
|
+
cb_instructions[0x25] = CbSla.new(cpu:, target: :l)
|
|
349
|
+
cb_instructions[0x26] = CbSla.new(cpu:, target: :mem_hl)
|
|
350
|
+
cb_instructions[0x27] = CbSla.new(cpu:, target: :a)
|
|
351
|
+
cb_instructions[0x28] = CbSra.new(cpu:, target: :b)
|
|
352
|
+
cb_instructions[0x29] = CbSra.new(cpu:, target: :c)
|
|
353
|
+
cb_instructions[0x2A] = CbSra.new(cpu:, target: :d)
|
|
354
|
+
cb_instructions[0x2B] = CbSra.new(cpu:, target: :e)
|
|
355
|
+
cb_instructions[0x2C] = CbSra.new(cpu:, target: :h)
|
|
356
|
+
cb_instructions[0x2D] = CbSra.new(cpu:, target: :l)
|
|
357
|
+
cb_instructions[0x2E] = CbSra.new(cpu:, target: :mem_hl)
|
|
358
|
+
cb_instructions[0x2F] = CbSra.new(cpu:, target: :a)
|
|
359
|
+
|
|
360
|
+
# Opcodes 0x30 -> 0x3F
|
|
361
|
+
cb_instructions[0x30] = CbSwap.new(cpu:, target: :b)
|
|
362
|
+
cb_instructions[0x31] = CbSwap.new(cpu:, target: :c)
|
|
363
|
+
cb_instructions[0x32] = CbSwap.new(cpu:, target: :d)
|
|
364
|
+
cb_instructions[0x33] = CbSwap.new(cpu:, target: :e)
|
|
365
|
+
cb_instructions[0x34] = CbSwap.new(cpu:, target: :h)
|
|
366
|
+
cb_instructions[0x35] = CbSwap.new(cpu:, target: :l)
|
|
367
|
+
cb_instructions[0x36] = CbSwap.new(cpu:, target: :mem_hl)
|
|
368
|
+
cb_instructions[0x37] = CbSwap.new(cpu:, target: :a)
|
|
369
|
+
cb_instructions[0x38] = CbSrl.new(cpu:, target: :b)
|
|
370
|
+
cb_instructions[0x39] = CbSrl.new(cpu:, target: :c)
|
|
371
|
+
cb_instructions[0x3A] = CbSrl.new(cpu:, target: :d)
|
|
372
|
+
cb_instructions[0x3B] = CbSrl.new(cpu:, target: :e)
|
|
373
|
+
cb_instructions[0x3C] = CbSrl.new(cpu:, target: :h)
|
|
374
|
+
cb_instructions[0x3D] = CbSrl.new(cpu:, target: :l)
|
|
375
|
+
cb_instructions[0x3E] = CbSrl.new(cpu:, target: :mem_hl)
|
|
376
|
+
cb_instructions[0x3F] = CbSrl.new(cpu:, target: :a)
|
|
377
|
+
|
|
378
|
+
# Opcodes 0x40 -> 0x4F
|
|
379
|
+
cb_instructions[0x40] = CbBit.new(cpu:, bit_pos: 0, target: :b)
|
|
380
|
+
cb_instructions[0x41] = CbBit.new(cpu:, bit_pos: 0, target: :c)
|
|
381
|
+
cb_instructions[0x42] = CbBit.new(cpu:, bit_pos: 0, target: :d)
|
|
382
|
+
cb_instructions[0x43] = CbBit.new(cpu:, bit_pos: 0, target: :e)
|
|
383
|
+
cb_instructions[0x44] = CbBit.new(cpu:, bit_pos: 0, target: :h)
|
|
384
|
+
cb_instructions[0x45] = CbBit.new(cpu:, bit_pos: 0, target: :l)
|
|
385
|
+
cb_instructions[0x46] = CbBit.new(cpu:, bit_pos: 0, target: :mem_hl)
|
|
386
|
+
cb_instructions[0x47] = CbBit.new(cpu:, bit_pos: 0, target: :a)
|
|
387
|
+
cb_instructions[0x48] = CbBit.new(cpu:, bit_pos: 1, target: :b)
|
|
388
|
+
cb_instructions[0x49] = CbBit.new(cpu:, bit_pos: 1, target: :c)
|
|
389
|
+
cb_instructions[0x4A] = CbBit.new(cpu:, bit_pos: 1, target: :d)
|
|
390
|
+
cb_instructions[0x4B] = CbBit.new(cpu:, bit_pos: 1, target: :e)
|
|
391
|
+
cb_instructions[0x4C] = CbBit.new(cpu:, bit_pos: 1, target: :h)
|
|
392
|
+
cb_instructions[0x4D] = CbBit.new(cpu:, bit_pos: 1, target: :l)
|
|
393
|
+
cb_instructions[0x4E] = CbBit.new(cpu:, bit_pos: 1, target: :mem_hl)
|
|
394
|
+
cb_instructions[0x4F] = CbBit.new(cpu:, bit_pos: 1, target: :a)
|
|
395
|
+
|
|
396
|
+
# Opcodes 0x50 -> 0x5F
|
|
397
|
+
cb_instructions[0x50] = CbBit.new(cpu:, bit_pos: 2, target: :b)
|
|
398
|
+
cb_instructions[0x51] = CbBit.new(cpu:, bit_pos: 2, target: :c)
|
|
399
|
+
cb_instructions[0x52] = CbBit.new(cpu:, bit_pos: 2, target: :d)
|
|
400
|
+
cb_instructions[0x53] = CbBit.new(cpu:, bit_pos: 2, target: :e)
|
|
401
|
+
cb_instructions[0x54] = CbBit.new(cpu:, bit_pos: 2, target: :h)
|
|
402
|
+
cb_instructions[0x55] = CbBit.new(cpu:, bit_pos: 2, target: :l)
|
|
403
|
+
cb_instructions[0x56] = CbBit.new(cpu:, bit_pos: 2, target: :mem_hl)
|
|
404
|
+
cb_instructions[0x57] = CbBit.new(cpu:, bit_pos: 2, target: :a)
|
|
405
|
+
cb_instructions[0x58] = CbBit.new(cpu:, bit_pos: 3, target: :b)
|
|
406
|
+
cb_instructions[0x59] = CbBit.new(cpu:, bit_pos: 3, target: :c)
|
|
407
|
+
cb_instructions[0x5A] = CbBit.new(cpu:, bit_pos: 3, target: :d)
|
|
408
|
+
cb_instructions[0x5B] = CbBit.new(cpu:, bit_pos: 3, target: :e)
|
|
409
|
+
cb_instructions[0x5C] = CbBit.new(cpu:, bit_pos: 3, target: :h)
|
|
410
|
+
cb_instructions[0x5D] = CbBit.new(cpu:, bit_pos: 3, target: :l)
|
|
411
|
+
cb_instructions[0x5E] = CbBit.new(cpu:, bit_pos: 3, target: :mem_hl)
|
|
412
|
+
cb_instructions[0x5F] = CbBit.new(cpu:, bit_pos: 3, target: :a)
|
|
413
|
+
|
|
414
|
+
# Opcodes 0x60 -> 0x6F
|
|
415
|
+
cb_instructions[0x60] = CbBit.new(cpu:, bit_pos: 4, target: :b)
|
|
416
|
+
cb_instructions[0x61] = CbBit.new(cpu:, bit_pos: 4, target: :c)
|
|
417
|
+
cb_instructions[0x62] = CbBit.new(cpu:, bit_pos: 4, target: :d)
|
|
418
|
+
cb_instructions[0x63] = CbBit.new(cpu:, bit_pos: 4, target: :e)
|
|
419
|
+
cb_instructions[0x64] = CbBit.new(cpu:, bit_pos: 4, target: :h)
|
|
420
|
+
cb_instructions[0x65] = CbBit.new(cpu:, bit_pos: 4, target: :l)
|
|
421
|
+
cb_instructions[0x66] = CbBit.new(cpu:, bit_pos: 4, target: :mem_hl)
|
|
422
|
+
cb_instructions[0x67] = CbBit.new(cpu:, bit_pos: 4, target: :a)
|
|
423
|
+
cb_instructions[0x68] = CbBit.new(cpu:, bit_pos: 5, target: :b)
|
|
424
|
+
cb_instructions[0x69] = CbBit.new(cpu:, bit_pos: 5, target: :c)
|
|
425
|
+
cb_instructions[0x6A] = CbBit.new(cpu:, bit_pos: 5, target: :d)
|
|
426
|
+
cb_instructions[0x6B] = CbBit.new(cpu:, bit_pos: 5, target: :e)
|
|
427
|
+
cb_instructions[0x6C] = CbBit.new(cpu:, bit_pos: 5, target: :h)
|
|
428
|
+
cb_instructions[0x6D] = CbBit.new(cpu:, bit_pos: 5, target: :l)
|
|
429
|
+
cb_instructions[0x6E] = CbBit.new(cpu:, bit_pos: 5, target: :mem_hl)
|
|
430
|
+
cb_instructions[0x6F] = CbBit.new(cpu:, bit_pos: 5, target: :a)
|
|
431
|
+
|
|
432
|
+
# Opcodes 0x70 -> 0x7F
|
|
433
|
+
cb_instructions[0x70] = CbBit.new(cpu:, bit_pos: 6, target: :b)
|
|
434
|
+
cb_instructions[0x71] = CbBit.new(cpu:, bit_pos: 6, target: :c)
|
|
435
|
+
cb_instructions[0x72] = CbBit.new(cpu:, bit_pos: 6, target: :d)
|
|
436
|
+
cb_instructions[0x73] = CbBit.new(cpu:, bit_pos: 6, target: :e)
|
|
437
|
+
cb_instructions[0x74] = CbBit.new(cpu:, bit_pos: 6, target: :h)
|
|
438
|
+
cb_instructions[0x75] = CbBit.new(cpu:, bit_pos: 6, target: :l)
|
|
439
|
+
cb_instructions[0x76] = CbBit.new(cpu:, bit_pos: 6, target: :mem_hl)
|
|
440
|
+
cb_instructions[0x77] = CbBit.new(cpu:, bit_pos: 6, target: :a)
|
|
441
|
+
cb_instructions[0x78] = CbBit.new(cpu:, bit_pos: 7, target: :b)
|
|
442
|
+
cb_instructions[0x79] = CbBit.new(cpu:, bit_pos: 7, target: :c)
|
|
443
|
+
cb_instructions[0x7A] = CbBit.new(cpu:, bit_pos: 7, target: :d)
|
|
444
|
+
cb_instructions[0x7B] = CbBit.new(cpu:, bit_pos: 7, target: :e)
|
|
445
|
+
cb_instructions[0x7C] = CbBit.new(cpu:, bit_pos: 7, target: :h)
|
|
446
|
+
cb_instructions[0x7D] = CbBit.new(cpu:, bit_pos: 7, target: :l)
|
|
447
|
+
cb_instructions[0x7E] = CbBit.new(cpu:, bit_pos: 7, target: :mem_hl)
|
|
448
|
+
cb_instructions[0x7F] = CbBit.new(cpu:, bit_pos: 7, target: :a)
|
|
449
|
+
|
|
450
|
+
# Opcodes 0x80 -> 0x8F
|
|
451
|
+
cb_instructions[0x80] = CbRes.new(cpu:, bit_pos: 0, target: :b)
|
|
452
|
+
cb_instructions[0x81] = CbRes.new(cpu:, bit_pos: 0, target: :c)
|
|
453
|
+
cb_instructions[0x82] = CbRes.new(cpu:, bit_pos: 0, target: :d)
|
|
454
|
+
cb_instructions[0x83] = CbRes.new(cpu:, bit_pos: 0, target: :e)
|
|
455
|
+
cb_instructions[0x84] = CbRes.new(cpu:, bit_pos: 0, target: :h)
|
|
456
|
+
cb_instructions[0x85] = CbRes.new(cpu:, bit_pos: 0, target: :l)
|
|
457
|
+
cb_instructions[0x86] = CbRes.new(cpu:, bit_pos: 0, target: :mem_hl)
|
|
458
|
+
cb_instructions[0x87] = CbRes.new(cpu:, bit_pos: 0, target: :a)
|
|
459
|
+
cb_instructions[0x88] = CbRes.new(cpu:, bit_pos: 1, target: :b)
|
|
460
|
+
cb_instructions[0x89] = CbRes.new(cpu:, bit_pos: 1, target: :c)
|
|
461
|
+
cb_instructions[0x8A] = CbRes.new(cpu:, bit_pos: 1, target: :d)
|
|
462
|
+
cb_instructions[0x8B] = CbRes.new(cpu:, bit_pos: 1, target: :e)
|
|
463
|
+
cb_instructions[0x8C] = CbRes.new(cpu:, bit_pos: 1, target: :h)
|
|
464
|
+
cb_instructions[0x8D] = CbRes.new(cpu:, bit_pos: 1, target: :l)
|
|
465
|
+
cb_instructions[0x8E] = CbRes.new(cpu:, bit_pos: 1, target: :mem_hl)
|
|
466
|
+
cb_instructions[0x8F] = CbRes.new(cpu:, bit_pos: 1, target: :a)
|
|
467
|
+
|
|
468
|
+
# Opcodes 0x90 -> 0x9F
|
|
469
|
+
cb_instructions[0x90] = CbRes.new(cpu:, bit_pos: 2, target: :b)
|
|
470
|
+
cb_instructions[0x91] = CbRes.new(cpu:, bit_pos: 2, target: :c)
|
|
471
|
+
cb_instructions[0x92] = CbRes.new(cpu:, bit_pos: 2, target: :d)
|
|
472
|
+
cb_instructions[0x93] = CbRes.new(cpu:, bit_pos: 2, target: :e)
|
|
473
|
+
cb_instructions[0x94] = CbRes.new(cpu:, bit_pos: 2, target: :h)
|
|
474
|
+
cb_instructions[0x95] = CbRes.new(cpu:, bit_pos: 2, target: :l)
|
|
475
|
+
cb_instructions[0x96] = CbRes.new(cpu:, bit_pos: 2, target: :mem_hl)
|
|
476
|
+
cb_instructions[0x97] = CbRes.new(cpu:, bit_pos: 2, target: :a)
|
|
477
|
+
cb_instructions[0x98] = CbRes.new(cpu:, bit_pos: 3, target: :b)
|
|
478
|
+
cb_instructions[0x99] = CbRes.new(cpu:, bit_pos: 3, target: :c)
|
|
479
|
+
cb_instructions[0x9A] = CbRes.new(cpu:, bit_pos: 3, target: :d)
|
|
480
|
+
cb_instructions[0x9B] = CbRes.new(cpu:, bit_pos: 3, target: :e)
|
|
481
|
+
cb_instructions[0x9C] = CbRes.new(cpu:, bit_pos: 3, target: :h)
|
|
482
|
+
cb_instructions[0x9D] = CbRes.new(cpu:, bit_pos: 3, target: :l)
|
|
483
|
+
cb_instructions[0x9E] = CbRes.new(cpu:, bit_pos: 3, target: :mem_hl)
|
|
484
|
+
cb_instructions[0x9F] = CbRes.new(cpu:, bit_pos: 3, target: :a)
|
|
485
|
+
|
|
486
|
+
# Opcodes 0xA0 -> 0xAF
|
|
487
|
+
cb_instructions[0xA0] = CbRes.new(cpu:, bit_pos: 4, target: :b)
|
|
488
|
+
cb_instructions[0xA1] = CbRes.new(cpu:, bit_pos: 4, target: :c)
|
|
489
|
+
cb_instructions[0xA2] = CbRes.new(cpu:, bit_pos: 4, target: :d)
|
|
490
|
+
cb_instructions[0xA3] = CbRes.new(cpu:, bit_pos: 4, target: :e)
|
|
491
|
+
cb_instructions[0xA4] = CbRes.new(cpu:, bit_pos: 4, target: :h)
|
|
492
|
+
cb_instructions[0xA5] = CbRes.new(cpu:, bit_pos: 4, target: :l)
|
|
493
|
+
cb_instructions[0xA6] = CbRes.new(cpu:, bit_pos: 4, target: :mem_hl)
|
|
494
|
+
cb_instructions[0xA7] = CbRes.new(cpu:, bit_pos: 4, target: :a)
|
|
495
|
+
cb_instructions[0xA8] = CbRes.new(cpu:, bit_pos: 5, target: :b)
|
|
496
|
+
cb_instructions[0xA9] = CbRes.new(cpu:, bit_pos: 5, target: :c)
|
|
497
|
+
cb_instructions[0xAA] = CbRes.new(cpu:, bit_pos: 5, target: :d)
|
|
498
|
+
cb_instructions[0xAB] = CbRes.new(cpu:, bit_pos: 5, target: :e)
|
|
499
|
+
cb_instructions[0xAC] = CbRes.new(cpu:, bit_pos: 5, target: :h)
|
|
500
|
+
cb_instructions[0xAD] = CbRes.new(cpu:, bit_pos: 5, target: :l)
|
|
501
|
+
cb_instructions[0xAE] = CbRes.new(cpu:, bit_pos: 5, target: :mem_hl)
|
|
502
|
+
cb_instructions[0xAF] = CbRes.new(cpu:, bit_pos: 5, target: :a)
|
|
503
|
+
|
|
504
|
+
# Opcodes 0xB0 -> 0xBF
|
|
505
|
+
cb_instructions[0xB0] = CbRes.new(cpu:, bit_pos: 6, target: :b)
|
|
506
|
+
cb_instructions[0xB1] = CbRes.new(cpu:, bit_pos: 6, target: :c)
|
|
507
|
+
cb_instructions[0xB2] = CbRes.new(cpu:, bit_pos: 6, target: :d)
|
|
508
|
+
cb_instructions[0xB3] = CbRes.new(cpu:, bit_pos: 6, target: :e)
|
|
509
|
+
cb_instructions[0xB4] = CbRes.new(cpu:, bit_pos: 6, target: :h)
|
|
510
|
+
cb_instructions[0xB5] = CbRes.new(cpu:, bit_pos: 6, target: :l)
|
|
511
|
+
cb_instructions[0xB6] = CbRes.new(cpu:, bit_pos: 6, target: :mem_hl)
|
|
512
|
+
cb_instructions[0xB7] = CbRes.new(cpu:, bit_pos: 6, target: :a)
|
|
513
|
+
cb_instructions[0xB8] = CbRes.new(cpu:, bit_pos: 7, target: :b)
|
|
514
|
+
cb_instructions[0xB9] = CbRes.new(cpu:, bit_pos: 7, target: :c)
|
|
515
|
+
cb_instructions[0xBA] = CbRes.new(cpu:, bit_pos: 7, target: :d)
|
|
516
|
+
cb_instructions[0xBB] = CbRes.new(cpu:, bit_pos: 7, target: :e)
|
|
517
|
+
cb_instructions[0xBC] = CbRes.new(cpu:, bit_pos: 7, target: :h)
|
|
518
|
+
cb_instructions[0xBD] = CbRes.new(cpu:, bit_pos: 7, target: :l)
|
|
519
|
+
cb_instructions[0xBE] = CbRes.new(cpu:, bit_pos: 7, target: :mem_hl)
|
|
520
|
+
cb_instructions[0xBF] = CbRes.new(cpu:, bit_pos: 7, target: :a)
|
|
521
|
+
|
|
522
|
+
# Opcodes 0xC0 -> 0xCF
|
|
523
|
+
cb_instructions[0xC0] = CbSet.new(cpu:, bit_pos: 0, target: :b)
|
|
524
|
+
cb_instructions[0xC1] = CbSet.new(cpu:, bit_pos: 0, target: :c)
|
|
525
|
+
cb_instructions[0xC2] = CbSet.new(cpu:, bit_pos: 0, target: :d)
|
|
526
|
+
cb_instructions[0xC3] = CbSet.new(cpu:, bit_pos: 0, target: :e)
|
|
527
|
+
cb_instructions[0xC4] = CbSet.new(cpu:, bit_pos: 0, target: :h)
|
|
528
|
+
cb_instructions[0xC5] = CbSet.new(cpu:, bit_pos: 0, target: :l)
|
|
529
|
+
cb_instructions[0xC6] = CbSet.new(cpu:, bit_pos: 0, target: :mem_hl)
|
|
530
|
+
cb_instructions[0xC7] = CbSet.new(cpu:, bit_pos: 0, target: :a)
|
|
531
|
+
cb_instructions[0xC8] = CbSet.new(cpu:, bit_pos: 1, target: :b)
|
|
532
|
+
cb_instructions[0xC9] = CbSet.new(cpu:, bit_pos: 1, target: :c)
|
|
533
|
+
cb_instructions[0xCA] = CbSet.new(cpu:, bit_pos: 1, target: :d)
|
|
534
|
+
cb_instructions[0xCB] = CbSet.new(cpu:, bit_pos: 1, target: :e)
|
|
535
|
+
cb_instructions[0xCC] = CbSet.new(cpu:, bit_pos: 1, target: :h)
|
|
536
|
+
cb_instructions[0xCD] = CbSet.new(cpu:, bit_pos: 1, target: :l)
|
|
537
|
+
cb_instructions[0xCE] = CbSet.new(cpu:, bit_pos: 1, target: :mem_hl)
|
|
538
|
+
cb_instructions[0xCF] = CbSet.new(cpu:, bit_pos: 1, target: :a)
|
|
539
|
+
|
|
540
|
+
# Opcodes 0xD0 -> 0xDF
|
|
541
|
+
cb_instructions[0xD0] = CbSet.new(cpu:, bit_pos: 2, target: :b)
|
|
542
|
+
cb_instructions[0xD1] = CbSet.new(cpu:, bit_pos: 2, target: :c)
|
|
543
|
+
cb_instructions[0xD2] = CbSet.new(cpu:, bit_pos: 2, target: :d)
|
|
544
|
+
cb_instructions[0xD3] = CbSet.new(cpu:, bit_pos: 2, target: :e)
|
|
545
|
+
cb_instructions[0xD4] = CbSet.new(cpu:, bit_pos: 2, target: :h)
|
|
546
|
+
cb_instructions[0xD5] = CbSet.new(cpu:, bit_pos: 2, target: :l)
|
|
547
|
+
cb_instructions[0xD6] = CbSet.new(cpu:, bit_pos: 2, target: :mem_hl)
|
|
548
|
+
cb_instructions[0xD7] = CbSet.new(cpu:, bit_pos: 2, target: :a)
|
|
549
|
+
cb_instructions[0xD8] = CbSet.new(cpu:, bit_pos: 3, target: :b)
|
|
550
|
+
cb_instructions[0xD9] = CbSet.new(cpu:, bit_pos: 3, target: :c)
|
|
551
|
+
cb_instructions[0xDA] = CbSet.new(cpu:, bit_pos: 3, target: :d)
|
|
552
|
+
cb_instructions[0xDB] = CbSet.new(cpu:, bit_pos: 3, target: :e)
|
|
553
|
+
cb_instructions[0xDC] = CbSet.new(cpu:, bit_pos: 3, target: :h)
|
|
554
|
+
cb_instructions[0xDD] = CbSet.new(cpu:, bit_pos: 3, target: :l)
|
|
555
|
+
cb_instructions[0xDE] = CbSet.new(cpu:, bit_pos: 3, target: :mem_hl)
|
|
556
|
+
cb_instructions[0xDF] = CbSet.new(cpu:, bit_pos: 3, target: :a)
|
|
557
|
+
|
|
558
|
+
# Opcodes 0xE0 -> 0xEF
|
|
559
|
+
cb_instructions[0xE0] = CbSet.new(cpu:, bit_pos: 4, target: :b)
|
|
560
|
+
cb_instructions[0xE1] = CbSet.new(cpu:, bit_pos: 4, target: :c)
|
|
561
|
+
cb_instructions[0xE2] = CbSet.new(cpu:, bit_pos: 4, target: :d)
|
|
562
|
+
cb_instructions[0xE3] = CbSet.new(cpu:, bit_pos: 4, target: :e)
|
|
563
|
+
cb_instructions[0xE4] = CbSet.new(cpu:, bit_pos: 4, target: :h)
|
|
564
|
+
cb_instructions[0xE5] = CbSet.new(cpu:, bit_pos: 4, target: :l)
|
|
565
|
+
cb_instructions[0xE6] = CbSet.new(cpu:, bit_pos: 4, target: :mem_hl)
|
|
566
|
+
cb_instructions[0xE7] = CbSet.new(cpu:, bit_pos: 4, target: :a)
|
|
567
|
+
cb_instructions[0xE8] = CbSet.new(cpu:, bit_pos: 5, target: :b)
|
|
568
|
+
cb_instructions[0xE9] = CbSet.new(cpu:, bit_pos: 5, target: :c)
|
|
569
|
+
cb_instructions[0xEA] = CbSet.new(cpu:, bit_pos: 5, target: :d)
|
|
570
|
+
cb_instructions[0xEB] = CbSet.new(cpu:, bit_pos: 5, target: :e)
|
|
571
|
+
cb_instructions[0xEC] = CbSet.new(cpu:, bit_pos: 5, target: :h)
|
|
572
|
+
cb_instructions[0xED] = CbSet.new(cpu:, bit_pos: 5, target: :l)
|
|
573
|
+
cb_instructions[0xEE] = CbSet.new(cpu:, bit_pos: 5, target: :mem_hl)
|
|
574
|
+
cb_instructions[0xEF] = CbSet.new(cpu:, bit_pos: 5, target: :a)
|
|
575
|
+
|
|
576
|
+
# Opcodes 0xF0 -> 0xFF
|
|
577
|
+
cb_instructions[0xF0] = CbSet.new(cpu:, bit_pos: 6, target: :b)
|
|
578
|
+
cb_instructions[0xF1] = CbSet.new(cpu:, bit_pos: 6, target: :c)
|
|
579
|
+
cb_instructions[0xF2] = CbSet.new(cpu:, bit_pos: 6, target: :d)
|
|
580
|
+
cb_instructions[0xF3] = CbSet.new(cpu:, bit_pos: 6, target: :e)
|
|
581
|
+
cb_instructions[0xF4] = CbSet.new(cpu:, bit_pos: 6, target: :h)
|
|
582
|
+
cb_instructions[0xF5] = CbSet.new(cpu:, bit_pos: 6, target: :l)
|
|
583
|
+
cb_instructions[0xF6] = CbSet.new(cpu:, bit_pos: 6, target: :mem_hl)
|
|
584
|
+
cb_instructions[0xF7] = CbSet.new(cpu:, bit_pos: 6, target: :a)
|
|
585
|
+
cb_instructions[0xF8] = CbSet.new(cpu:, bit_pos: 7, target: :b)
|
|
586
|
+
cb_instructions[0xF9] = CbSet.new(cpu:, bit_pos: 7, target: :c)
|
|
587
|
+
cb_instructions[0xFA] = CbSet.new(cpu:, bit_pos: 7, target: :d)
|
|
588
|
+
cb_instructions[0xFB] = CbSet.new(cpu:, bit_pos: 7, target: :e)
|
|
589
|
+
cb_instructions[0xFC] = CbSet.new(cpu:, bit_pos: 7, target: :h)
|
|
590
|
+
cb_instructions[0xFD] = CbSet.new(cpu:, bit_pos: 7, target: :l)
|
|
591
|
+
cb_instructions[0xFE] = CbSet.new(cpu:, bit_pos: 7, target: :mem_hl)
|
|
592
|
+
cb_instructions[0xFF] = CbSet.new(cpu:, bit_pos: 7, target: :a)
|
|
593
|
+
|
|
594
|
+
cb_instructions.freeze
|
|
595
|
+
end
|
|
596
|
+
end
|
|
597
|
+
end
|
|
598
|
+
end
|
|
599
|
+
end
|
|
600
|
+
# rubocop:enable Metrics/MethodLength, Metrics/ModuleLength
|