amaterasu 0.6.0

data/lib/amaterasu/game_boy/cpu/instructions/ld16.rb

@@ -0,0 +1,79 @@
+# frozen_string_literal: true
+
+module Amaterasu
+  module GameBoy
+    class Cpu
+      module Instructions
+        # Holds the logic of all the 16-bit Load instructions.
+        class Ld16 < Base
+          def initialize(cpu:, target:, source:)
+            super(cpu:)
+
+            @mnemonic = "LD #{format_operand(target)}, #{format_operand(source)}"
+            @logic    = build_logic(target, source)
+          end
+
+          private
+
+          def build_logic(target, source)
+            return -> { ld_mem_imm16_sp } if target == :mem_imm16
+
+            case target
+            when :bc then -> { @registers.bc = @cpu.fetch_next_word }
+            when :de then -> { @registers.de = @cpu.fetch_next_word }
+            when :hl
+              case source
+              when :imm16 then -> { @registers.hl = @cpu.fetch_next_word }
+              when :sp_plus_sig8
+                lambda do
+                  unsigned_byte = @cpu.fetch_next_byte
+                  signed_value = @cpu.sign_value(unsigned_byte)
+                  sp = @registers.sp
+                  result = @cpu.add16(@registers.sp, signed_value)
+
+                  @registers.clear_flags
+                  @registers.h_flag = (sp & 0x0F) + (unsigned_byte & 0x0F) > 0x0F
+                  @registers.c_flag = (sp & 0xFF) + (unsigned_byte & 0xFF) > 0xFF
+
+                  @registers.hl = result
+                end
+              else
+                raise ArgumentError, 'Unknown Ld16 source for LD HL'
+              end
+            when :sp
+              case source
+              when :imm16 then -> { @registers.sp = @cpu.fetch_next_word }
+              when :hl
+                lambda do
+                  @cpu.internal_processing
+                  @registers.sp = @registers.hl
+                end
+              else
+                raise ArgumentError, 'Unknown Ld16 source for LD SP'
+              end
+            else
+              raise ArgumentError, 'Unknown Ld16 target'
+            end
+          end
+
+          # Loads the LSB from SP to the imm16 address.
+          # Loads the MSB from SP to the imm16 address + 1.
+          #
+          # M-cycle 1: Fetches the opcode.
+          # M-cycle 2: Fetches the LSB of the address to be used.
+          # M-cycle 3: Fetches the MSB of the address to be used.
+          # M-cycle 4: Writes the LSB of SP into the address.
+          # M-cycle 5: Writes the MSB of SP into the address + 1.
+          #
+          def ld_mem_imm16_sp
+            imm16 = @cpu.fetch_next_word
+            sp = @registers.sp
+
+            @cpu.bus_write(address: imm16, value: sp & 0xFF)
+            @cpu.bus_write(address: imm16 + 1, value: (sp >> 8) & 0xFF)
+          end
+        end
+      end
+    end
+  end
+end

data/lib/amaterasu/game_boy/cpu/instructions/ld8.rb

@@ -0,0 +1,210 @@
+# frozen_string_literal: true
+
+module Amaterasu
+  module GameBoy
+    class Cpu
+      module Instructions
+        # Holds the logic of all the 8-bit Load instructions.
+        class Ld8 < Base
+          def initialize(cpu:, target:, source:)
+            super(cpu:)
+
+            @mnemonic = "LD #{format_operand(target)}, #{format_operand(source)}"
+            @logic    = build_logic(target, source)
+          end
+
+          private
+
+          def build_logic(target, source)
+            return -> { ld_a_mem_imm16 } if source == :mem_imm16
+            return -> { ld_a_mem_bc } if source == :mem_bc
+            return -> { ld_a_mem_de } if source == :mem_de
+
+            case target
+            when :a       then load_a(source)
+            when :b       then load_b(source)
+            when :c       then load_c(source)
+            when :d       then load_d(source)
+            when :e       then load_e(source)
+            when :h       then load_h(source)
+            when :l       then load_l(source)
+            when :mem_hl  then load_mem_hl(source)
+            when :mem_hli then -> { load_mem_hli }
+            when :mem_hld then -> { load_mem_hld }
+            when :mem_bc  then -> { @cpu.bus_write(address: @registers.bc, value: @registers.a) }
+            when :mem_de  then -> { @cpu.bus_write(address: @registers.de, value: @registers.a) }
+            when :mem_imm16 then -> { ld_mem_imm16_a }
+            else
+              raise ArgumentError, 'Unknown target for :build_logic in Ld8'
+            end
+          end
+
+          def load_a(source)
+            case source
+            when :a      then -> {}
+            when :b      then -> { @registers.a = @registers.b }
+            when :c      then -> { @registers.a = @registers.c }
+            when :d      then -> { @registers.a = @registers.d }
+            when :e      then -> { @registers.a = @registers.e }
+            when :h      then -> { @registers.a = @registers.h }
+            when :l      then -> { @registers.a = @registers.l }
+            when :imm8   then -> { @registers.a = @cpu.fetch_next_byte }
+            when :mem_hl then -> { @registers.a = @cpu.bus_read(address: @registers.hl) }
+            when :mem_hli
+              lambda do
+                @registers.a = @cpu.bus_read(address: @registers.hl)
+                @registers.hl += 1
+              end
+            when :mem_hld
+              lambda do
+                @registers.a = @cpu.bus_read(address: @registers.hl)
+                @registers.hl -= 1
+              end
+            else
+              raise ArgumentError, 'Unknown source for :load_a in Ld8'
+            end
+          end
+
+          def load_b(source)
+            case source
+            when :a      then -> { @registers.b = @registers.a }
+            when :b      then -> {}
+            when :c      then -> { @registers.b = @registers.c }
+            when :d      then -> { @registers.b = @registers.d }
+            when :e      then -> { @registers.b = @registers.e }
+            when :h      then -> { @registers.b = @registers.h }
+            when :l      then -> { @registers.b = @registers.l }
+            when :imm8   then -> { @registers.b = @cpu.fetch_next_byte }
+            when :mem_hl then -> { @registers.b = @cpu.bus_read(address: @registers.hl) }
+            else
+              raise ArgumentError, 'Unknown source for :load_b in Ld8'
+            end
+          end
+
+          def load_c(source)
+            case source
+            when :a      then -> { @registers.c = @registers.a }
+            when :b      then -> { @registers.c = @registers.b }
+            when :c      then -> {}
+            when :d      then -> { @registers.c = @registers.d }
+            when :e      then -> { @registers.c = @registers.e }
+            when :h      then -> { @registers.c = @registers.h }
+            when :l      then -> { @registers.c = @registers.l }
+            when :imm8   then -> { @registers.c = @cpu.fetch_next_byte }
+            when :mem_hl then -> { @registers.c = @cpu.bus_read(address: @registers.hl) }
+            else
+              raise ArgumentError, 'Unknown source for :load_c in Ld8'
+            end
+          end
+
+          def load_d(source)
+            case source
+            when :a      then -> { @registers.d = @registers.a }
+            when :b      then -> { @registers.d = @registers.b }
+            when :c      then -> { @registers.d = @registers.c }
+            when :d      then -> {}
+            when :e      then -> { @registers.d = @registers.e }
+            when :h      then -> { @registers.d = @registers.h }
+            when :l      then -> { @registers.d = @registers.l }
+            when :imm8   then -> { @registers.d = @cpu.fetch_next_byte }
+            when :mem_hl then -> { @registers.d = @cpu.bus_read(address: @registers.hl) }
+            else
+              raise ArgumentError, 'Unknown source for :load_d in Ld8'
+            end
+          end
+
+          def load_e(source)
+            case source
+            when :a      then -> { @registers.e = @registers.a }
+            when :b      then -> { @registers.e = @registers.b }
+            when :c      then -> { @registers.e = @registers.c }
+            when :d      then -> { @registers.e = @registers.d }
+            when :e      then -> {}
+            when :h      then -> { @registers.e = @registers.h }
+            when :l      then -> { @registers.e = @registers.l }
+            when :imm8   then -> { @registers.e = @cpu.fetch_next_byte }
+            when :mem_hl then -> { @registers.e = @cpu.bus_read(address: @registers.hl) }
+            else
+              raise ArgumentError, 'Unknown source for :load_e in Ld8'
+            end
+          end
+
+          def load_h(source)
+            case source
+            when :a      then -> { @registers.h = @registers.a }
+            when :b      then -> { @registers.h = @registers.b }
+            when :c      then -> { @registers.h = @registers.c }
+            when :d      then -> { @registers.h = @registers.d }
+            when :e      then -> { @registers.h = @registers.e }
+            when :h      then -> {}
+            when :l      then -> { @registers.h = @registers.l }
+            when :imm8   then -> { @registers.h = @cpu.fetch_next_byte }
+            when :mem_hl then -> { @registers.h = @cpu.bus_read(address: @registers.hl) }
+            else
+              raise ArgumentError, 'Unknown source for :load_h in Ld8'
+            end
+          end
+
+          def load_l(source)
+            case source
+            when :a      then -> { @registers.l = @registers.a }
+            when :b      then -> { @registers.l = @registers.b }
+            when :c      then -> { @registers.l = @registers.c }
+            when :d      then -> { @registers.l = @registers.d }
+            when :e      then -> { @registers.l = @registers.e }
+            when :h      then -> { @registers.l = @registers.h }
+            when :l      then -> {}
+            when :imm8   then -> { @registers.l = @cpu.fetch_next_byte }
+            when :mem_hl then -> { @registers.l = @cpu.bus_read(address: @registers.hl) }
+            else
+              raise ArgumentError, 'Unknown source for :load_l in Ld8'
+            end
+          end
+
+          def load_mem_hl(source)
+            case source
+            when :a    then -> { @cpu.bus_write(address: @registers.hl, value: @registers.a) }
+            when :b    then -> { @cpu.bus_write(address: @registers.hl, value: @registers.b) }
+            when :c    then -> { @cpu.bus_write(address: @registers.hl, value: @registers.c) }
+            when :d    then -> { @cpu.bus_write(address: @registers.hl, value: @registers.d) }
+            when :e    then -> { @cpu.bus_write(address: @registers.hl, value: @registers.e) }
+            when :h    then -> { @cpu.bus_write(address: @registers.hl, value: @registers.h) }
+            when :l    then -> { @cpu.bus_write(address: @registers.hl, value: @registers.l) }
+            when :imm8 then -> { @cpu.bus_write(address: @registers.hl, value: @cpu.fetch_next_byte) }
+            else
+              raise ArgumentError, 'Unknown source for :load_mem_hl in Ld8'
+            end
+          end
+
+          def load_mem_hli
+            @cpu.bus_write(address: @registers.hl, value: @registers.a)
+            @registers.hl += 1
+          end
+
+          def load_mem_hld
+            @cpu.bus_write(address: @registers.hl, value: @registers.a)
+            @registers.hl -= 1
+          end
+
+          def ld_mem_imm16_a
+            imm16_address = @cpu.fetch_next_word
+            @cpu.bus_write(address: imm16_address, value: @registers.a)
+          end
+
+          def ld_a_mem_imm16
+            imm16_address = @cpu.fetch_next_word
+            @registers.a = @cpu.bus_read(address: imm16_address)
+          end
+
+          def ld_a_mem_bc
+            @registers.a = @cpu.bus_read(address: @registers.bc)
+          end
+
+          def ld_a_mem_de
+            @registers.a = @cpu.bus_read(address: @registers.de)
+          end
+        end
+      end
+    end
+  end
+end

data/lib/amaterasu/game_boy/cpu/instructions/ldh.rb

@@ -0,0 +1,61 @@
+# frozen_string_literal: true
+
+module Amaterasu
+  module GameBoy
+    class Cpu
+      module Instructions
+        # Holds the logic of all the LDH (Load High RAM) instructions.
+        class Ldh < Base
+          IO_BASE_ADDRESS = 0xFF00
+
+          def initialize(cpu:, target:, source:)
+            super(cpu:)
+
+            @mnemonic = "LDH #{format_operand(target)}, #{format_operand(source)}"
+            @bytes    = 2
+            @m_cycles = 2
+            @logic    = build_logic(target, source)
+          end
+
+          private
+
+          def build_logic(target, source)
+            case target
+            when :a
+              case source
+              when :mem_unsig8 then -> { ldh_a_mem_unsig8 }
+              when :mem_c then -> { ldh_a_mem_c }
+              else
+                raise ArgumentError, 'Unknown Ldh source for :a target'
+              end
+            when :mem_unsig8 then -> { ldh_mem_unsig8_a }
+            when :mem_c then -> { ldh_mem_c_a }
+            else
+              raise ArgumentError, 'Unknown Ldh target'
+            end
+          end
+
+          def ldh_mem_unsig8_a
+            unsigned_byte = @cpu.fetch_next_byte
+
+            @cpu.bus_write(address: IO_BASE_ADDRESS + unsigned_byte, value: @registers.a)
+          end
+
+          def ldh_a_mem_unsig8
+            unsigned_byte = @cpu.fetch_next_byte
+
+            @registers.a = @cpu.bus_read(address: IO_BASE_ADDRESS + unsigned_byte)
+          end
+
+          def ldh_mem_c_a
+            @cpu.bus_write(address: IO_BASE_ADDRESS + @registers.c, value: @registers.a)
+          end
+
+          def ldh_a_mem_c
+            @registers.a = @cpu.bus_read(address: IO_BASE_ADDRESS + @registers.c)
+          end
+        end
+      end
+    end
+  end
+end

data/lib/amaterasu/game_boy/cpu/instructions/misc.rb

@@ -0,0 +1,53 @@
+# frozen_string_literal: true
+
+module Amaterasu
+  module GameBoy
+    class Cpu
+      module Instructions
+        # Holds the logic for CPL, SCF and CCF instructions.
+        class Misc < Base
+          def initialize(cpu:, operation:)
+            super(cpu:)
+
+            @mnemonic = format_operand(operation)
+            @logic    = build_logic(operation)
+          end
+
+          private
+
+          def build_logic(operation)
+            case operation
+            when :cpl then -> { cpl }
+            when :scf then -> { scf }
+            when :ccf then -> { ccf }
+            else
+              raise ArgumentError, 'Unknown Misc operation'
+            end
+          end
+
+          # Set Carry flag.
+          def scf
+            @registers.n_flag = false
+            @registers.h_flag = false
+            @registers.c_flag = true
+          end
+
+          # Complement the Carry flag.
+          def ccf
+            @registers.n_flag = false
+            @registers.h_flag = false
+            @registers.c_flag = @registers.c_flag.zero?
+          end
+
+          # Complement the value from the A register.
+          def cpl
+            @registers.a = ~@registers.a
+
+            @registers.n_flag = true
+            @registers.h_flag = true
+          end
+        end
+      end
+    end
+  end
+end

data/lib/amaterasu/game_boy/cpu/instructions/nop.rb

@@ -0,0 +1,19 @@
+# frozen_string_literal: true
+
+module Amaterasu
+  module GameBoy
+    class Cpu
+      module Instructions
+        # Defines the mnemonic, bytes and logic for the NOP instruction.
+        class Nop < Base
+          def initialize(cpu:)
+            super
+
+            @mnemonic = 'NOP'
+            @logic = -> {}
+          end
+        end
+      end
+    end
+  end
+end

data/lib/amaterasu/game_boy/cpu/instructions/or.rb

@@ -0,0 +1,56 @@
+# frozen_string_literal: true
+
+module Amaterasu
+  module GameBoy
+    class Cpu
+      module Instructions
+        # Handles the logic related to all possible OR instructions
+        #
+        # - OR A, r8
+        # - OR A, [HL]
+        # - OR A, n8
+        class Or < Base
+          # @param cpu [Cpu] Holds a direct reference to the main Cpu object.
+          # @param source [Symbol] Operator, can be a register, :mem_hl, :imm8.
+          def initialize(cpu:, source:)
+            super(cpu:)
+
+            @mnemonic = "OR A, #{source}"
+            @logic    = build_logic(source)
+          end
+
+          private
+
+          # Builds the logic for all OR instructions.
+          # Returns a lambda object to be called by the CPU.
+          def build_logic(source)
+            case source
+            when :a      then -> { or_a(@registers.a) }
+            when :b      then -> { or_a(@registers.b) }
+            when :c      then -> { or_a(@registers.c) }
+            when :d      then -> { or_a(@registers.d) }
+            when :e      then -> { or_a(@registers.e) }
+            when :h      then -> { or_a(@registers.h) }
+            when :l      then -> { or_a(@registers.l) }
+            when :mem_hl then -> { or_a(@cpu.bus_read(address: @registers.hl)) }
+            when :imm8   then -> { or_a(@cpu.fetch_next_byte) }
+            else
+              raise ArgumentError, 'Unknown Or source'
+            end
+          end
+
+          # Performs a Bitwise OR between a given value and the A register.
+          #
+          def or_a(value)
+            result = @registers.a | value
+
+            @registers.clear_flags
+            @registers.z_flag = result.nobits?(0xFF)
+
+            @registers.a = result
+          end
+        end
+      end
+    end
+  end
+end

data/lib/amaterasu/game_boy/cpu/instructions/pop.rb

@@ -0,0 +1,39 @@
+# frozen_string_literal: true
+
+module Amaterasu
+  module GameBoy
+    class Cpu
+      module Instructions
+        # Holds the logic of all the POP instructions.
+        class Pop < Base
+          # Creates a Pop instruction object with a mnemonic and logic to be executed.
+          def initialize(cpu:, reg16:)
+            super(cpu:)
+
+            @mnemonic = "POP #{format_operand(reg16)}"
+            @logic    = build_logic(reg16)
+          end
+
+          private
+
+          # Returns a Proc object to be executed by the CPU at runtime.
+          #
+          # M-cycle 1: Fetches opcode.
+          # M-cycle 2: Gets the reg16 lsb from the stack.
+          # M-cycle 3: Gets the reg16 msb from the stack.
+          #            Assigns the 16-bit value to a given reg16 (same cycle).
+          def build_logic(reg16)
+            case reg16
+            when :bc then -> { @registers.bc = @cpu.stack_pop }
+            when :de then -> { @registers.de = @cpu.stack_pop }
+            when :hl then -> { @registers.hl = @cpu.stack_pop }
+            when :af then -> { @registers.af = @cpu.stack_pop }
+            else
+              raise ArgumentError, 'Unknown Pop reg16'
+            end
+          end
+        end
+      end
+    end
+  end
+end

data/lib/amaterasu/game_boy/cpu/instructions/push.rb

@@ -0,0 +1,43 @@
+# frozen_string_literal: true
+
+module Amaterasu
+  module GameBoy
+    class Cpu
+      module Instructions
+        # Holds the logic of all the PUSH instructions.
+        class Push < Base
+          # Creates a Push instruction object with a mnemonic and logic to be executed.
+          def initialize(cpu:, reg16:)
+            super(cpu:)
+
+            @mnemonic = "PUSH #{format_operand(reg16)}"
+            @logic    = build_logic(reg16)
+          end
+
+          private
+
+          # Returns a Proc object to be executed by the CPU at runtime.
+          def build_logic(reg16)
+            case reg16
+            when :bc then -> { push(@registers.bc) }
+            when :de then -> { push(@registers.de) }
+            when :hl then -> { push(@registers.hl) }
+            when :af then -> { push(@registers.af) }
+            else
+              raise ArgumentError, 'Unknown Push reg16'
+            end
+          end
+
+          # M-cycle 1: Fetches opcode.
+          # M-cycle 2: Internal processing (dead cycle).
+          # M-cycle 3: Writes msb from reg16 into the stack.
+          # M-cycle 4: Writes lsb from reg16 into the stack.
+          def push(reg16)
+            @cpu.internal_processing
+            @cpu.stack_push(value: reg16)
+          end
+        end
+      end
+    end
+  end
+end

data/lib/amaterasu/game_boy/cpu/instructions/ret.rb

@@ -0,0 +1,70 @@
+# frozen_string_literal: true
+
+module Amaterasu
+  module GameBoy
+    class Cpu
+      module Instructions
+        # Holds the logic of all the RET + RETI instructions.
+        class Ret < Base
+          # Creates a Ret instruction object with a mnemonic and logic to be executed.
+          def initialize(cpu:, condition: nil, enable_ime: false)
+            super(cpu:)
+
+            @mnemonic = enable_ime ? 'RETI' : "RET #{format_operand(condition)}".strip
+            @logic    = build_logic(condition, enable_ime)
+          end
+
+          private
+
+          # Returns a Proc object to be executed by the CPU at runtime.
+          def build_logic(condition, enable_ime)
+            return -> { reti } if enable_ime
+            return -> { ret }  if condition.nil?
+
+            case condition
+            when :nz then -> { ret_cc(condition: @registers.z_flag.zero?) }
+            when :z  then -> { ret_cc(condition: @registers.z_flag == 1) }
+            when :nc then -> { ret_cc(condition: @registers.c_flag.zero?) }
+            when :c  then -> { ret_cc(condition: @registers.c_flag == 1) }
+            else
+              raise ArgumentError, 'Unknown Ret condition'
+            end
+          end
+
+          # M-cycle 1: Fetches opcode.
+          # M-cycle 2: Spends 1 cycle to evaluate condition (Only for RET cc).
+          # ---------- Returns early if condition not met.
+          # M-cycle 3: Pops the LSB from the Stack.
+          # M-cycle 4: Pops the MSB from the Stack.
+          # M-cycle 5: Jumps to the return address.
+          def ret_cc(condition: true)
+            @cpu.internal_processing
+            return unless condition
+
+            return_address = @cpu.stack_pop
+            @cpu.jump_to(address: return_address)
+          end
+
+          # M-cycle 1: Fetches opcode.
+          # M-cycle 2: Pops the LSB from the Stack.
+          # M-cycle 3: Pops the MSB from the Stack.
+          # M-cycle 4: Jumps to the return address.
+          def ret
+            return_address = @cpu.stack_pop
+            @cpu.jump_to(address: return_address)
+          end
+
+          # M-cycle 1: Fetches opcode.
+          # M-cycle 2: Pops the LSB from the Stack.
+          # M-cycle 3: Pops the MSB from the Stack.
+          # M-cycle 4: Jumps to the return address
+          #            Enable interrupts (same cycle).
+          def reti
+            ret
+            @cpu.enable_interrupts
+          end
+        end
+      end
+    end
+  end
+end