amaterasu 0.6.0

data/lib/amaterasu/game_boy/cpu/instructions/add8.rb

@@ -0,0 +1,63 @@
+# frozen_string_literal: true
+
+module Amaterasu
+  module GameBoy
+    class Cpu
+      module Instructions
+        # Handles the logic related to all possible ADD instructions
+        #
+        # - ADD A, r8
+        # - ADD A, [HL]
+        # - ADD A, n8
+        class Add8 < Base
+          # @param cpu [Cpu] Holds a direct reference to the main Cpu object.
+          # @param source [Symbol] Operator, can be a register, :mem_hl, :imm8.
+          def initialize(cpu:, source:)
+            super(cpu:)
+
+            @mnemonic = "ADD A, #{source}"
+            @logic    = build_logic(source)
+          end
+
+          private
+
+          # Builds the logic for all ADD instructions.
+          # Returns a lambda object to be called by the CPU.
+          def build_logic(source)
+            case source
+            when :a      then -> { add_a(@registers.a) }
+            when :b      then -> { add_a(@registers.b) }
+            when :c      then -> { add_a(@registers.c) }
+            when :d      then -> { add_a(@registers.d) }
+            when :e      then -> { add_a(@registers.e) }
+            when :h      then -> { add_a(@registers.h) }
+            when :l      then -> { add_a(@registers.l) }
+            when :mem_hl then -> { add_a(@cpu.bus_read(address: @registers.hl)) }
+            when :imm8   then -> { add_a(@cpu.fetch_next_byte) }
+            else
+              raise ArgumentError, 'Unknown Add8 source'
+            end
+          end
+
+          # Adds a given value into register A.
+          #
+          # - Sets the Zero flag if the result is zero, otherwise clears it.
+          # - Sets the Subtraction flag to zero.
+          # - Sets the Half Carry flag if there was overflow from Bit 3, otherwise clears it.
+          # - Sets the Carry flag if there was overflow from Bit 7, otherwise clears it.
+          def add_a(value)
+            acc = @registers.a
+            result = @registers.a + value
+
+            @registers.z_flag = result.nobits?(0xFF)
+            @registers.n_flag = false
+            @registers.h_flag = (acc & 0x0F) + (value & 0x0F) > 0x0F
+            @registers.c_flag = result > 0xFF
+
+            @registers.a = result
+          end
+        end
+      end
+    end
+  end
+end

data/lib/amaterasu/game_boy/cpu/instructions/and.rb

@@ -0,0 +1,62 @@
+# frozen_string_literal: true
+
+module Amaterasu
+  module GameBoy
+    class Cpu
+      module Instructions
+        # Handles the logic related to all possible AND instructions
+        #
+        # - AND A, r8
+        # - AND A, [HL]
+        # - AND A, n8
+        class And < Base
+          # @param cpu [Cpu] Holds a direct reference to the main Cpu object.
+          # @param source [Symbol] Operator, can be a register, :mem_hl, :imm8.
+          def initialize(cpu:, source:)
+            super(cpu:)
+
+            @mnemonic = "AND A, #{source}"
+            @logic    = build_logic(source)
+          end
+
+          private
+
+          # Builds the logic for all AND instructions.
+          # Returns a lambda object to be called by the CPU.
+          def build_logic(source)
+            case source
+            when :a      then -> { and_a(@registers.a) }
+            when :b      then -> { and_a(@registers.b) }
+            when :c      then -> { and_a(@registers.c) }
+            when :d      then -> { and_a(@registers.d) }
+            when :e      then -> { and_a(@registers.e) }
+            when :h      then -> { and_a(@registers.h) }
+            when :l      then -> { and_a(@registers.l) }
+            when :mem_hl then -> { and_a(@cpu.bus_read(address: @registers.hl)) }
+            when :imm8   then -> { and_a(@cpu.fetch_next_byte) }
+            else
+              raise ArgumentError, 'Unknown And source'
+            end
+          end
+
+          # Performs a bitwise AND between a given value and the register A.
+          #
+          # - Sets the Zero flag if the result is zero, otherwise clears it.
+          # - Always clears the Subtraction flag.
+          # - Always sets the Half Carry flag.
+          # - Always clears the Carry flag.
+          def and_a(value)
+            result = @registers.a & value
+
+            @registers.z_flag = result.nobits?(0xFF)
+            @registers.n_flag = false
+            @registers.h_flag = true
+            @registers.c_flag = false
+
+            @registers.a = result
+          end
+        end
+      end
+    end
+  end
+end

data/lib/amaterasu/game_boy/cpu/instructions/base.rb

@@ -0,0 +1,38 @@
+# frozen_string_literal: true
+
+module Amaterasu
+  module GameBoy
+    class Cpu
+      module Instructions
+        # Defines the mnemonic, bytes and logic for the NOP instruction.
+        class Base
+          attr_reader :mnemonic
+
+          def initialize(cpu:)
+            @cpu = cpu
+            @registers = cpu.registers
+          end
+
+          def execute
+            @logic.call
+          end
+
+          private
+
+          def format_operand(operand)
+            return ''      if operand.nil?
+            return 'n8'    if operand == :imm8
+            return 'n16'   if operand == :imm16
+            return '[HL]'  if operand == :mem_hl
+            return '[HL+]' if operand == :mem_hli
+            return '[HL-]' if operand == :mem_hld
+            return '[C]'   if operand == :mem_c
+            return '[a8]'  if operand == :mem_unsig8
+
+            operand.to_s.upcase
+          end
+        end
+      end
+    end
+  end
+end

data/lib/amaterasu/game_boy/cpu/instructions/call.rb

@@ -0,0 +1,48 @@
+# frozen_string_literal: true
+
+module Amaterasu
+  module GameBoy
+    class Cpu
+      module Instructions
+        # Holds the logic of all the CALL instructions.
+        class Call < Base
+          # Creates a Call instruction object with a mnemonic and logic to be executed.
+          def initialize(cpu:, condition: nil)
+            super(cpu:)
+
+            @mnemonic = "CALL #{format_operand(condition)}, imm16"
+            @logic    = build_logic(condition)
+          end
+
+          private
+
+          # Returns a Proc object to be executed by the CPU at runtime.
+          def build_logic(condition)
+            case condition
+            when :nz then -> { call(@registers.z_flag.zero?) }
+            when :z  then -> { call(@registers.z_flag == 1) }
+            when :nc then -> { call(@registers.c_flag.zero?) }
+            when :c  then -> { call(@registers.c_flag == 1) }
+            else -> { call(true) }
+            end
+          end
+
+          # M-cycle 1: Fetches opcode.
+          # M-cycle 2: Fetches next immediate byte (lsb).
+          # M-cycle 3: Fetches next immediate byte (msb).
+          # ---------- Return early if condition not met.
+          # M-cycle 4: Pushes the msb of the PC onto the stack.
+          # M-cycle 5: Pushes the lsb of the PC onto the stack.
+          # M-cycle 6: Jumps to the call address.
+          def call(condition)
+            call_address = @cpu.fetch_next_word
+            return unless condition
+
+            @cpu.stack_push(value: @registers.pc)
+            @cpu.jump_to(address: call_address)
+          end
+        end
+      end
+    end
+  end
+end

data/lib/amaterasu/game_boy/cpu/instructions/cb_bit.rb

@@ -0,0 +1,52 @@
+# frozen_string_literal: true
+
+module Amaterasu
+  module GameBoy
+    class Cpu
+      module Instructions
+        # Holds the logic of all the BIT instructions.
+        class CbBit < Base
+          include Utils::BitOps
+
+          def initialize(cpu:, bit_pos:, target:)
+            super(cpu:)
+
+            @mnemonic = "BIT #{bit_pos}, #{format_operand(target)}"
+            @logic    = build_logic(bit_pos, target)
+          end
+
+          private
+
+          def build_logic(bit_pos, target)
+            case target
+            when :b      then -> { bit_test(bit_pos, @registers.b) }
+            when :c      then -> { bit_test(bit_pos, @registers.c) }
+            when :d      then -> { bit_test(bit_pos, @registers.d) }
+            when :e      then -> { bit_test(bit_pos, @registers.e) }
+            when :h      then -> { bit_test(bit_pos, @registers.h) }
+            when :l      then -> { bit_test(bit_pos, @registers.l) }
+            when :mem_hl then -> { bit_test(bit_pos, @cpu.bus_read(address: @registers.hl)) }
+            when :a      then -> { bit_test(bit_pos, @registers.a) }
+            else
+              raise ArgumentError, 'Unknown CbBit target'
+            end
+          end
+
+          # Checks the bit value from a given target at a given position [0-7].
+          #
+          # - Sets the zero flag if bit tested is 0, otherwise clears the flag.
+          # - Subtraction flag is always cleared.
+          # - Half Carry flag is always set.
+          # - Carry flag is untouched.
+          def bit_test(bit_pos, target_value)
+            bit_value = bit(target_value, bit_pos)
+
+            @registers.z_flag = bit_value.zero?
+            @registers.n_flag = false
+            @registers.h_flag = true
+          end
+        end
+      end
+    end
+  end
+end

data/lib/amaterasu/game_boy/cpu/instructions/cb_res.rb

@@ -0,0 +1,49 @@
+# frozen_string_literal: true
+
+module Amaterasu
+  module GameBoy
+    class Cpu
+      module Instructions
+        # Holds the logic of all the RES instructions.
+        class CbRes < Base
+          include Utils::BitOps
+
+          # Creates a new CbRes object containing the mnemonic (String) and logic (Proc).
+          def initialize(cpu:, bit_pos:, target:)
+            super(cpu:)
+
+            @mnemonic = "RES #{bit_pos}, #{format_operand(target)}"
+            @logic    = build_logic(bit_pos, target)
+          end
+
+          private
+
+          # @param bit_pos [Integer] Integer between 0 and 7.
+          # @param target [Symbol] Either a 8-bit register (:a, :b, :c, ...) or :mem_hl.
+          #
+          # @return [Proc] Logic to be executed by the Cpu.
+          #
+          def build_logic(bit_pos, target)
+            case target
+            when :a      then -> { @registers.a = clear_bit(@registers.a, bit_pos) }
+            when :b      then -> { @registers.b = clear_bit(@registers.b, bit_pos) }
+            when :c      then -> { @registers.c = clear_bit(@registers.c, bit_pos) }
+            when :d      then -> { @registers.d = clear_bit(@registers.d, bit_pos) }
+            when :e      then -> { @registers.e = clear_bit(@registers.e, bit_pos) }
+            when :h      then -> { @registers.h = clear_bit(@registers.h, bit_pos) }
+            when :l      then -> { @registers.l = clear_bit(@registers.l, bit_pos) }
+            when :mem_hl
+              lambda do
+                value_at_mem_hl = @cpu.bus_read(address: @registers.hl)
+                result = clear_bit(value_at_mem_hl, bit_pos)
+                @cpu.bus_write(address: @registers.hl, value: result)
+              end
+            else
+              raise ArgumentError, 'Unknown CbRes target'
+            end
+          end
+        end
+      end
+    end
+  end
+end

data/lib/amaterasu/game_boy/cpu/instructions/cb_rl.rb

@@ -0,0 +1,70 @@
+# frozen_string_literal: true
+
+module Amaterasu
+  module GameBoy
+    class Cpu
+      module Instructions
+        # Holds the logic of all the RL (Rotate Left Through Carry) instructions.
+        #
+        # - RL r8
+        # - RL [HL]
+        class CbRl < Base
+          include Utils::BitOps
+
+          def initialize(cpu:, target:)
+            super(cpu:)
+
+            @mnemonic = "RL #{format_operand(target)}"
+            @logic    = build_logic(target)
+          end
+
+          private
+
+          def build_logic(target)
+            case target
+            when :b      then -> { @registers.b = rl_reg8(@registers.b) }
+            when :c      then -> { @registers.c = rl_reg8(@registers.c) }
+            when :d      then -> { @registers.d = rl_reg8(@registers.d) }
+            when :e      then -> { @registers.e = rl_reg8(@registers.e) }
+            when :h      then -> { @registers.h = rl_reg8(@registers.h) }
+            when :l      then -> { @registers.l = rl_reg8(@registers.l) }
+            when :mem_hl then -> { rl_mem_hl }
+            when :a      then -> { @registers.a = rl_reg8(@registers.a) }
+            else
+              raise ArgumentError, 'Unknown CbRl target'
+            end
+          end
+
+          # [C] <- [7][6][5][4][3][2][1][0] <- [C]
+          # [7]    [6][5][4][3][2][1][0][C]
+          #
+          def rl_reg8(reg8_value)
+            carry_in = @registers.c_flag
+            old_bit7 = bit(reg8_value, 7)
+            result = (reg8_value << 1) | carry_in
+
+            @registers.clear_flags
+            @registers.z_flag = result.nobits?(0xFF)
+            @registers.c_flag = old_bit7 == 1
+
+            result
+          end
+
+          # Takes 2 extra cycles due to the Bus read and write operations.
+          def rl_mem_hl
+            value_at_mem_hl = @cpu.bus_read(address: @registers.hl)
+            carry_in = @registers.c_flag
+            old_bit7 = bit(value_at_mem_hl, 7)
+            result = (value_at_mem_hl << 1) | carry_in
+
+            @registers.clear_flags
+            @registers.z_flag = result.nobits?(0xFF)
+            @registers.c_flag = old_bit7 == 1
+
+            @cpu.bus_write(address: @registers.hl, value: result)
+          end
+        end
+      end
+    end
+  end
+end

data/lib/amaterasu/game_boy/cpu/instructions/cb_rlc.rb

@@ -0,0 +1,68 @@
+# frozen_string_literal: true
+
+module Amaterasu
+  module GameBoy
+    class Cpu
+      module Instructions
+        # Holds the logic of all the RLC (Rotate Left Circular) instructions.
+        #
+        # - RLC r8
+        # - RLC [HL]
+        class CbRlc < Base
+          include Utils::BitOps
+
+          def initialize(cpu:, target:)
+            super(cpu:)
+
+            @mnemonic = "RLC #{format_operand(target)}"
+            @logic    = build_logic(target)
+          end
+
+          private
+
+          def build_logic(target)
+            case target
+            when :b      then -> { @registers.b = rlc_reg8(@registers.b) }
+            when :c      then -> { @registers.c = rlc_reg8(@registers.c) }
+            when :d      then -> { @registers.d = rlc_reg8(@registers.d) }
+            when :e      then -> { @registers.e = rlc_reg8(@registers.e) }
+            when :h      then -> { @registers.h = rlc_reg8(@registers.h) }
+            when :l      then -> { @registers.l = rlc_reg8(@registers.l) }
+            when :mem_hl then -> { rlc_mem_hl }
+            when :a      then -> { @registers.a = rlc_reg8(@registers.a) }
+            else
+              raise ArgumentError, 'Unknown CbRlc target'
+            end
+          end
+
+          # [C]   <- [7][6][5][4][3][2][1][0] <- [7]
+          # [C=7]    [6][5][4][3][2][1][0][7]
+          #
+          def rlc_reg8(reg8_value)
+            old_bit7 = bit(reg8_value, 7)
+            result = (reg8_value << 1) | old_bit7
+
+            @registers.clear_flags
+            @registers.z_flag = result.nobits?(0xFF)
+            @registers.c_flag = old_bit7 == 1
+
+            result
+          end
+
+          # Takes 2 extra cycles due to the Bus read and write operations.
+          def rlc_mem_hl
+            value_at_mem_hl = @cpu.bus_read(address: @registers.hl)
+            old_bit7 = bit(value_at_mem_hl, 7)
+            result = (value_at_mem_hl << 1) | old_bit7
+
+            @registers.clear_flags
+            @registers.z_flag = result.nobits?(0xFF)
+            @registers.c_flag = old_bit7 == 1
+
+            @cpu.bus_write(address: @registers.hl, value: result)
+          end
+        end
+      end
+    end
+  end
+end

data/lib/amaterasu/game_boy/cpu/instructions/cb_rr.rb

@@ -0,0 +1,70 @@
+# frozen_string_literal: true
+
+module Amaterasu
+  module GameBoy
+    class Cpu
+      module Instructions
+        # Holds the logic of all the RR (Rotate Right Through Carry) instructions.
+        #
+        # - RR r8
+        # - RR [HL]
+        class CbRr < Base
+          include Utils::BitOps
+
+          def initialize(cpu:, target:)
+            super(cpu:)
+
+            @mnemonic = "RR #{format_operand(target)}"
+            @logic    = build_logic(target)
+          end
+
+          private
+
+          def build_logic(target)
+            case target
+            when :b      then -> { @registers.b = rr_reg8(@registers.b) }
+            when :c      then -> { @registers.c = rr_reg8(@registers.c) }
+            when :d      then -> { @registers.d = rr_reg8(@registers.d) }
+            when :e      then -> { @registers.e = rr_reg8(@registers.e) }
+            when :h      then -> { @registers.h = rr_reg8(@registers.h) }
+            when :l      then -> { @registers.l = rr_reg8(@registers.l) }
+            when :mem_hl then -> { rr_mem_hl }
+            when :a      then -> { @registers.a = rr_reg8(@registers.a) }
+            else
+              raise ArgumentError, 'Unknown CbRr target'
+            end
+          end
+
+          # [C] -> [7][6][5][4][3][2][1][0] -> [C]
+          #        [C][7][6][5][4][3][2][1] -> [0]
+          #
+          def rr_reg8(reg8_value)
+            carry_in = @registers.c_flag
+            old_bit0 = bit(reg8_value, 0)
+            result = (carry_in << 7) | (reg8_value >> 1)
+
+            @registers.clear_flags
+            @registers.z_flag = result.nobits?(0xFF)
+            @registers.c_flag = old_bit0 == 1
+
+            result
+          end
+
+          # Takes 2 extra cycles due to the Bus read and write operations.
+          def rr_mem_hl
+            value_at_mem_hl = @cpu.bus_read(address: @registers.hl)
+            carry_in = @registers.c_flag
+            old_bit0 = bit(value_at_mem_hl, 0)
+            result = (carry_in << 7) | (value_at_mem_hl >> 1)
+
+            @registers.clear_flags
+            @registers.z_flag = result.nobits?(0xFF)
+            @registers.c_flag = old_bit0 == 1
+
+            @cpu.bus_write(address: @registers.hl, value: result)
+          end
+        end
+      end
+    end
+  end
+end

data/lib/amaterasu/game_boy/cpu/instructions/cb_rrc.rb

@@ -0,0 +1,68 @@
+# frozen_string_literal: true
+
+module Amaterasu
+  module GameBoy
+    class Cpu
+      module Instructions
+        # Holds the logic of all the RRC (Rotate Right Circular) instructions.
+        #
+        # - RRC r8
+        # - RRC [HL]
+        class CbRrc < Base
+          include Utils::BitOps
+
+          def initialize(cpu:, target:)
+            super(cpu:)
+
+            @mnemonic = "RRC #{format_operand(target)}"
+            @logic    = build_logic(target)
+          end
+
+          private
+
+          def build_logic(target)
+            case target
+            when :b      then -> { @registers.b = rrc_reg8(@registers.b) }
+            when :c      then -> { @registers.c = rrc_reg8(@registers.c) }
+            when :d      then -> { @registers.d = rrc_reg8(@registers.d) }
+            when :e      then -> { @registers.e = rrc_reg8(@registers.e) }
+            when :h      then -> { @registers.h = rrc_reg8(@registers.h) }
+            when :l      then -> { @registers.l = rrc_reg8(@registers.l) }
+            when :mem_hl then -> { rrc_mem_hl }
+            when :a      then -> { @registers.a = rrc_reg8(@registers.a) }
+            else
+              raise ArgumentError, 'Unknown CbRrc target'
+            end
+          end
+
+          # [0] -> [7][6][5][4][3][2][1][0] -> [C]
+          #        [0][7][6][5][4][3][2][1] -> [C=0]
+          #
+          def rrc_reg8(reg8_value)
+            old_bit0 = bit(reg8_value, 0)
+            result = (old_bit0 << 7) | (reg8_value >> 1)
+
+            @registers.clear_flags
+            @registers.z_flag = result.nobits?(0xFF)
+            @registers.c_flag = old_bit0 == 1
+
+            result
+          end
+
+          # Takes 2 extra cycles due to the Bus read and write operations.
+          def rrc_mem_hl
+            value_at_mem_hl = @cpu.bus_read(address: @registers.hl)
+            old_bit0 = bit(value_at_mem_hl, 0)
+            result = (old_bit0 << 7) | (value_at_mem_hl >> 1)
+
+            @registers.clear_flags
+            @registers.z_flag = result.nobits?(0xFF)
+            @registers.c_flag = old_bit0 == 1
+
+            @cpu.bus_write(address: @registers.hl, value: result)
+          end
+        end
+      end
+    end
+  end
+end

data/lib/amaterasu/game_boy/cpu/instructions/cb_set.rb

@@ -0,0 +1,51 @@
+# frozen_string_literal: true
+
+module Amaterasu
+  module GameBoy
+    class Cpu
+      module Instructions
+        # Holds the logic of all the SET instructions.
+        #
+        # - SET u3, r8
+        # - SET u3, [HL]
+        class CbSet < Base
+          include Utils::BitOps
+
+          # Creates a new CbSet object containing the mnemonic (String) and logic (Proc).
+          def initialize(cpu:, bit_pos:, target:)
+            super(cpu:)
+
+            @mnemonic = "SET #{bit_pos}, #{format_operand(target)}"
+            @logic    = build_logic(bit_pos, target)
+          end
+
+          private
+
+          # @param bit_pos [Integer] Integer between 0 and 7.
+          # @param target [Symbol] Either a 8-bit register (:a, :b, :c, ...) or :mem_hl.
+          #
+          # @return [Proc] Setups what the instruction should execute at runtime.
+          #
+          def build_logic(bit_pos, target)
+            case target
+            when :a      then -> { @registers.a = set_bit(@registers.a, bit_pos) }
+            when :b      then -> { @registers.b = set_bit(@registers.b, bit_pos) }
+            when :c      then -> { @registers.c = set_bit(@registers.c, bit_pos) }
+            when :d      then -> { @registers.d = set_bit(@registers.d, bit_pos) }
+            when :e      then -> { @registers.e = set_bit(@registers.e, bit_pos) }
+            when :h      then -> { @registers.h = set_bit(@registers.h, bit_pos) }
+            when :l      then -> { @registers.l = set_bit(@registers.l, bit_pos) }
+            when :mem_hl
+              lambda do
+                result = set_bit(@cpu.bus_read(address: @registers.hl), bit_pos)
+                @cpu.bus_write(address: @registers.hl, value: result)
+              end
+            else
+              raise ArgumentError, 'Unknown CbSet target'
+            end
+          end
+        end
+      end
+    end
+  end
+end