amaterasu 0.6.0

data/lib/amaterasu/game_boy/cpu/instructions/cb_sla.rb

@@ -0,0 +1,69 @@
+# frozen_string_literal: true
+
+module Amaterasu
+  module GameBoy
+    class Cpu
+      module Instructions
+        # Holds the logic of all the SLA instructions.
+        #
+        # - SLA r8
+        # - SLA [HL]
+        class CbSla < Base
+          include Utils::BitOps
+
+          def initialize(cpu:, target:)
+            super(cpu:)
+
+            @mnemonic = "SLA #{format_operand(target)}"
+            @logic    = build_logic(target)
+          end
+
+          private
+
+          def build_logic(target)
+            case target
+            when :b      then -> { @registers.b = sla_reg8(@registers.b) }
+            when :c      then -> { @registers.c = sla_reg8(@registers.c) }
+            when :d      then -> { @registers.d = sla_reg8(@registers.d) }
+            when :e      then -> { @registers.e = sla_reg8(@registers.e) }
+            when :h      then -> { @registers.h = sla_reg8(@registers.h) }
+            when :l      then -> { @registers.l = sla_reg8(@registers.l) }
+            when :mem_hl then -> { sla_mem_hl }
+            when :a      then -> { @registers.a = sla_reg8(@registers.a) }
+            else
+              raise ArgumentError, 'Unknown CbSla target'
+            end
+          end
+
+          # Shift Left Arithmetically.
+          #
+          # C <- [7][6][5][4][3][2][1][0] <- 0
+          #
+          def sla_reg8(reg8_value)
+            old_bit7 = bit(reg8_value, 7)
+            result = reg8_value << 1
+
+            @registers.clear_flags
+            @registers.z_flag = result.nobits?(0xFF)
+            @registers.c_flag = old_bit7 == 1
+
+            result
+          end
+
+          # Takes 2 extra cycles due to the Bus read and write operations.
+          def sla_mem_hl
+            byte = @cpu.bus_read(address: @registers.hl)
+            old_bit7 = bit(byte, 7)
+            result = byte << 1
+
+            @registers.clear_flags
+            @registers.z_flag = result.nobits?(0xFF)
+            @registers.c_flag = old_bit7 == 1
+
+            @cpu.bus_write(address: @registers.hl, value: result)
+          end
+        end
+      end
+    end
+  end
+end

data/lib/amaterasu/game_boy/cpu/instructions/cb_sra.rb

@@ -0,0 +1,71 @@
+# frozen_string_literal: true
+
+module Amaterasu
+  module GameBoy
+    class Cpu
+      module Instructions
+        # Holds the logic of all the SRA instructions.
+        #
+        # - SRA r8
+        # - SRA [HL]
+        class CbSra < Base
+          include Utils::BitOps
+
+          def initialize(cpu:, target:)
+            super(cpu:)
+
+            @mnemonic = "SRA #{format_operand(target)}"
+            @logic    = build_logic(target)
+          end
+
+          private
+
+          def build_logic(target)
+            case target
+            when :b      then -> { @registers.b = sra_reg8(@registers.b) }
+            when :c      then -> { @registers.c = sra_reg8(@registers.c) }
+            when :d      then -> { @registers.d = sra_reg8(@registers.d) }
+            when :e      then -> { @registers.e = sra_reg8(@registers.e) }
+            when :h      then -> { @registers.h = sra_reg8(@registers.h) }
+            when :l      then -> { @registers.l = sra_reg8(@registers.l) }
+            when :mem_hl then -> { sra_mem_hl }
+            when :a      then -> { @registers.a = sra_reg8(@registers.a) }
+            else
+              raise ArgumentError, 'Unknown CbSra target'
+            end
+          end
+
+          # Shift Right Arithmetically.
+          #
+          # [7][6][5][4][3][2][1][0] -> C
+          #
+          def sra_reg8(reg8)
+            old_bit0 = bit(reg8, 0)
+            old_bit7 = bit(reg8, 7)
+            result = (old_bit7 << 7) | (reg8 >> 1)
+
+            @registers.clear_flags
+            @registers.z_flag = result.nobits?(0xFF)
+            @registers.c_flag = old_bit0 == 1
+
+            result
+          end
+
+          # Takes 2 extra cycles due to the Bus read and write operations.
+          def sra_mem_hl
+            byte = @cpu.bus_read(address: @registers.hl)
+            old_bit0 = bit(byte, 0)
+            old_bit7 = bit(byte, 7)
+            result = (old_bit7 << 7) | (byte >> 1)
+
+            @registers.clear_flags
+            @registers.z_flag = result.nobits?(0xFF)
+            @registers.c_flag = old_bit0 == 1
+
+            @cpu.bus_write(address: @registers.hl, value: result)
+          end
+        end
+      end
+    end
+  end
+end

data/lib/amaterasu/game_boy/cpu/instructions/cb_srl.rb

@@ -0,0 +1,69 @@
+# frozen_string_literal: true
+
+module Amaterasu
+  module GameBoy
+    class Cpu
+      module Instructions
+        # Holds the logic of all the SRL instructions.
+        #
+        # - SRL r8
+        # - SRL [HL]
+        class CbSrl < Base
+          include Utils::BitOps
+
+          def initialize(cpu:, target:)
+            super(cpu:)
+
+            @mnemonic = "SRL #{format_operand(target)}"
+            @logic    = build_logic(target)
+          end
+
+          private
+
+          def build_logic(target)
+            case target
+            when :b      then -> { @registers.b = srl_reg8(@registers.b) }
+            when :c      then -> { @registers.c = srl_reg8(@registers.c) }
+            when :d      then -> { @registers.d = srl_reg8(@registers.d) }
+            when :e      then -> { @registers.e = srl_reg8(@registers.e) }
+            when :h      then -> { @registers.h = srl_reg8(@registers.h) }
+            when :l      then -> { @registers.l = srl_reg8(@registers.l) }
+            when :mem_hl then -> { srl_mem_hl }
+            when :a      then -> { @registers.a = srl_reg8(@registers.a) }
+            else
+              raise ArgumentError, 'Unknown CbSrl target'
+            end
+          end
+
+          # Shift Right Logically.
+          #
+          # 0 -> [7][6][5][4][3][2][1][0] -> C
+          #
+          def srl_reg8(reg8)
+            old_bit0 = bit(reg8, 0)
+            result = reg8 >> 1
+
+            @registers.clear_flags
+            @registers.z_flag = result.nobits?(0xFF)
+            @registers.c_flag = old_bit0 == 1
+
+            result
+          end
+
+          # Takes 2 extra cycles due to the Bus read and write operations.
+          def srl_mem_hl
+            byte = @cpu.bus_read(address: @registers.hl)
+            old_bit0 = bit(byte, 0)
+            result = byte >> 1
+
+            @registers.clear_flags
+            @registers.z_flag = result.nobits?(0xFF)
+            @registers.c_flag = old_bit0 == 1
+
+            @cpu.bus_write(address: @registers.hl, value: result)
+          end
+        end
+      end
+    end
+  end
+end

data/lib/amaterasu/game_boy/cpu/instructions/cb_swap.rb

@@ -0,0 +1,67 @@
+# frozen_string_literal: true
+
+module Amaterasu
+  module GameBoy
+    class Cpu
+      module Instructions
+        # Holds the logic of all the SWAP instructions.
+        #
+        # - SWAP r8
+        # - SWAP [HL]
+        class CbSwap < Base
+          include Utils::BitOps
+
+          def initialize(cpu:, target:)
+            super(cpu:)
+
+            @mnemonic = "SWAP #{format_operand(target)}"
+            @logic    = build_logic(target)
+          end
+
+          private
+
+          def build_logic(target)
+            case target
+            when :b      then -> { @registers.b = swap(@registers.b) }
+            when :c      then -> { @registers.c = swap(@registers.c) }
+            when :d      then -> { @registers.d = swap(@registers.d) }
+            when :e      then -> { @registers.e = swap(@registers.e) }
+            when :h      then -> { @registers.h = swap(@registers.h) }
+            when :l      then -> { @registers.l = swap(@registers.l) }
+            when :mem_hl then -> { swap_mem_hl }
+            when :a      then -> { @registers.a = swap(@registers.a) }
+            else
+              raise ArgumentError, 'Unknown CbSwap target'
+            end
+          end
+
+          # Swaps the positions of the Upper and Lower 4 bits.
+          #
+          # 11110000 -> 00001111
+          #
+          def swap(target)
+            upper4 = (target >> 4) & 0x0F
+            result = (target << 4) | upper4
+
+            @registers.clear_flags
+            @registers.z_flag = result.nobits?(0xFF)
+
+            result
+          end
+
+          # Takes 2 extra cycles due to the Bus read and write operations.
+          def swap_mem_hl
+            byte = @cpu.bus_read(address: @registers.hl)
+            upper4 = (byte >> 4) & 0x0F
+            result = (byte << 4) | upper4
+
+            @registers.clear_flags
+            @registers.z_flag = result.nobits?(0xFF)
+
+            @cpu.bus_write(address: @registers.hl, value: result)
+          end
+        end
+      end
+    end
+  end
+end

data/lib/amaterasu/game_boy/cpu/instructions/cp.rb

@@ -0,0 +1,61 @@
+# frozen_string_literal: true
+
+module Amaterasu
+  module GameBoy
+    class Cpu
+      module Instructions
+        # Handles the logic related to all possible CP instructions
+        #
+        # - CP A, r8
+        # - CP A, [HL]
+        # - CP A, n8
+        class Cp < Base
+          # @param cpu [Cpu] Holds a direct reference to the main Cpu object.
+          # @param source [Symbol] Operator, can be a register, :mem_hl, :imm8.
+          def initialize(cpu:, source:)
+            super(cpu:)
+
+            @mnemonic = "CP A, #{source}"
+            @logic    = build_logic(source)
+          end
+
+          private
+
+          # Builds the logic for all CP instructions.
+          # Returns a lambda object to be called by the CPU.
+          def build_logic(source)
+            case source
+            when :a      then -> { cp_a(@registers.a) }
+            when :b      then -> { cp_a(@registers.b) }
+            when :c      then -> { cp_a(@registers.c) }
+            when :d      then -> { cp_a(@registers.d) }
+            when :e      then -> { cp_a(@registers.e) }
+            when :h      then -> { cp_a(@registers.h) }
+            when :l      then -> { cp_a(@registers.l) }
+            when :mem_hl then -> { cp_a(@cpu.bus_read(address: @registers.hl)) }
+            when :imm8   then -> { cp_a(@cpu.fetch_next_byte) }
+            else
+              raise ArgumentError, 'Unknown Cp source'
+            end
+          end
+
+          # Subtracts a given value from register A and discard the result.
+          #
+          # - Sets the Zero flag if the result is zero, otherwise clears it.
+          # - Always sets the Subtraction flag.
+          # - Sets the Half Carry flag if it needed to borrow from Bit 4.
+          # - Sets the Carry flag if it needed to borrow (acc < value).
+          def cp_a(value)
+            acc = @registers.a
+            result = @registers.a - value
+
+            @registers.z_flag = result.nobits?(0xFF)
+            @registers.n_flag = true
+            @registers.h_flag = (acc & 0x0F) < (value & 0x0F)
+            @registers.c_flag = acc < value
+          end
+        end
+      end
+    end
+  end
+end

data/lib/amaterasu/game_boy/cpu/instructions/daa.rb

@@ -0,0 +1,59 @@
+# frozen_string_literal: true
+
+module Amaterasu
+  module GameBoy
+    class Cpu
+      module Instructions
+        # Holds the logic for DAA instruction.
+        class Daa < Base
+          def initialize(cpu:)
+            super
+
+            @mnemonic = 'DAA'
+            @logic    = -> { daa }
+          end
+
+          private
+
+          # Decimal Adjust Accumulator.
+          #
+          # Is used after performing a given arithmetic operation (ADD, SUB, ADC, SBC)
+          # whose inputs were in Binary-Coded Decimal (BCD).
+          # So after running this instruction the numbers would be adjusted to BCD format.
+          #
+          # This instruction never clears the Carry flag (1 => 0).
+          # It either preserves the value (0 => 0), (1 => 1) or sets it (0 => 1).
+          #
+          def daa
+            acc = @registers.a
+            carry_in = @registers.c_flag
+            new_carry = carry_in == 1
+            bcd_correction = 0x00
+
+            if @registers.n_flag.zero?
+              bcd_correction |= 0x06 if @registers.h_flag == 1 || (acc & 0x0F) > 0x09
+
+              if @registers.c_flag == 1 || (acc & 0xFF) > 0x99
+                bcd_correction |= 0x60
+                new_carry = true
+              end
+
+              bcd_adjusted = acc + bcd_correction
+            else
+              bcd_correction |= 0x06 if @registers.h_flag == 1
+              bcd_correction |= 0x60 if @registers.c_flag == 1
+
+              bcd_adjusted = acc - bcd_correction
+            end
+
+            @registers.z_flag = bcd_adjusted.nobits?(0xFF)
+            @registers.h_flag = false
+            @registers.c_flag = new_carry
+
+            @registers.a = bcd_adjusted
+          end
+        end
+      end
+    end
+  end
+end

data/lib/amaterasu/game_boy/cpu/instructions/dec.rb

@@ -0,0 +1,64 @@
+# frozen_string_literal: true
+
+module Amaterasu
+  module GameBoy
+    class Cpu
+      module Instructions
+        # Holds the logic of all the Decrement instructions.
+        class Dec < Base
+          def initialize(cpu:, operand:)
+            super(cpu:)
+
+            @mnemonic = "DEC #{format_operand(operand)}"
+            @logic    = build_logic(operand)
+          end
+
+          private
+
+          def build_logic(operand)
+            case operand
+            when :a      then -> { @registers.a = dec(@registers.a) }
+            when :b      then -> { @registers.b = dec(@registers.b) }
+            when :c      then -> { @registers.c = dec(@registers.c) }
+            when :d      then -> { @registers.d = dec(@registers.d) }
+            when :e      then -> { @registers.e = dec(@registers.e) }
+            when :h      then -> { @registers.h = dec(@registers.h) }
+            when :l      then -> { @registers.l = dec(@registers.l) }
+            when :bc     then -> { @registers.bc = dec16(@registers.bc) }
+            when :de     then -> { @registers.de = dec16(@registers.de) }
+            when :hl     then -> { @registers.hl = dec16(@registers.hl) }
+            when :sp     then -> { @registers.sp = dec16(@registers.sp) }
+            when :mem_hl
+              lambda {
+                value_at_mem_hl = @cpu.bus_read(address: @registers.hl)
+                @cpu.bus_write(address: @registers.hl, value: dec(value_at_mem_hl))
+              }
+            else
+              raise ArgumentError, 'Unknown Dec operand'
+            end
+          end
+
+          # M-cycle 1: Decrements a 8-bit value, sets the flags.
+          #
+          def dec(value)
+            result = value - 1
+
+            @registers.z_flag = result.nobits?(0xFF)
+            @registers.n_flag = true
+            @registers.h_flag = value.nobits?(0x0F)
+
+            result
+          end
+
+          # M-cycle 1: Decrements a 16-bit register value.
+          # M-cycle 2: Internal processing due to the 16-bit subtraction.
+          # ---------  Flags are untouched in the dec16.
+          #
+          def dec16(reg16)
+            @cpu.sub16(reg16, 1)
+          end
+        end
+      end
+    end
+  end
+end

data/lib/amaterasu/game_boy/cpu/instructions/di.rb

@@ -0,0 +1,21 @@
+# frozen_string_literal: true
+
+module Amaterasu
+  module GameBoy
+    class Cpu
+      module Instructions
+        # Holds the logic of the DI (Disable Interrupts) instruction.
+        class Di < Base
+          def initialize(cpu:)
+            super
+
+            @mnemonic = 'DI'
+            @bytes    = 1
+            @m_cycles = 1
+            @logic    = -> { @cpu.disable_interrupts }
+          end
+        end
+      end
+    end
+  end
+end

data/lib/amaterasu/game_boy/cpu/instructions/ei.rb

@@ -0,0 +1,19 @@
+# frozen_string_literal: true
+
+module Amaterasu
+  module GameBoy
+    class Cpu
+      module Instructions
+        # Holds the logic of the DI (Disable Interrupts) instruction.
+        class Ei < Base
+          def initialize(cpu:)
+            super
+
+            @mnemonic = 'EI'
+            @logic    = -> { @cpu.enable_interrupts }
+          end
+        end
+      end
+    end
+  end
+end

data/lib/amaterasu/game_boy/cpu/instructions/halt.rb

@@ -0,0 +1,19 @@
+# frozen_string_literal: true
+
+module Amaterasu
+  module GameBoy
+    class Cpu
+      module Instructions
+        # Handles the logic for the HALT instruction.
+        class Halt < Base
+          def initialize(cpu:)
+            super
+
+            @mnemonic = 'HALT'
+            @logic    = -> { @cpu.halt }
+          end
+        end
+      end
+    end
+  end
+end

data/lib/amaterasu/game_boy/cpu/instructions/inc.rb

@@ -0,0 +1,64 @@
+# frozen_string_literal: true
+
+module Amaterasu
+  module GameBoy
+    class Cpu
+      module Instructions
+        # Holds the logic of all the INC (Increment) instructions.
+        class Inc < Base
+          def initialize(cpu:, operand:)
+            super(cpu:)
+
+            @mnemonic = "INC #{format_operand(operand)}"
+            @logic    = build_logic(operand)
+          end
+
+          private
+
+          def build_logic(operand)
+            case operand
+            when :a      then -> { @registers.a = inc(@registers.a) }
+            when :b      then -> { @registers.b = inc(@registers.b) }
+            when :c      then -> { @registers.c = inc(@registers.c) }
+            when :d      then -> { @registers.d = inc(@registers.d) }
+            when :e      then -> { @registers.e = inc(@registers.e) }
+            when :h      then -> { @registers.h = inc(@registers.h) }
+            when :l      then -> { @registers.l = inc(@registers.l) }
+            when :bc     then -> { @registers.bc = inc16(@registers.bc) }
+            when :de     then -> { @registers.de = inc16(@registers.de) }
+            when :hl     then -> { @registers.hl = inc16(@registers.hl) }
+            when :sp     then -> { @registers.sp = inc16(@registers.sp) }
+            when :mem_hl
+              lambda do
+                value_at_mem_hl = @cpu.bus_read(address: @registers.hl)
+                @cpu.bus_write(address: @registers.hl, value: inc(value_at_mem_hl))
+              end
+            else
+              raise ArgumentError, 'Unknown Inc operand'
+            end
+          end
+
+          # M-cycle 1: Increments a 8-bit value, sets the flags.
+          #
+          def inc(value)
+            result = value + 1
+
+            @registers.z_flag = result.nobits?(0xFF)
+            @registers.n_flag = false
+            @registers.h_flag = value.allbits?(0x0F)
+
+            result
+          end
+
+          # M-cycle 1: Increments a 16-bit register value.
+          # M-cycle 2: Internal processing due to the 16-bit addition.
+          # ---------  Flags are untouched in the inc16.
+          #
+          def inc16(reg16)
+            @cpu.add16(reg16, 1)
+          end
+        end
+      end
+    end
+  end
+end

data/lib/amaterasu/game_boy/cpu/instructions/jp.rb

@@ -0,0 +1,54 @@
+# frozen_string_literal: true
+
+module Amaterasu
+  module GameBoy
+    class Cpu
+      module Instructions
+        # Holds the logic of all the load instructions.
+        class Jp < Base
+          def initialize(cpu:, location:, condition: nil)
+            super(cpu:)
+
+            @mnemonic = "JP #{format_operand(condition)}, #{format_operand(location)}"
+            @logic    = build_logic(location, condition)
+          end
+
+          private
+
+          def build_logic(location, condition)
+            if condition.nil?
+              case location
+              when :imm16 then -> { @cpu.jump_to(address: @cpu.fetch_next_word) }
+              when :hl then -> { @registers.pc = @registers.hl } # No extra cycle
+              else
+                raise ArgumentError, 'Unknown Jp location'
+              end
+            else
+              case condition
+              when :nz then -> { jp(condition: @registers.z_flag.zero?) }
+              when :nc then -> { jp(condition: @registers.c_flag.zero?) }
+              when :z  then -> { jp(condition: @registers.z_flag == 1) }
+              when :c  then -> { jp(condition: @registers.c_flag == 1) }
+              else
+                raise ArgumentError, 'Unknown Jp condition'
+              end
+            end
+          end
+
+          # M-cycle 1: Fetches the opcode.
+          # M-cycle 2: Fetches next immediate byte (lsb).
+          # M-cycle 3: Fetches next immediate byte (msb).
+          # ---------  Returns early if condition is not met.
+          # M-cycle 4: Jumps to the address (takes 1 internal cycle).
+          #
+          def jp(condition:)
+            address = @cpu.fetch_next_word
+            return unless condition
+
+            @cpu.jump_to(address:)
+          end
+        end
+      end
+    end
+  end
+end

data/lib/amaterasu/game_boy/cpu/instructions/jr.rb

@@ -0,0 +1,45 @@
+# frozen_string_literal: true
+
+module Amaterasu
+  module GameBoy
+    class Cpu
+      module Instructions
+        # Holds the logic of all the JR (Jump Relative) instructions.
+        class Jr < Base
+          def initialize(cpu:, condition: nil)
+            super(cpu:)
+
+            @mnemonic = "JR #{format_operand(condition)}, e8"
+            @logic    = build_logic(condition)
+          end
+
+          private
+
+          def build_logic(condition)
+            case condition
+            when :nz then -> { jr(@registers.z_flag.zero?) }
+            when :z  then -> { jr(@registers.z_flag == 1) }
+            when :nc then -> { jr(@registers.c_flag.zero?) }
+            when :c  then -> { jr(@registers.c_flag == 1) }
+            else -> { jr(true) }
+            end
+          end
+
+          # Jumps relative to a signed offset.
+          #
+          # - CPU always fetches the unsigned byte.
+          # - Calculates the offset by signing the value between -128 and +127.
+          # - If it's a conditional jump, check the condition and return early if it's false.
+          # - If the condition is true or there is no condition, jump.
+          def jr(cc)
+            unsigned_byte = @cpu.fetch_next_byte
+            offset = @cpu.sign_value(unsigned_byte)
+            return unless cc
+
+            @cpu.jump_to(address: @registers.pc + offset)
+          end
+        end
+      end
+    end
+  end
+end