HDLRuby 2.11.12 → 3.0.0

data/README.md

@@ -3,6 +3,25 @@
 HDLRuby is a library for describing and simulating digital electronic
 systems.
 
+__Note__:
+
+If you are new to HDLRuby, it is recommended that you consult first the following tutorial (even if you are a hardware person):
+
+ * [HDLRuby tutorial for software people](tuto/tutorial_sw.md)
+
+__What's new__
+
+For HDLRuby version 3.0.0:
+
+ * This section;
+
+ * [The sequencers](#sequencer-software-like-hardware-coding-stdsequencerrb) for software-like hardware design;
+
+ * A [tutorial](tuto/tutorial_sw.md) for software people;
+
+ * The stable [standard libraries](#standard-libraries) are loaded by default.
+
+
 __Install__:
 
 The recommended installation method is from rubygem as follows:
@@ -20,14 +39,14 @@ git clone HDLRuby
 __Warning__: 
 
  - This is still preliminary work which may change before we release a stable version.
- - It is highly recommended to have both basic knowledges of the Ruby language and hardware description languages before using HDLRuby.
+ - It is highly recommended to have both basic knowledge of the Ruby language and hardware description languages before using HDLRuby.
 
 
 # Compiling HDLRuby descriptions
 
 ## Using the HDLRuby compiler
 
-'hdrcc' is the HDLRuby compiler. It takes as input an HDLRuby file, checks it, and can produce as output a Verilog HDL, VHDL, or a YAML low-level descriptions of HW components but it can also simulate the input description.
+'hdrcc' is the HDLRuby compiler. It takes as input an HDLRuby file, checks it, and can produce as output a Verilog HDL, VHDL, or a YAML low-level description of HW components but it can also simulate the input description.
 
 
 __Usage__:
@@ -49,68 +68,76 @@ Where:
 | `-v, --verilog`   | Output in Verilog HDL format                         |
 | `-V, --vhdl`      | Output in VHDL format                                |
 | `-s, --syntax`    | Output the Ruby syntax tree                          |
-| `-C, --clang`     | Output the C code of the standalone simulator.       |
-| `-S, --sim`       | Perform the simulation with the default engine.      |
-| `--csim`          | Perform the simulation with the standalone engine.   |
-| `--rsim`          | Perform the simulation with the Ruby engine.         |
-| `--rcsim`         | Perform the simulation with the Hybris engine.       |
+| `-C, --clang`     | Output the C code of the standalone simulator        |
+| `-S, --sim`       | Perform the simulation with the default engine       |
+| `--csim`          | Perform the simulation with the standalone engine    |
+| `--rsim`          | Perform the simulation with the Ruby engine          |
+| `--rcsim`         | Perform the simulation with the Hybris engine        |
 | `--vcd`           | Make the simulator generate a VCD file               |
 | `-d, --directory` | Specify the base directory for loading the HDLRuby files |
 | `-D, --debug`     | Set the HDLRuby debug mode |
 | `-t, --top system`| Specify the top system describing the circuit to compile |
 | `-p, --param x,y,z`     | Specify the generic parameters                 |
-| `--version `      | Print the version number, then exit                  |
+| `--get-samples`   | Copy the sample directory (hdr_samples) to current one, then exit |
+| `--version`       | Show the version number, then exit                  |
 | `-h, --help`      | Show the help message                                    |
 
 __Notes__:
 
 * If no top system is given, it is automatically looked for from the input file.
 * If no option is given, it simply checks the input file.
-* The simulator option (-S) requires a standard compiler (accessible through the command `cc`) to be available in the executable path.
+* If you are new to HDLRuby, or if you want to see how new features work, we strongly encourage to get a local copy of the test HDLRuby sample using:  
+    
+  ```bash
+  hdrcc --get-samples
+  ```  
+    
+  Then in your current directory (folder) the `hdr_samples` subdirectory will appear that contains several HDLRuby example files. For details about the samples can be found there: [samples](#sample-hdlruby-descriptions).
+
 
 __Examples__:
 
 * Compile system named `adder` from `adder.rb` input file and generate a low-level YAML description into directory `adder`:
 
-```
+```bash
 hdrcc --yaml --top adder adder.rb adder
 ```
 
 * Compile `adder.rb` input file and generate a low-level Verilog HDL description into directory `adder`:
 
-```
+```bash
 hdrcc -v adder.rb adder
 ```
   
 * Compile system `adder` whose bit width is generic from `adder_gen.rb` input file to a 16-bit circuit low-level VHDL description into directory `adder`:
 
-```
+```bash
 hdrcc -V -t adder --param 16 adder_gen.rb adder
 ```
 
 * Compile system `multer` with inputs and output bit width is generic from `multer_gen.rb` input file to a 16x16->32-bit circuit whose low-level YAML description into directory `multer`:
 
-```
+```bash
 hdrcc -y -t multer -p 16,16,32 multer_gen.rb multer
 ```
 
-* Simulate the circuit described in file `counter_bench.rb` using the default simluation engine and putting the simulator's files in directory `counter`:
+* Simulate the circuit described in file `counter_bench.rb` using the default simulation engine and putting the simulator's files in directory `counter`:
 
-```
+```bash
 hdrcc -S counter_bench.rb counter
 ```
 
-As a policy, the default simulation enigne is set to the fastest one (cuttently it is the hybrid engine).
+As a policy, the default simulation engine is set to the fastest one (currently it is the hybrid engine).
 
 * Run in interactive mode.
 
-```
+```bash
 hdrcc -I
 ```
 
 * Run in interactive mode using pry as UI.
 
-```
+```bash
 hdrcc -I pry
 ```
 
@@ -166,13 +193,13 @@ The second specificity of HDLRuby is that it supports natively all the features
 
 __Notes__:
 
-- It is still possible to extend HDLRuby to support hardware descriptions of a higher level than RTL, please refer to section [Extending HDLRuby](#extend) for more details.
+- It is still possible to extend HDLRuby to support hardware descriptions of a higher level than RTL, please refer to section [Extending HDLRuby](#extending-hdlruby) for more details.
 - In this document, HDLRuby constructs will often be compared to their Verilog HDL or VHDL equivalents for simpler explanations.
 
 ## Introduction
 
 This introduction gives a glimpse of the possibilities of the language.
-However, we do recommend consulting the section about the [high-level programming features](#highfeat) to have a more complete view of the advanced possibilities of this language.
+However, we do recommend consulting the section about the [high-level programming features](#high-level-programming-features) to have a more complete view of the advanced possibilities of this language.
 
 At first glance, HDLRuby appears like any other HDL (like Verilog HDL or VHDL), for instance, the following code describes a simple D-FF:
 
@@ -187,7 +214,7 @@ system :dff do
 end
 ```
 
-As it can be seen in the code above, `system` is the keyword used for describing a digital circuit. This keyword is an equivalent of the Verilog HDL `module`. In such a system, signals are declared using a `<type>.<direction>` construct where `type` is the data type of the signal (e.g., `bit` as in the code above) and `direction` indicates if the signal is an input, an output, an inout or an inner one; and executable blocks (similar to `always` block of Verilog HDL) are described using the `par` keyword when they are parallel and `seq` when they are sequential (i.e., with respectively non-blocking and blocking assignments).
+As can be seen in the code above, `system` is the keyword used for describing a digital circuit. This keyword is the equivalent of the Verilog HDL `module`. In such a system, signals are declared using a `<type>.<direction>` construct where `type` is the data type of the signal (e.g., `bit` as in the code above) and `direction` indicates if the signal is an input, an output, an inout or an inner one; and executable blocks (similar to `always` block of Verilog HDL) are described using the `par` keyword when they are parallel and `seq` when they are sequential (i.e., with respectively non-blocking and blocking assignments).
 
 After such a system has been defined, it can be instantiated. For example, a single instance of the `dff` system named `dff0` can be declared as follows:
 
@@ -195,7 +222,7 @@ After such a system has been defined, it can be instantiated. For example, a sin
 dff :dff0
 ```
 
-The ports of this instance can then be accessed to be used like any other signals, e.g., `dff0.d` for access the `d` input of the FF.
+The ports of this instance can then be accessed to be used like any other signals, e.g., `dff0.d` for accessing the `d` input of the FF.
 
 Several instances can also be declared in a single statement. For example, a 2-bit counter based on the previous `dff` circuits can be described as follows:
 
@@ -230,7 +257,7 @@ system :counter2 do
 end
 ```
 
-In the code above, two possible connection methods are shown: for `dff0` ports are connected by name, and for `dff1` ports are connected by declaration order. Please notice that it is also possible to connect only a subset of the ports while declaring and to reconnect already connected ports in further statements.
+In the code above, two possible connection methods are shown: for `dff0` ports are connected by name, and for `dff1` ports are connected by declaration order. Please notice that it is also possible to connect only a subset of the ports while declaring, and to reconnect already connected ports in further statements.
 
 While a circuit can be generated from the code given above, a benchmark must
 be provided to test it. Such a benchmark is described by constructs called
@@ -285,8 +312,7 @@ end
 ```
 
 Then, it often happens that a system will end up with only one instance.
-In such a case, the system declaration can be omitted and an instance
-can be directly declared as follows:
+In such a case, the system declaration can be omitted, and an instance can be directly declared as follows:
 
 ```ruby
 instance :dff_single do
@@ -395,7 +421,7 @@ system :shifter do |n|
 end
 ```
 
-As it can be seen in the above examples, in HDLRuby, any construct is an object and therefore include methods. For instance, declaring a signal of a given `type` and direction (input, output, or inout) is done as follows so that `direction` is a method of the type, and the signal names are the arguments of this method (symbols or string are supported.)
+As can be seen in the above examples, in HDLRuby, any construct is an object and therefore include methods. For instance, declaring a signal of a given `type` and direction (input, output, or inout) is done as follows so that `direction` is a method of the type, and the signal names are the arguments of this method (symbols or string are supported.)
 
 ```ruby
 <type>.<direction> <list of symbols representing the signal>
@@ -430,7 +456,7 @@ system :sumprod_16_3456 do
 end
 ```
 
-The description above is straightforward, but it would be necessary to rewrite it if another circuit with different bit width or coefficients is to be designed. Moreover, if the number of coefficients is large an error in the expression will be easy to make and hard to find. A better approach would be to use a generic description of such a circuit as follows:
+The description above is straightforward, but it would be necessary to rewrite it if another circuit with different bit widths or coefficients is to be designed. Moreover, if the number of coefficients is large an error in the expression will be easy to make and hard to find. A better approach would be to use a generic description of such a circuit as follows:
 
 ```ruby
 system :sumprod do |typ,coefs|
@@ -446,7 +472,7 @@ end
 In the code above, there are two generic parameters,
 `typ`, which indicates the data type of the circuit, and `coefs`, which is assumed to be an array of coefficients. Since the number of inputs depends on the number of provided coefficients, it is declared as an array of `width` bit signed whose size is equal to the number of coefficients.
 
-The description of the sum of products may be more difficult to understand for people not familiar with the Ruby language. The `each_with_index` method iterates over the coefficients adding their index as iteration variable, the resulting operation (i.e., the iteration loop) is then modified by the `reduce` method that accumulates the code passed as arguments. This code, starting by `|sum,coef,i|` simply performs the addition of the current accumulation result (`sum`) with the product of the current coefficient (`coef`) and input (`ins[i]`, where `i` is the index) in the iteration. The argument `_b0` initializes the sum to `0`.
+The description of the sum of products may be more difficult to understand for people not familiar with the Ruby language. The `each_with_index` method iterates over the coefficients adding their index as an iteration variable, the resulting operation (i.e., the iteration loop) is then modified by the `reduce` method that accumulates the code passed as arguments. This code, starting by `|sum,coef,i|` simply performs the addition of the current accumulation result (`sum`) with the product of the current coefficient (`coef`) and input (`ins[i]`, where `i` is the index) in the iteration. The argument `_b0` initializes the sum to `0`.
 
 While slightly longer than the previous description, this description allows declaring a circuit implementing a sum of products with any bit width and any number of coefficients. For instance, the following code describes a signed 32-bit sum of products with  16 coefficients (just random numbers here).
 
@@ -456,7 +482,7 @@ sumprod(signed[32], [3,78,43,246, 3,67,1,8, 47,82,99,13, 5,77,2,4]).(:my_circuit
 
 As seen in the code above, when passing a generic argument for instantiating a generic system, the name of the instance is put between brackets for avoiding confusion.
 
-While the description `sumprod` is already usable in a wide range of cases, it still uses the standard addition and multiplication. However, there are cases where specific components are to be used for these operations, either for sake of performance, compliance with constraints, or because functionally different operations are required (e.g., saturated computations). This can be solved by using functions implementing such computation in place of operators, for example as follows:
+While the description `sumprod` is already usable in a wide range of cases, it still uses standard addition and multiplication. However, there are cases where specific components are to be used for these operations, either for sake of performance, compliance with constraints, or because functionally different operations are required (e.g., saturated computations). This can be solved by using functions implementing such computation in place of operators, for example as follows:
 
 ```ruby
 system :sumprod_func do |typ,coefs|
@@ -502,7 +528,7 @@ end
 
 It would however be necessary to add this argument when invoking the function, e.g., `add(1000,sum,mult(...))`. While this argument is relevant for addition with saturation, it is not for the other kind of addition operations, and hence, the code of `sumprod` is not general-purpose any longer.
 
-HDLRuby provides two ways to address such issues. First, it is possible to pass code as an argument. In the case of `sumprod` it would then be enough to add two arguments that perform the required addition and multiplication. The example is below:
+HDLRuby provides two ways to address such issues. First, it is possible to pass code as an argument. In the case of `sumprod`, it would then be enough to add two arguments that perform the required addition and multiplication. The example is below:
 
 ```ruby
 system :sumprod_proc do |add,mult,typ,coefs|
@@ -625,10 +651,10 @@ From there, we will describe in more detail each construct of HDLRuby.
 ## Naming rules
 <a name="names"></a>
 
-Several constructs in HDLRuby are referred to by name, e.g., systems and signals.  When such constructs are declared, their names are to be specified by Ruby symbols starting with a lower case. For example, `:hello` is a valid name declaration, but `:Hello` is not.
+Several constructs in HDLRuby are referred to by name, e.g., systems and signals.  When such constructs are declared, their names are to be specified by Ruby symbols starting with a lowercase. For example, `:hello` is a valid name declaration, but `:Hello` is not.
 
 After being declared, the construct can be referred to by using the name directly (i.e., without the `:` of Ruby symbols). For example, if a construct
-has been declared with `:hello` as name, it will be afterward referred to by `hello`.
+has been declared with `:hello` as the name, it will be afterward referred to by `hello`.
 
 ## Systems and signals
 
@@ -650,7 +676,7 @@ __Notes__:
   Ruby keywords (in which case the parentheses can be omitted) are as follows:
 
 ```ruby
-system :box do
+system :box does
 end
 ```
 
@@ -921,7 +947,7 @@ Where:
  * `<name>` is the name of the scope.
  * `<code>` is the code within the scope.
 
-Contrary to the case of scopes without a name, signals and instances declared within a named scope can be accessed outside using this name as a reference. For example, in the code below signal `sig` declared within scope named `scop` is accessed outside it using `scop.sig`:
+Contrary to the case of scopes without a name, signals, and instances declared within a named scope can be accessed outside using this name as a reference. For example, in the code below signal `sig` declared within scope named `scop` is accessed outside it using `scop.sig`:
 
 ```ruby
 sub :scop do
@@ -948,7 +974,7 @@ end
 In addition, it is possible to declare inner signals within an execution block.
 While such signals will be physically linked to the system, they are only accessible within the block they are declared into. This permits a tighter scope for signals, which improves the readability of the code and make it possible to declare several signals with identical names provided their respective scopes are different.
 
-An event represents a specific change of state of a signal. 
+An event represents a specific change in the state of a signal. 
 For example, a rising edge of a clock signal named `clk` will be represented by the event `clk.posedge`. In HDLRuby, events are obtained directly from
 expressions using the following methods: `posedge` for a rising edge, `negedge` for a falling edge, and `edge` for any edge.
 Events are described in more detail in section [Events](#events).
@@ -989,7 +1015,7 @@ system :with_sequential_behavior do
 end
 ```
 
-A sub-block can also have a different execution mode if it is declared using `seq`, which will force sequential execution mode, and `par` which will force parallel execution mode. For example, in the following code a parallel sub-block is declared within a sequential one:
+A sub-block can also have a different execution mode if it is declared using `seq`, which will force sequential execution mode and `par` which will force parallel execution mode. For example, in the following code a parallel sub-block is declared within a sequential one:
 
 ```ruby
 system :with_sequential_behavior do
@@ -1002,7 +1028,7 @@ system :with_sequential_behavior do
 end
 ```
 
-Sub blocks have their scope so that it is possible to declare signals without colliding with existing ones. For example, it is possible to
+Sunblocks have their scope so that it is possible to declare signals without colliding with existing ones. For example, it is possible to
 declare three different inner signals all called `sig` as follows:
 
 ```ruby
@@ -1117,7 +1143,7 @@ unshift do
 end
 ```
 
-For example the following code inserts two statements at the beginning of the current block:
+For example, the following code inserts two statements at the beginning of the current block:
 
 ```ruby
 par do
@@ -1129,7 +1155,7 @@ par do
 end
 ```
 
-The code above will actually result in the following block:
+The code above will result in the following block:
 
 ```ruby
 par do
@@ -1151,7 +1177,7 @@ In HDLRuby, dynamically reconfigurable devices are modeled by instances having m
 <instance>.choice(<list of named systems>)
 ```
 
-For example, assuming systems `sys0`, `sys1` and `sys2` have been previously declared a device named `dev012` able to be reconfigured to one of these three systems would be declared as follows (the connections of the instance, omitted in the example, can be done as usual):
+For example, assuming systems `sys0`, `sys1`, and `sys2` have been previously declared a device named `dev012` able to be reconfigured to one of these three systems would be declared as follows (the connections of the instance, omitted in the example, can be done as usual):
 
 ```ruby
 sys0 :dev012 # dev012 is at first a standard instance of sys0
@@ -1183,9 +1209,8 @@ These reconfiguration commands are treated as regular RTL statements in HDLRuby
 
 
 ## Events
-<a name="events"></a>
 
-Each behavior of a system is associated with a list of events, called a sensitivity list, that specifies when the behavior is to be executed. An event is associated with a signal and represents the instants when the signal reaches a given state.
+Each behavior of a system is associated with a list of events, called a sensitivity list, that specifies when the behavior is to be executed. An event is associated with a signal and represents the instant when the signal reaches a given state.
 
 There are three kinds of events: positive edge events represent the instants when their corresponding signals vary from 0 to 1, and negative edge events
 represent the instants when their corresponding signals vary from 1 to 0 and the change events represent the instants when their corresponding signals vary.
@@ -1211,7 +1236,6 @@ __Note:__
  - The `change` keyword can be omitted.
 
 ## Statements
-<a name="statements"></a>
 
 Statements are the basic elements of a behavioral description. They are regrouped in blocks that specify their execution mode (parallel or sequential).
 There are four kinds of statements: the transmit statement which computes expressions and sends the result to the target signals, the control statement
@@ -1224,7 +1248,7 @@ __Note__:
 
 ### Transmit statement
 
-A transmit statement is declared using the arrow operator `<=` within a behavior. Its right value is the expression to compute and its left value is a reference to the target signals (or parts of signals), i.e., the signals (or part of signals) that receive the computation result.
+A transmit statement is declared using the arrow operator `<=` within a behavior. Its right value is the expression to compute and its left value is a reference to the target signals (or parts of signals), i.e., the signals (or parts of signals) that receive the computation result.
 
 For example, the following code transmits the value `3` to signal `s0` and the sum of the values of signals `i0` and `i1` to the first four bits of signal `s1`:
 
@@ -1282,7 +1306,7 @@ end
 
 ### helsif
 
-In addition to `helse` it is possible to set additional conditions to an `hif` using the `helsif` keyword as follows:
+In addition to `helse`, it is possible to set additional conditions to an `hif` using the `helsif` keyword as follows:
 
 ```ruby
 hif <condition 0> do
@@ -1416,11 +1440,10 @@ While the underlying structure of any HDLRuby type is the bit vector, complex ty
 <a name="expressions"></a>
 
 Expressions are any construct that represents a value associated with a type.
-They include [immediate values](#values), [reference to signals](#references) and operations among other expressions using [expression operators](#operators).
+They include [immediate values](#immediate-values), [reference to signals](#references) and operations among other expressions using [expression operators](#expression-operators).
 
 
 ### Immediate values
-<a name="values"></a>
 
 The immediate values of HDLRuby can represent vectors of `bit`, `unsigned`, and `signed`, and integer or floating-point numbers. They are prefixed by a `_` character and include a header that indicates the vector type and the base used for representing the value, followed by a numeral representing the value. The bit width of a value is obtained by default from the width of the numeral, but it is also possible to specify it in the header. In addition, the character `_` can be put anywhere in the number for increasing the readability, it will be ignored.
 
@@ -1475,7 +1498,6 @@ __Notes__:
 
 
 ### References
-<a name="references"></a>
 
 References are expressions used to designate signals or a part of signals.
 
@@ -1517,7 +1539,6 @@ end
 ```
 
 ### Expression operators
-<a name="operators"></a>
 
 The following table gives a summary of the operators available in HDLRuby.
 More details are given for each group of operators in the subsequent sections.
@@ -1594,10 +1615,9 @@ __Notes__:
  
  - The operator precedence is the one of Ruby.
 
- - Ruby does not allow to override the `&&`, the `||` and the `?:` operators so that they are not present in HDLRuby. Instead of the `?:` operator, HDLRuby provides the more general multiplex operator `mux`. However, HDLRuby does not provide any replacement for the `&&` and the `||` operators, please refer to section [Logic operators](#logic) for a justification about this issue.
+ - Ruby does not allow to override the `&&`, the `||` and the `?:` operators so that they are not present in HDLRuby. Instead of the `?:` operator, HDLRuby provides the more general multiplex operator `mux`. However, HDLRuby does not provide any replacement for the `&&` and the `||` operators, please refer to section [Logic operators](#logic-and-shift-operators) for a justification about this issue.
 
 #### Assignment operators
-<a name="assignment"></a>
 
 The assignment operators can be used with any type. They are the connection and the transmission operators both being represented by `<=`.
 
@@ -1625,7 +1645,6 @@ __Notes__:
 
 
 #### Logic and shift operators
-<a name="logic"></a>
 
 In HDLRuby, the logic operators are all bitwise.  For performing Boolean computations, it is necessary to use single-bit values.  The bitwise logic binary operators are `&`, `|`, and `^`, and the unary one is `~`.  They have the same meaning as their Ruby equivalents.
 
@@ -1651,11 +1670,10 @@ sig.rl(3)
 ```
 
 It is possible to perform other kinds of shifts or rotations using the selection and the concatenation operators. Please refer to section [Concatenation and
-selection operators](#concat) for more details about these operators. 
+selection operators](#concatenation-and-selection-operators) for more details about these operators. 
 
 
 #### Conversion operators
-<a name="conversion"></a>
 
 The conversion operators are used to change the type of an expression.
 There are two kinds of such operators: the type pun that does not change the raw value of the expression and the type cast that changes the raw value.
@@ -1667,7 +1685,7 @@ The type puns include `to_bit`, `to_unsigned` and `to_signed` that convert expre
 sig.to_bit <= _b01010011
 ```
 
-The type casts change both the type and the value and are used to adjust the width of the types.  They can only be applied to vectors of `bit`, `signed`, or `unsinged` and can only increase the bit width (bit width can be truncated using the selection operator, please refer to the [next section](#concat)).
+The type casts change both the type and the value and are used to adjust the width of the types.  They can only be applied to vectors of `bit`, `signed`, or `unsinged` and can only increase the bit width (bit width can be truncated using the selection operator, please refer to the next section).
 These operators comprise the bit width conversions: `ljust`, `rjust`, `zext` and `sext`.
 
 More precisely, the bit width conversions operate as follows:
@@ -1701,7 +1719,6 @@ More precisely, the bit width conversions operate as follows:
 
 
 #### Concatenation and selection operators
-<a name="concat"></a>
 
 Concatenation and selection are done using the `[]` operator as follows:
 
@@ -1912,7 +1929,6 @@ Ruby functions can be compared to the macros of the C languages: they are more f
 
 
 ## Time
-<a name="time"></a>
 
 ### Time values
 <a name="time_val"></a>
@@ -1987,7 +2003,6 @@ sequential blocks. The execution semantic is the following:
 
 
 ## High-level programming features
-<a name="highfeat"></a>
 
 ### Using Ruby in HDLRuby
 
@@ -2525,7 +2540,6 @@ When describing a system, it is possible to disconnect or completely undefine a
 
 
 ## Extending HDLRuby
-<a name="extend"></a>
 
 Like any Ruby classes, the constructs of HDLRuby can be dynamically extended. If it is not recommended to change their internal structure, it is possible to add methods to them for an extension.
 
@@ -2653,8 +2667,7 @@ This way, calling directly `to_low` will automatically use `my_generation`.
 
 
 
-# Standard library
-<a name="library"></a>
+# Standard libraries
 
 The standard libraries are included in the module `Std`.
 They can be loaded as follows, where `<library name>` is the name of the
@@ -2670,9 +2683,23 @@ After the libraries are loaded, the module `Std` must be included as follows:
 include HDLRuby::High::Std
 ```
 
+> However, `hdrcc` does load the stable components of the standard library by default, so that you do not need to require nor include anything more to use them. In the current version, the stable components are the followings:  
+  
+  - `std/clocks.rb`  
+
+  - `std/fixpoint.rb`  
+
+  - `std/decoder.rb`  
 
+  - `std/fsm.rb`  
 
-## Clocks
+  - `std/sequencer.rb`  
+
+  - `std/sequencer_sync.rb`
+
+
+
+## Clocks: `std/clocks.rb`
 <a name="clocks"></a>
 
 The `clocks` library provides utilities for easier handling of clock synchronizations.
@@ -2694,7 +2721,7 @@ end
 
 __Note__: this library does generate all the RTL code for the circuit handling the division of the frequency. 
 
-## Counters
+## Counters: `std/counters.rb`
 <a name="counters"></a>
 
 This library provides two new constructs for implementing synthesizable wait statements.
@@ -2711,12 +2738,12 @@ Where:
  * `<clock>` is the clock to use, this argument can be omitted.
  * `<reset>` is the signal used to reset the counter used for waiting, this argument can be omitted.
 
-This statement can be used either inside or outside a clocked behavior. When used within a clocked behavior, the clock event of the behavior is used for the counter unless specified otherwise. When used outside such a behavior, the clock is the global default clock `$clk`. In both cases, the reset is the global reset `$rst` unless specified otherwise.
+This statement can be used either inside or outside a clocked behavior. When used within a clocked behavior, the clock event of the behavior is used for the counter unless specified otherwise. When used outside such behavior, the clock is the global default clock `$clk`. In both cases, the reset is the global reset `$rst` unless specified otherwise.
 
 The second construct is the `before` statement that activates a block until a given number of clock cycles is passed. Its syntax and usage are identical to the `after` statement.
 
 
-## Decoder
+## Decoder: `std/decoder.rb`
 <a name="decoder"></a>
 
 This library provides a new set of control statements for easily describing an instruction decoder.
@@ -2733,7 +2760,7 @@ Where `signal` is the signal to decode and `block` is a procedure block (i.e., R
 entry(<pattern>) <block>
 ```
 
-Where `pattern` is a string describing the pattern to match for the entry, and `block` is a procedure block describing the actions (some HDLRuby code) that are performed when the entry matches. The string describing the pattern can include `0` and `1` characters for specifying a specific value for the corresponding bit, or any alphabetical character for specifying a field in the pattern. The fields in the pattern can then be used by name in the block describing the action. When a letter is used several times within a pattern, the corresponding bits are concatenated and are used as a signal multi-bit signal in the block.
+Where `pattern` is a string describing the pattern to match the entry, and `block` is a procedure block describing the actions (some HDLRuby code) that are performed when the entry matches. The string describing the pattern can include `0` and `1` characters for specifying a specific value for the corresponding bit, or any alphabetical character for specifying a field in the pattern. The fields in the pattern can then be used by name in the block describing the action. When a letter is used several times within a pattern, the corresponding bits are concatenated and are used as a signal multi-bit signal in the block.
 
 For example, the following code describes a decoder for signal `ir` with two entries, the first one computing the sum of fields `x` and `y` and assigning the result to signal `s` and the second one computing the sum of fields `x` `y` and `z` and assigning the result to signal `s`:
 
@@ -2746,12 +2773,12 @@ end
 
 It can be noticed for field `z` in the example above that the bits are not required to be contiguous.
 
-## FSM
+## FSM: `std/fsm.rb`
 <a name="fsm"></a>
 
 This library provides a new set of control statements for easily describing a finite state machine (FSM).
 
-A finite state machine can be declared anywhere provided it is outside a behavior using the `fsm` keyword as follows:
+A finite state machine can be declared anywhere in a system provided it is outside a behavior using the `fsm` keyword as follows:
 
 ```ruby
 fsm(<event>,<reset>,<mode>) <block>
@@ -2794,7 +2821,7 @@ goto(cond,:st_a,:st_b,:st_c)
 
 Several goto statements can be used, the last one having priority provided it is taken (i.e., its condition corresponds to one of the target states). If no goto is taken, the next transition is the next declared one.
 
-For example, the following code describes a FSM describing a circuit that checks if two buttons (`but_a` and `but_b`) are pressed and released in sequence for activating an output signal (`ok`):
+For example, the following code describes an FSM describing a circuit that checks if two buttons (`but_a` and `but_b`) are pressed and released in sequence for activating an output signal (`ok`):
 
 ```ruby
 fsm(clk.posedge,rst,:sync) do
@@ -2818,7 +2845,7 @@ fsm(clk.posedge,rst,:sync) do
 end
 ```
 
-__Note__: the goto statements acts globally, i.e., they are independant of the place where they are declared within the state. For example for both following statements, the next state will always be `st_a` whatever `cond` maybe:
+__Note__: the goto statements act globally, i.e., they are independent of the place where they are declared within the state. For example for both following statements, the next state will always be `st_a` whatever `cond` maybe:
 
 ```ruby
    state(:st_0) do
@@ -2837,7 +2864,7 @@ That is to say, for a conditional `goto` for `st_1` the code should have been wr
    end
 ```
 
-The use of `goto` makes the design of FSM shorter for a majority of the cases, be sometimes, a finer control is required. For that purpose it is also possible to configure the FSM is `static` mode where the `next_state` statement that indicates implicitly the next state. Putting is static mode is done by passing `:static` as argument when declaring the FSM. For example the following FSM uses `next_state` to specify explicitly the next states depending on some condition signals `cond0` and `cond1`:
+The use of `goto` makes the design of FSM shorter for a majority of the cases, be sometimes, a finer control is required. For that purpose, it is also possible to configure the FSM is `static` mode where the `next_state` statement that indicates implicitly the next state. Putting in static mode is done by passing `:static` as an argument when declaring the FSM. For example, the following FSM uses `next_state` to specify explicitly the next states depending on some condition signals `cond0` and `cond1`:
 
 ```ruby
 fsm(clk.posedge,rst,:static)
@@ -2850,8 +2877,449 @@ fsm(clk.posedge,rst,:static)
 end
 ```
 
+## Sequencer (software-like hardware coding):: `std/sequencer.rb`
+<a name="sequencer"></a>
+
+This library provides a new set of control statements for describing the behavior of a circuit. Behind the curtain, these constructs build a finite state machine where states are deduced from the control points within the description.
+
+A sequencer can be declared anywhere in a system provided it is outside a behavior using the `sequencer` keyword as follows:
+
+```ruby
+sequencer(<clock>,<start>) <block>
+```
+
+Where `clock` is the clock signal advancing the execution of the sequence, `start` is the signal starting the execution, and `block` is the description of the sequence to be executed. Both `clock` and `start` can also be events (i.e., `posedge` or `negedge`).
+
+A sequence is a specific case of a `seq` block that includes the following software-like additional constructs:
+
+ - `step`: wait until the next event (given argument `event` of the sequencer).
+
+ - `sif(<condition>) <block>`: executes `block` if `condition` is met.
+
+ - `selsif(<condition>) <block>`: executes `block` if previous `sif` or `selsif` condition is not met and if current `condition` is met.
+
+ - `selse <block>`: executes `block` if the condition of the previous `sif` statement is not met.
+
+ - `swait(<condition>)`: waits until that `condition` is met.
+
+ - `swhile(<condition>) <block>`: executes `block` while `condition` is met.
+
+ - `sfor(<enumerable>) <block>`: executes `block` on each element of `enumerable`. This latter can be any enumerable Ruby object or any signal. If the signal is not hierarchical (e.g., bit vector), the iteration will be over each bit.
+
+ - `sbreak`: ends current iteration.
+
+ - `scontinue`: goes to the next step of the iteration.
+
+ - `sterminate`: ends the execution of the sequence.
+
+It is also possible to use enumerators (iterators) similar to the Ruby `each` using the following methods within sequences:
+
+ - `<object>.seach`: `object` any enumerable Ruby object or any signal. If a block is given, it works like `sfor`, otherwise, it returns a HDLRuby enumerator (please see [enumerator](#hdlruby-enumerators-and-enumerable-objects-stdsequencerrb) for details about them).
+
+ - `<object>.stimes`: can be used on integers and is equivalent to `seach` on each integer from 0 up to `object-1`.
+
+ - `<object>.supto(<last>)`: can be used on integers and is equivalent to `seach` on each integer from `object` up to `last`.
+
+ - `<object>.sdownto(<last>)`: can be used on an integer and is equivalent to `seach` on each integer from `object` down to `last`.
+
+The objects that support these methods are called _enumerable_ objects. They include the HDLRuby signals, the HDLRuby enumerators, and all the Ruby enumerable objects (e.g., ranges, arrays).
+
+
+Here are a few examples of sequencers synchronized in the positive edge of `clk` and starting when `start` becomes one. The first one computes the Fibonacci series until 100, producing a new term in signal `v` at each cycle:
+
+```ruby
+require 'std/sequencer.rb'
+include HDLRuby::High::Std
+
+system :a_circuit do
+   inner :clk, :start
+   [16].inner :a, :b
+   
+   sequencer(clk.posedge,start) do
+      a <= 0
+      b <= 1
+      swhile(v < 100) do
+         b <= a + b
+         a <= b - a
+      end
+   end
+end
+```
+
+The second one computes the square of the integers from 10 to 100, producing one result per cycle in signal `a`:
+
+```ruby
+inner :clk, :start
+[16].inner :a
+
+sequencer(clk.posedge,start) do
+   10.supto(100) { |i| a <= i*i }
+end
+```
+
+The third one reverses the content of memory `mem` (the result will be "!dlrow olleH"):
+
+```ruby
+inner :clk, :start
+bit[8][-12].inner mem: "Hello world!"
+
+sequencer(clk.posedge,start) do
+   mem.size.stimes do |i|
+      [8].inner :tmp
+      tmp       <= mem[i]
+      mem[i]    <= mem[-i-1]
+      mem[-i-1] <= tmp
+   end
+end
+```
+
+The fourth one computes the sum of all the elements of memory `mem` but stops if the sum is larger than 16:
+
+```ruby
+inner :clk, :start
+bit[8][-8].inner mem: [ _h02, _h04, _h06, _h08, _h0A, _h0C, _h0E ]
+bit[8] :sum
+
+sequencer(clk.posedge,start) do
+   sum <= 0
+   sfor(mem) do |elem|
+      sum <= sum + elem
+      sif(sum > 16) { sterminate }
+   end
+end
+```
+
+
+### HDLRuby enumerators and enumerable objects: `std/sequencer.rb`
+
+HDLRuby enumerators are objects for generating iterations within sequencers. They are created using the method `seach` on enumerable objects as presented in the previous section.
+
+The enumerators can be controlled using the following methods:
+
+ - `size`: returns the number of elements the enumerator can access.
+
+ - `type`: returns the type of the elements accessed by the enumerator.
+
+ - `seach`: returns the current enumerator. If a block is given, performs the iteration instead of returning an enumerator.
+
+ - `seach_with_index`: returns an enumerator over the elements of the current enumerator associated with their index position. If a block is given, performs the iteration instead of returning an enumerator.
+
+ - `seach_with_object(<obj>)`: returns an enumerator over the elements of the current enumerator associated with object `obj` (any object, HDLRuby or not, can be used). If a block is given, performs the iteration instead of returning an enumerator.
+
+ - `with_index`: identical to `seach_with_index`.
+
+ - `with_object(<obj>)`: identical to `seach_with_object`.
+
+ - `clone`: create a new enumerator on the same elements.
+
+ - `speek`: returns the current element pointed by the enumerator without advancing it.
+
+ - `snext`: returns the current element pointed by the enumerator and goes to the next one.
+
+ - `srewind`: restart the enumeration.
+
+ - `+`: concatenation of enumerators.
+
+It is also possible to define a custom enumerator using the following command:
+
+```ruby
+<enum> = senumerator(<typ>,<size>) <block>
+```
+
+Where `enum` is a Ruby variable referring to the enumerator, `typ` is the data type and `size` is the number of the elements to enumerate and `block` is the block that implements the access to an element by index. For example, an enumerator on a memory could be defined as follows:
+
+```ruby
+    bit[8][-8].inner mem: [ _h01, _h02, _h03, _h04, _h30, _h30, _h30, _h30 ]
+    [3].inner :addr
+    [8].inner :data
+
+    data <= mem[addr]
+
+    mem_enum = senumerator(bit[8],8) do |i|
+        addr <= i
+        step
+        data
+    end
+```
+
+In the code above, `mem_enum` is the variable referring to the resulting enumerator built for accessing memory `mem`. For the access, it is assumed that one cycle must be waited after the address is sets, and therefore a `step` command is added in the access procedure before `data` can be returned.
+
+With this basis, several algorithms have been implemented using enumerators and are usable for all the enumerable objects. All these algorithms are HW implantation of the Ruby Enumerable methods. They are accessible using the corresponding ruby method prefixed by character `s`. For example, the HW implementation of the ruby `all?` method is generated by the `sall?` method. In details:
+
+ - `sall?`: HW implementation of the Ruby `all?` method. Returns a single-bit signal. When 0 this value means false and when 1 it means true.
+
+ - `sany?`: HW implementation of the Ruby `any?` method. Returns a single-bit signal. When 0 this value means false and when 1 it means true.
+
+ - `schain`: HW implementation of the Ruby `chain`.
+
+ - `smap`: HW implementation of the Ruby `map` method. When used with a block returns a vector signal containing each computation result.
+
+ - `scompact`: HW implementation of the Ruby `compact` method. However, since there is no nil value in HW, use 0 instead for compacting. Returns a vector signal containing the compaction result.
+
+ - `scount`: HW implementation of the Ruby `count` method. Returns a signal whose bit width matches the size of the enumerator containing the count result.
+
+ - `scycle`: HW implementation of the Ruby `cycle` method.
+
+ - `sfind`: HW implementation of the Ruby `find` method. Returns a signal containing the found element, or 0 if not found.
+
+ - `sdrop`: HW implementation of the Ruby `drop` method. Returns a vector signal containing the remaining elements.
+
+ - `sdrop_while`: HW implementation of the Ruby `drop_while` method. Returns a vector signal containing the remaining elements.
+
+ - `seach_cons`: HW implementation of the Ruby `each_cons` method.
+
+ - `seach_slice`: HW implementation of the Ruby `each_slice` method.
+
+ - `seach_with_index`: HW implementation of the Ruby `each_with_index` method.
+
+ - `seach_with_object`: HW implementation of the Ruby `each_with_object` method.
+
+ - `sto_a`: HW implementation of the Ruby `to_a` method. Returns a vector signal containing all the elements of the enumerator.
+
+ - `sselect`: HW implementation of the Ruby `select` method. Returns a vector signal containing the selected elements.
+
+ - `sfind_index`: HW implementation of the Ruby `find_index` method. Returns the index of the found element or -1 if not.
+
+ - `sfirst`: HW implementation of the Ruby `first` method. Returns a vector signal containing the first elements.
+
+ - `sinclude?`: HW implementation of the Ruby `include?` method. Returns a single-bit signal. When 0 this value means false and when 1 it means true.
+
+ - `sinject`: HW implementation of the Ruby `inject` method. Return a signal of the type of elements containing the computation result.
+
+ - `smax`: HW implementation of the Ruby `max` method. Return a vector signal containing the found max values.
+
+ - `smax_by`: HW implementation of the Ruby `max_by` method. Return a vector signal containing the found max values.
+
+ - `smin`: HW implementation of the Ruby `min` method. Return a vector signal containing the found min values.
+
+ - `smin_by`: HW implementation of the Ruby `min_by` method. Return a vector signal containing the found min values.
+
+ - `sminmax`: HW implementation of the Ruby `minmax` method. Returns a 2-element vector signal containing the resulting min and max values.
+
+ - `sminmax_by`: HW implementation of the Ruby `minmax_by` method. Returns a 2-element vector signal containing the resulting min and max values.
+
+ - `snone?`: HW implementation of the Ruby `none?` method. Returns a single-bit signal. When 0 this value means false and when 1 it means true.
+
+ - `sone?`: HW implementation of the Ruby `one?` method. Returns a single-bit signal. When 0 this value means false and when 1 it means true.
+
+ - `sreject`: HW implementation of the Ruby `reject` method. Returns a vector signal containing the remaining elements.
+
+ - `sreverse_each`: HW implementation of the Ruby `reverse_each` method.
+
+ - `ssort`: HW implementation of the Ruby `sort` method. Returns a vector signal containing the sorted elements.
+
+ - `ssort_by`: HW implementation of the Ruby `sort_by` method. Returns a vector signal containing the sorted elements.
+
+ - `ssum`: HW implementation of the Ruby `sum` method. Returns a signal with the type of elements containing the sum result.
+
+ - `stake`: HW implementation of the Ruby `take` method. Returns a vector signal containing the taken elements.
+
+ - `stake_while`: HW implementation of the Ruby `take_while` method. Returns a vector signal containing the taken elements.
+
+ - `suniq`: HW implementation the Ruby `uniq` method. Returns a vector signal containing the selected elements.
+
+
+
+### Shared signals, arbiters and monitors: `std/sequencer_sync.rb`
+<a name="shared"></a>
+
+#### Shared signals
+
+Like any other processes, It is not possible for several sequencers to write to the same signal. This is because there would be race competition that may destroy physically the device if such operations where authorized. In standard RTL design, this limitation is overcome by implementing three-state buses, multiplexers and arbiters. However, HDLRuby sequencers supports another kind of signals called the *shared signals* that abstract the implementation details for avoiding race competition.
+
+The shared signals are declared like the other kind of signals from their type. The syntax is the following:
+
+```ruby
+<type>.shared <list of names>
+```
+
+They can also have an initial (and default) value when declared as follows:
+
+```ruby
+<type>.shared <list of names with initialization>
+```
+
+For example the following code declare two 8-bit shared signals `x` and `y` and two signed 16-bit shared signals initialized to 0 `u` and `v`:
+
+```ruby
+[8].shared :x, :y
+signed[8].shared u: 0, v: 0
+```
+
+A shared signals can then be read and written to by any sequencer from anywhere in the subsequent code of the current scope. However, they cannot be written to outside a sequencer. For example, the following code is valid:
+
+```ruby
+input :clk, :start
+[8].inner :val0, :val1
+[8].shared :x, :y
+
+val0 <= x+y
+par(clk.posedge) { val1 <= x+y }
+
+sequencer(clk.posedge,start) do
+   10.stimes { |i| x <= i }
+end
+
+sequencer(clk.posedge,start) do
+   5.stimes { |i| x <= i*2 ; y <= i*2 }
+end
+```
+
+But the following code is not valid:
+
+```ruby
+[8].shared w: 0
+
+par(clk.posedge) { w <= w + 1 }
+```
+
+By default, a shared signal acknowledge writing from the first sequencer that access it in order of declaration, the others are ignored. In the first example given above, that means for signal `x` the value is always the one written by the first sequencer, i.e., from 0 to 9 changing once per clock cycle. However, the value of signal `y` is set by the second sequencer since it is this one only that writes to this signal.
+
+This default behavior of shared signal avoids race competition, but is not very useful in practice. For a better control, it is possible to select which sequencer is to be acknowledged for writing. This is done by setting the number of the sequencer which can write the signal that controls the sharing accessed as follows:
+
+```ruby
+<shared signal>.select
+```
+
+The select value starts from 0 for the first sequencer writing to the shared signal, and is increased by one per writing sequencer. For example, in the first example, for selecting the second sequencer for writing to `x` the follow code can be added after this signal is declared:
+
+```ruby
+   x.select <= 1
+```
+
+This value can be changed at runtime too. For example, instead of setting the second sequencer, it is possible to switch sequencer every clock cycle as follows:
+
+```ruby
+   par(clk.posedge) { x.select <= x.select + 1 }
+```
+
+__Note__: this select sub signal is a standard RTL signal that has the same properties and limitations as the other ones, i.e., this is not a shared signal itself.
+
+
+#### Arbiters
+
+Usually, it is not the signals that we want to share, but the resources they drives. For example, in a CPU, it is an ALU that is shared as a whole rather than each of its input separately. In order to support such cases and ease the handling of shared signals, the library also provides the *arbiter* components. This component is instantiated like a standard module as follows, where `name` is the name of the arbiter instance:
+
+```ruby
+arbiter(:<name>).(<list of shared signal>)
+```
+
+When instantiated, an arbiter will take control of the select sub signals of the shared signals (hence, you cannot control the selection yourself for them any longer). In returns, it provides the possibility of requiring or releasing access to the shared signals. Requiring access is done by sending the value 1 to the arbiter, and releasing is done by sending the value 0. If a sequencer writes to a shared signal under arbitration without requiring access first, the write will simply be ignored.
+
+The following is an example of arbiter that controls access to shared signals `x` and `y` and two sequencers acquiring and releasing accesses to them:
+
+```ruby
+input :clk, :start
+[8].shared x, y
+arbiter(:ctrl_xy).(x,y)
+
+sequencer(clk.posedge,start) do
+   ctrl_xy <= 1
+   x <= 0 ; y <= 0
+   5.stime do |i|
+      x <= x + 1
+      y <= y + 2
+   end
+   ctrl_xy <= 0
+end
+
+sequencer(clk.posedge,start) do
+   ctrl_xy <= 1
+   x <= 2; y <= 1
+   10.stime do |i|
+      x <= x + 2
+      y <= y + 1
+   end
+   ctrl_xy <= 0
+end
+```
+
+In the example, both sequencers require access to signals `x` and `y` before accessing them and then releasing the access. 
+
+Requiring access does not guaranties that the access will be granted by the arbiter though. In the access is not granted, the write access will be ignored.
+The default access granting policy of an arbiter is the priority in order of sequencer declaration. I.e., if several sequencer are requiring at the same time, then the one declared the earliest in the code gains write access. For example, with the code given about, the first sequencer have write access to `x` and `y`, and since after five write cycles it releases access, the second sequencer can then write to these signals. However, not obtaining write access does not block the execution of the sequencer, simply, its write access to the corresponding shared signals is simple ignored. In the example, the second sequencer will do its first five loop cycles without any effect, and have only its five last ones that change the shared signals. To avoid such a behavior, it is possible to check if the write access is granted using arbiter sub signal `acquired`: if this signal is one in current sequencer, that means the access is granted, otherwise its is 0. For example the following will increase signal `x` only if write access is granted:
+
+```ruby
+hif(ctrl_xy.acquired) { x <= x + 1 }
+```
+
+The policy of an arbiter can be changed using command policy. You can either provide a new priority table, containing the number of the sequencers in order of priority (the first one having higher priority. The number of a sequencer is assign in order of declaration provided it uses the arbiter. For example, in the previous code, the second sequencer can be given higher priority by adding the following code after having declared the arbiter:
+
+```ruby
+ctrl_xy.policy([1,0])
+```
+
+It is also possible to set a more complex policy by providing to the policy method a block of code whose argument is a vector indicating which sequencer is currently requiring write access to the shared signals and whose result will be the number of the sequencer to grant the access. This code will be executing each time an write access is actually performed. For example, in the previous code, a policy switch priorities at each access can be implemented as follows:
 
-## Fixed-point (fixpoint)
+```ruby
+inner priority_xy: 0
+inner grant_xy
+ctrl_xy.policy do |acq|
+   hcase(acq)
+   hwhen(_b01) do
+      grant_xy <= 0
+      priority_xy <= ~priority_xy
+   end
+   hwhen(_b10) do
+      grant_xy <= 1
+      priority_xy <= ~priority_xy
+   end
+   hwhen(_b11) do
+      grant_xy <= priority_xy
+      priority_xy <= ~priority_xy
+   end
+   grant_xy
+end
+```
+
+As seen in the code above, each bit of the `acq` vector is one when the corresponding sequencer required an access or 0 otherwise, bit 0 corresponding to sequencer 0, bit 1 to sequencer 1 and so one.
+
+
+#### Monitors
+
+Arbiters a especially useful when we can ensure that the sequencers accessing the same resource do not overlap or when the do not need to synchronize with each other. If such synchronizations are required, instead of arbiters, it is possible to use the *monitor* components.
+
+The monitor component are instantiated like the arbiters as follows:
+
+```ruby
+monitor(:<name>).(<list of shared signals>)
+```
+
+Monitors are used exactly the same ways as arbiters (including the write access granting policies), but blocks the execution of the sequencers that require a write access until the access is granted. If we take the example of code with two sequencers given as illustration of arbiter usage, replacing the arbiter by a monitor as follows will lock the second sequencer until it can write to shared variables `x` and `y` ensuring that all its loop cycles have the specified result:
+
+```ruby
+monitor(:ctrl_xy).(x,y)
+```
+
+Since monitors locks processes, it automatically insert a step, hence to avoid confusion, aquiring access to a monitor is done by using method `lock` instead of assigning 1, and releasing is done by using method `unlock` instead of assigning 0. Hence, when using a monitor, the previous arbiter-based code should be rewriten as follows:
+
+```ruby
+input :clk, :start
+[8].shared x, y
+monitor(:ctrl_xy).(x,y)
+
+sequencer(clk.posedge,start) do
+   ctrl_xy.lock
+   x <= 0 ; y <= 0
+   5.stime do |i|
+      x <= x + 1
+      y <= y + 2
+   end
+   ctrl_xy.unlock
+end
+
+sequencer(clk.posedge,start) do
+   ctrl_xy.lock
+   x <= 2; y <= 1
+   10.stime do |i|
+      x <= x + 2
+      y <= y + 1
+   end
+   ctrl_xy.unlock
+end
+```
+
+## Fixed-point (fixpoint): `std/fixpoint.rb`
 <a name="fixpoint"></a>
 
 This library provides a new fixed point set of data types. These new data types can be bit vectors, unsigned or signed values and are declared respectively as follows:
@@ -2876,14 +3344,14 @@ In addition to the fixed point data type, a method is added to the literal objec
 <litteral>.to_fix(<number of bits after the decimal point>)
 ```
 
-For example, the following code converts a floating-point value to a fixed point value with 16 bits after the decimal point:
+For example, the following code converts a floating-point value to a fixed-point value with 16 bits after the decimal point:
 
 ```
 3.178.to_fix(16)
 ```
 
 
-## Channel
+## Channel: `std/channel.rb`
 <a name="channel"></a>
 
 This library provides a unified interface to complex communication protocols through a new kind of component called the channels that abstract the details of communication protocols. The channels can be used similarly to the ports of a system and are used through a unified interface so that changing the kind of channel, i.e., the communication protocol, does not require any modification of the code.
@@ -2923,9 +3391,9 @@ The access points to a channel can also be handled individually by declaring por
  * `output <name>`: declares a port for writing to the channel and associates them to `name` if any
  * `inout <name>`: declares a port for reading and writing to the channel and associates them to `name` if any
 
-Such port can then be accessed using the same `read` and `write` method of a channel, the difference being that they can also be configured for new access procedures using the `wrap` method:
+Such a port can then be accessed using the same `read` and `write` method of a channel, the difference being that they can also be configured for new access procedures using the `wrap` method:
 
- * `wrap(<args>) <code>`: creates a new port whose read or write procedure has the elements of `<args>` and the ones produced by `<code>` assign to the arguments of the read or write procedure.
+ * `wrap(<args>) <code>`: creates a new port whose read or write procedure has the elements of `<args>` and the ones produced by `<code>` assigned to the arguments of the read or write procedure.
 
 For example, assuming `mem` is a channel whose read and write access have as argument the target address and data signals, the following code creates a port for always accessing at address 0:
 
@@ -2939,7 +3407,7 @@ Some channels may include several branches, they are accessed by name using the
  
  * `branch(<name>)`: gets branch named `name` from the channel. This name can be any ruby object (e.g., a number) but it will be converted internally to a ruby symbol.
 
-A branch is a full-fledge channel and is used identically. For instance, the following code gets access to branch number 0 of channel `ch`, gets its inputs port, reads it, and put the result in signal `val` on the rising edges of signal `clk`:
+A branch is a full-fledged channel and is used identically. For instance, the following code gets access to branch number 0 of channel `ch`, gets its inputs port, reads it, and put the result in signal `val` on the rising edges of signal `clk`:
 
 ```ruby
 br = ch.branch(0)
@@ -3061,17 +3529,18 @@ end
 
 __Note__:
 
- * The code of the circuits, in the examples `producer8`, `consumer8`, and `producer_consummer8` is independent of the content of the channel. For example, the sample `with_channel.rb` (please see [sample](#sample)) use the same circuits with a channel implementing handshaking.
+ * The code of the circuits, in the examples `producer8`, `consumer8`, and `producer_consummer8` is independent of the content of the channel. For example, the sample `with_channel.rb` (please see [samples](#sample-hdlruby-descriptions)) uses the same circuits with a channel implementing handshaking.
 
+<!---
 
 ## Pipeline
 <a name="pipeline"></a>
 
 This library provides a construct for an easy description of pipeline architectures.
 
+-->
 
 # Sample HDLRuby descriptions
-<a name="sample"></a>
 
 Several samples HDLRuby descriptions are available in the following directory:
 
@@ -3079,15 +3548,22 @@ path/to/HDLRuby/lib/HDLRuby/hdr\_samples
 
 For the gem install, the path to HDLRuby can be found using the following:
 
-```
+```bash
 gem which HDLRuby
 ```
 
+But you can also import the samples to your local directory with the following command (recommended):
+
+```bash
+hdrcc --get-samples
+```
+
 The naming convention of the samples is the following:
 
 * `<name>.rb`:       default type of sample.
 * `<name>_gen.rb`:   generic parameters are required for processing the sample.
 * `<name>_bench.rb`: sample including a simulation benchmark, these are the only samples that can be simulated using `hdrcc -S`. Please notice that such a sample cannot be converted to VHDL or Verilog HDL yet.
+* `with_<name>.rb`: sample illustrating a single aspect of HDLRuby or one of its library, usually includes a benchmark.
 
 
 # Contributing
@@ -3097,10 +3573,6 @@ Bug reports and pull requests are welcome on GitHub at https://github.com/civol/
 
 # To do
 
- * Test the compatibility of the HDLRuby framework with the Microsoft Windows environments.
- * Add the generation of VHDL and Verilog code for the time behaviors.
- * Provide targets for the `Reconf` library.
- * Add a standard wave output for the simulator.
  * Find and fix the (maybe) terrifying number of bugs.
  * Add a GUI (any volunteer to do it?).