HDLRuby 2.11.12 → 3.0.0
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- checksums.yaml +4 -4
- data/README.html +3274 -0
- data/README.md +556 -84
- data/ext/hruby_sim/hruby_sim_calc.c +2 -0
- data/lib/HDLRuby/backend/hruby_allocator.rb +2 -2
- data/lib/HDLRuby/backend/hruby_c_allocator.rb +7 -7
- data/lib/HDLRuby/hdr_samples/mei8_bench.rb +1 -1
- data/lib/HDLRuby/hdr_samples/with_bram.rb +3 -3
- data/lib/HDLRuby/hdr_samples/with_bram_frame_stack.rb +105 -0
- data/lib/HDLRuby/hdr_samples/with_bram_stack.rb +69 -0
- data/lib/HDLRuby/hdr_samples/with_register_stack.rb +150 -0
- data/lib/HDLRuby/hdr_samples/with_sequencer.rb +190 -0
- data/lib/HDLRuby/hdr_samples/with_sequencer_deep.rb +91 -0
- data/lib/HDLRuby/hdr_samples/with_sequencer_enumerable.rb +405 -0
- data/lib/HDLRuby/hdr_samples/with_sequencer_enumerator.rb +89 -0
- data/lib/HDLRuby/hdr_samples/with_sequencer_sync.rb +120 -0
- data/lib/HDLRuby/hdrcc.rb +15 -2
- data/lib/HDLRuby/hdrlib.rb +1 -1
- data/lib/HDLRuby/hruby_db.rb +2 -2
- data/lib/HDLRuby/hruby_high.rb +38 -20
- data/lib/HDLRuby/hruby_high_fullname.rb +3 -1
- data/lib/HDLRuby/hruby_low.rb +2 -2
- data/lib/HDLRuby/hruby_low2c.rb +58 -43
- data/lib/HDLRuby/hruby_low2hdr.rb +66 -40
- data/lib/HDLRuby/hruby_low2high.rb +86 -44
- data/lib/HDLRuby/hruby_low2seq.rb +26 -18
- data/lib/HDLRuby/hruby_low2sym.rb +14 -13
- data/lib/HDLRuby/hruby_low2vhd.rb +78 -43
- data/lib/HDLRuby/hruby_low_bool2select.rb +61 -46
- data/lib/HDLRuby/hruby_low_casts_without_expression.rb +56 -44
- data/lib/HDLRuby/hruby_low_cleanup.rb +18 -16
- data/lib/HDLRuby/hruby_low_fix_types.rb +64 -32
- data/lib/HDLRuby/hruby_low_mutable.rb +53 -118
- data/lib/HDLRuby/hruby_low_resolve.rb +26 -31
- data/lib/HDLRuby/hruby_low_with_bool.rb +33 -16
- data/lib/HDLRuby/hruby_low_with_port.rb +3 -3
- data/lib/HDLRuby/hruby_low_with_var.rb +23 -9
- data/lib/HDLRuby/hruby_low_without_concat.rb +19 -13
- data/lib/HDLRuby/hruby_low_without_namespace.rb +47 -32
- data/lib/HDLRuby/hruby_low_without_parinseq.rb +18 -12
- data/lib/HDLRuby/hruby_low_without_select.rb +36 -23
- data/lib/HDLRuby/hruby_low_without_subsignals.rb +29 -28
- data/lib/HDLRuby/hruby_rcsim.rb +79 -64
- data/lib/HDLRuby/hruby_rsim.rb +64 -15
- data/lib/HDLRuby/hruby_rsim_mute.rb +2 -3
- data/lib/HDLRuby/hruby_rsim_vcd.rb +28 -25
- data/lib/HDLRuby/hruby_values.rb +13 -2
- data/lib/HDLRuby/hruby_verilog.rb +90 -48
- data/lib/HDLRuby/soft/stacks.rb +219 -0
- data/lib/HDLRuby/std/bram.rb +9 -5
- data/lib/HDLRuby/std/clocks.rb +1 -1
- data/lib/HDLRuby/std/fsm.rb +29 -9
- data/lib/HDLRuby/std/sequencer.rb +1857 -0
- data/lib/HDLRuby/std/sequencer_sync.rb +400 -0
- data/lib/HDLRuby/std/std.rb +12 -0
- data/lib/HDLRuby/version.rb +1 -1
- data/tuto/adder_sat_flags_vcd.png +0 -0
- data/tuto/addsub_vcd.png +0 -0
- data/tuto/alu_vcd.png +0 -0
- data/tuto/bit_pong_vcd.png +0 -0
- data/tuto/checksum_vcd.png +0 -0
- data/tuto/circuit_hdr.odg +0 -0
- data/tuto/circuit_hdr.png +0 -0
- data/tuto/circuit_hie.odg +0 -0
- data/tuto/circuit_hie.png +0 -0
- data/tuto/circuit_view.odg +0 -0
- data/tuto/circuit_view.png +0 -0
- data/tuto/clock_counter_vcd.png +0 -0
- data/tuto/counter_ext_vcd.png +0 -0
- data/tuto/fact_vcd.png +0 -0
- data/tuto/hw_flow.odg +0 -0
- data/tuto/hw_flow.png +0 -0
- data/tuto/maxxer_vcd.png +0 -0
- data/tuto/pingpong0_vcd.png +0 -0
- data/tuto/pingpong1_vcd.png +0 -0
- data/tuto/pingpong2_vcd.png +0 -0
- data/tuto/ram_vcd.png +0 -0
- data/tuto/serializer_vcd.png +0 -0
- data/tuto/sw_flow.odg +0 -0
- data/tuto/sw_flow.png +0 -0
- data/tuto/the_counter_vcd.png +0 -0
- data/tuto/tutorial_sw.html +2359 -0
- data/tuto/tutorial_sw.md +2684 -0
- data/tuto/tutorial_sw.pdf +0 -0
- data/tuto/tutorial_sw_jp.md +417 -0
- metadata +44 -2
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require 'std/sequencer'
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module HDLRuby::High::Std
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##
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# Standard HDLRuby::High library: sequencer synchronizer generator.
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# The idea is to be able to write sw-like sequential code.
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#
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########################################################################
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# Describes a signal with shared write.
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class SharedSignalI
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# Create a new shared signal of type +typ+.
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# NOTE: for now the arbitration is the priority in order of write access
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# declaration.
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def initialize(typ, name, default_value = 0)
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# Process the arguments.
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typ = typ.to_type
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@type = typ
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name = name.to_sym
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@name = name
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@default_value = default_value
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# Create the name of the access process.
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@name_sub = HDLRuby.uniq_name(:"#{name}_sub")
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this = self
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# Register the shared signal.
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HDLRuby::High.space_reg(name) { this }
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# Create the output value and selection of the signal.
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value_out = nil
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select = nil
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HDLRuby::High.cur_system.open do
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value_out = typ.inner(HDLRuby.uniq_name(:"#{name}_out"))
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select = [1].inner(HDLRuby.uniq_name(:"#{name}_select") => 0)
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end
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@value_out = value_out
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@select = select
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# First no access point.
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@size = 0
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# Create the input values.
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values_in = nil
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HDLRuby::High.cur_system.open do
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values_in = typ[-1].inner(HDLRuby.uniq_name(:"#{name}_in"))
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end
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@values_in = values_in
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# The set of access points by sequencer.
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@points = { }
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end
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# Adds an access point.
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def add_point
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# Maybe a point already exist for current sequencer.
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sequ = SequencerT.current
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point = @points[sequ]
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return @values_in[point] if point # Yes, return it.
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# No, do create a new one.
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point = @points[sequ] = @size
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# Resize the flag and value vectors.
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@size += 1
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size = @size
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@values_in.type.instance_variable_set(:@range,0..size-1)
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@select.type.instance_variable_set(:@range,(size-1).width-1..0)
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# (Re)Generate the access arbitrer.
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name_sub = @name_sub
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values_in = @values_in
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value_out = @value_out
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select = @select
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default_value = @default_value
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# The access arbitrer.
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HDLRuby::High.cur_system.open do
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sub(name_sub) do
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par do
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hcase(select)
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size.times do |i|
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hwhen(i) { value_out <= values_in[i] }
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end
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helse { value_out <= default_value }
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end
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end
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end
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# Return the current access point.
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return values_in[size-1]
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end
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# Write access code generation.
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def <=(expr)
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# Create a new access point.
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value_in = self.add_point
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# Actually implement the access.
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value_in <= expr.to_expr
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return self
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end
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# Read access code generation:
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# actually hidden in the conversion to expression.
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def to_expr
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# Return the resulting value.
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@value_out
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end
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# Selection of the output value code generation.
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# +arg+ can be the index or directly the selected sequencer.
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# If no arg is given, return access to the selection signal direction.
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def select(arg = nil)
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return @select unless arg
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if arg.is_a?(SequencerT) then
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pt = @points[arg]
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@select <= @points[arg] if pt
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else
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@select <= arg
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end
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end
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# For to_expr an all the other methods.
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def method_missing(m, *args, &ruby_block)
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self.to_expr.send(m,*args,&ruby_block)
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end
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end
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# Describes an arbiter for a shared signal.
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class ArbiterT
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# Create a new arbitrer named +name+ for shared signals +sigs+.
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def initialize(name,*sigs)
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# Sets the name.
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name = name.to_sym
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@name = name
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# Register the signals.
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@signals = []
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# Adds the signals.
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self.(*sigs)
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# Create the set of access points.
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@size = 0
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@points = {}
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# Create the acquire/release bit vector.
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acquires = nil
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HDLRuby::High.cur_system.open do
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acquires = [1].inner(HDLRuby.uniq_name(:"#{name}_acq") => 0)
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end
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@acquires = acquires
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# Register the arbiter.
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this = self
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HDLRuby::High.space_reg(name) { this }
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end
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# Adds the signals.
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def call(*sigs)
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sigs.each do |sig|
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unless sig.is_a?(SharedSignalI) then
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raise "An arbitrer only works on a shared signal, not a #{sig.class}"
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end
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@signals << sig
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end
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end
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# Adds an access point.
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def add_point
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# Maybe a point already exist for current sequencer.
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sequ = SequencerT.current
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point = @points[sequ]
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return point if point
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# No add it.
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point = @size
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@points[sequ] = point
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@size += 1
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# Resize the acquire vector according to the new point.
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@acquires.type.instance_variable_set(:@range,0..point)
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return point
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end
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# Shared signal selection code generation.
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def select(point)
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@signals.each do |signal|
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signal.select(@points.key(point))
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end
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end
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# Arbiter access code generation: 1 for acquire and 0 for release.
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def <=(val)
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# Add an access point if required.
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point = self.add_point
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# Do the access.
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@acquires[point] <= val
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end
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end
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# Describes a priority-based arbiter.
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class PriorityArbiterT < ArbiterT
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# Create a new priority-based arbiter named +name+ with priority table
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# +tbl+ or priority algorithm +ruby_block+ for shared signals +sigs+.
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def initialize(name, tbl = nil, *sigs, &ruby_block)
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super(name,*sigs)
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# Set the priority policy.
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self.policy(tbl,&ruby_block)
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# Create the name of the access procedure sub.
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@name_sub = HDLRuby.uniq_name(:"#{name}_sub")
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end
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# Set the policy either using a priority table +tbl+ by directly
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# providing the priority algorithm through +ruby_block+
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def policy(tbl = nil, &ruby_block)
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# By default the priority table is the points declaration order.
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if !tbl && ruby_block == nil then
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@priority = proc { |acquires,i| acquires[i] == 1 }
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elsif tbl then
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@priority = proc do |acquires,i|
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pri = tbl[i]
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raise "Invalid priority index: #{i}" unless pri
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acquires[pri] == 1
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end
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else
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@priority = ruby_block
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end
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end
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# Add a point.
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def add_point
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point = super # The point is added by the parent class.
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# Update the access procedure.
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name_sub = @name_sub
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this = self
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size = @size
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acquires = @acquires
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priority = @priority
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HDLRuby::High.cur_system.open do
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sub(name_sub) do
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seq do
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if(size == 1) then
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# Anyway, only one accesser.
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this.select(0)
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else
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hif(priority.(acquires,0)) do
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this.select(0)
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end
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(1..size-1).each do |i|
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helsif(priority.(acquires,i)) do
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this.select(i)
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end
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end
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helse do # No acquire at all, select the first point.
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this.select(0)
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end
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end
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end
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end
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end
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return point
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end
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end
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# Describes priority-based monitor.
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class PriorityMonitorT < PriorityArbiterT
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# Create a new priority-based arbiter named +name+ with priority table
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# +tbl+ or priority algorithm +ruby_block+ for shared signals +sigs+.
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def initialize(name, tbl = nil, *sigs, &ruby_block)
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super(name,tbl,*sigs,&ruby_block)
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# Declare the current selected point.
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selected_point = nil
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name = @name
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HDLRuby::High.cur_system.open do
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selected_point = [1].inner(HDLRuby.uniq_name(:"#{name}_selected"))
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end
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@selected_point = selected_point
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end
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# Add a point.
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def add_point
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# Redefine to update the size of @selected_point.
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point = super
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@selected_point.type.instance_variable_set(:@range,(@size-1).width-1..0)
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return point
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end
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# Shared signal selection code generation.
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def select(point)
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# Redefine to remember which point is selected.
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super(point)
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@selected_point <= point
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end
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# # Arbiter access code generation: 1 for acquire and 0 for release.
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# def <=(val)
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# # Fully redefine to lock until selected if acquiring.
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# # Add an access point if required.
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# point = self.add_point
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# # Do the access.
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# res = (@acquires[point] <= val)
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# selected_point = @selected_point
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# # Lock until not selected.
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# if val.respond_to?(:to_i) then
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# if val.to_i == 1 then
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# SequencerT.current.swhile(selected_point != point)
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# end
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# else
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# SequencerT.current.swhile((val.to_expr == 1) & (selected_point != point))
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# end
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+
# return res
|
306
|
+
# end
|
307
|
+
|
308
|
+
# Arbiter access code generation: 1 for acquire and 0 for release.
|
309
|
+
def <=(val)
|
310
|
+
raise "For monitors, you must use the methods lock and unlock."
|
311
|
+
end
|
312
|
+
|
313
|
+
# Monitor lock code generation
|
314
|
+
def lock
|
315
|
+
# Fully redefine to lock until selected if acquiring.
|
316
|
+
# Add an access point if required.
|
317
|
+
point = self.add_point
|
318
|
+
# Do the access.
|
319
|
+
res = (@acquires[point] <= 1)
|
320
|
+
selected_point = @selected_point
|
321
|
+
# Lock until not selected.
|
322
|
+
SequencerT.current.swhile(selected_point != point)
|
323
|
+
return res
|
324
|
+
end
|
325
|
+
|
326
|
+
# Monitor unlock code generation
|
327
|
+
def unlock
|
328
|
+
# Fully redefine to lock until selected if acquiring.
|
329
|
+
# Add an access point if required.
|
330
|
+
point = self.add_point
|
331
|
+
# Do the access.
|
332
|
+
res = (@acquires[point] <= 0)
|
333
|
+
selected_point = @selected_point
|
334
|
+
return res
|
335
|
+
end
|
336
|
+
end
|
337
|
+
|
338
|
+
|
339
|
+
# Declares an arbiter named +name+ with priority table +tbl+ or priority
|
340
|
+
# procedure +rubyblock+.
|
341
|
+
def arbiter(name,tbl = nil, &ruby_block)
|
342
|
+
return PriorityArbiterT.new(name,tbl,&ruby_block)
|
343
|
+
end
|
344
|
+
|
345
|
+
# Declares a monitor named +name+ with priority table +tbl+ or priority
|
346
|
+
# procedure +rubyblock+.
|
347
|
+
def monitor(name,tbl = nil, &ruby_block)
|
348
|
+
return PriorityMonitorT.new(name,tbl,&ruby_block)
|
349
|
+
end
|
350
|
+
|
351
|
+
|
352
|
+
|
353
|
+
|
354
|
+
# Enhance the Htype module for creating a shared signal.
|
355
|
+
module HDLRuby::High::Htype
|
356
|
+
|
357
|
+
# Create new shared signals from +args+.
|
358
|
+
# +args+ can be a name of list of names or a hash associating names to
|
359
|
+
# default values.
|
360
|
+
def shared(*args)
|
361
|
+
# # Process the arguments.
|
362
|
+
# Create the shared signal.
|
363
|
+
sig = nil
|
364
|
+
args.each do |arg|
|
365
|
+
if arg.is_a?(Hash) then
|
366
|
+
arg.each do |k,v|
|
367
|
+
sig = SharedSignalI.new(self,k,v)
|
368
|
+
end
|
369
|
+
else
|
370
|
+
sig = SharedSignalI.new(self,arg)
|
371
|
+
end
|
372
|
+
end
|
373
|
+
return sig
|
374
|
+
end
|
375
|
+
end
|
376
|
+
|
377
|
+
|
378
|
+
class ::Array
|
379
|
+
# Enhance the Array type for creating shared signals.
|
380
|
+
|
381
|
+
# Create new shared signals from +args+.
|
382
|
+
def shared(*names)
|
383
|
+
return self.to_type.shared(*names)
|
384
|
+
end
|
385
|
+
end
|
386
|
+
|
387
|
+
|
388
|
+
class ::Hash
|
389
|
+
# Enhance the Struct type for creating shared signals.
|
390
|
+
|
391
|
+
# Create new shared signals from +args+.
|
392
|
+
def shared(*names)
|
393
|
+
return self.to_type.shared(*names)
|
394
|
+
end
|
395
|
+
end
|
396
|
+
|
397
|
+
|
398
|
+
|
399
|
+
|
400
|
+
end
|
@@ -0,0 +1,12 @@
|
|
1
|
+
|
2
|
+
##
|
3
|
+
# Standard HDLRuby::High library: all the stable functionalities.
|
4
|
+
#
|
5
|
+
########################################################################
|
6
|
+
|
7
|
+
require 'std/clocks.rb'
|
8
|
+
require 'std/fixpoint.rb'
|
9
|
+
require 'std/decoder.rb'
|
10
|
+
require 'std/fsm.rb'
|
11
|
+
require 'std/sequencer.rb'
|
12
|
+
require 'std/sequencer_sync.rb'
|
data/lib/HDLRuby/version.rb
CHANGED
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|
data/tuto/addsub_vcd.png
ADDED
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|
data/tuto/alu_vcd.png
ADDED
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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ADDED
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|
data/tuto/hw_flow.odg
ADDED
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|
data/tuto/hw_flow.png
ADDED
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|
data/tuto/maxxer_vcd.png
ADDED
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|
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|
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|
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|
data/tuto/ram_vcd.png
ADDED
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|
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|
data/tuto/sw_flow.odg
ADDED
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|
data/tuto/sw_flow.png
ADDED
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|
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|