HDLRuby 2.11.12 → 3.0.0

data/lib/HDLRuby/hruby_rsim_vcd.rb

@@ -40,9 +40,9 @@ module HDLRuby::High
         return idstr
     end
 
-    ##
-    # Enhance the system type class with VCD support.
+
     class SystemT
+        # Enhance the system type class with VCD support.
 
         ## Initializes the displayer for generating a vcd on +vcdout+
         def show_init(vcdout)
@@ -161,9 +161,9 @@ module HDLRuby::High
     end
 
 
-    ##
-    # Enhance the scope class with VCD support.
     class Scope
+        # Enhance the scope class with VCD support.
+
         ## Shows the hierarchy of the variables.
         def show_hierarchy(vcdout)
             # puts "show_hierarchy for scope=#{self}"
@@ -252,9 +252,10 @@ module HDLRuby::High
         end
     end
 
-    ##
-    # Enhance the signals class with VCD support.
+
     module SimSignal
+        # Enhance the signals class with VCD support.
+
         ## Shows the hierarchy of the variables.
         def show_hierarchy(vcdout)
             # puts "show_hierarcy for signal=#{self.name}"
@@ -300,9 +301,10 @@ module HDLRuby::High
         end
     end
 
-    ##
-    # Enhance the Transmit class with VCD support.
+
     class Transmit
+        # Enhance the Transmit class with VCD support.
+
         ## Shows the hierarchy of the variables.
         def show_hierarchy(vcdout)
             # By default: nothing to do.
@@ -319,9 +321,10 @@ module HDLRuby::High
         end
     end
 
-    ##
-    # Enhance the TimeRepeat class with VCD support.
+
     class TimeRepeat
+        # Enhance the TimeRepeat class with VCD support.
+        
         ## Shows the hierarchy of the variables.
         def show_hierarchy(vcdout)
             # Recurse on the statement.
@@ -339,9 +342,10 @@ module HDLRuby::High
         end
     end
 
-    ##
-    # Enhance the TimeWait class with VCD support.
+
     class TimeWait
+        # Enhance the TimeWait class with VCD support.
+
         ## Shows the hierarchy of the variables.
         def show_hierarchy(vcdout)
             # By default: nothing to do.
@@ -358,9 +362,10 @@ module HDLRuby::High
         end
     end
 
-    ##
-    # Enhance the Print class with VCD support.
+
     class Print
+        # Enhance the Print class with VCD support.
+
         ## Shows the hierarchy of the variables.
         def show_hierarchy(vcdout)
             # By default: nothing to do.
@@ -378,7 +383,7 @@ module HDLRuby::High
     end
 
 
-    ## Module adding show_hierarchyto block objects.
+    ## Module adding show_hierarchy to block objects.
     module BlockHierarchy
         ## Shows the hierarchy of the variables.
         def show_hierarchy(vcdout)
@@ -445,23 +450,20 @@ module HDLRuby::High
     end
 
 
-    ##
-    # Enhance the block class with VCD support.
     class Block
+        # Enhance the block class with VCD support.
         include HDLRuby::High::BlockHierarchy
     end
 
 
-    ##
-    # Enhance the block class with VCD support.
     class TimeBlock
+        # Enhance the block class with VCD support.
         include HDLRuby::High::BlockHierarchy
     end
 
 
-    ##
-    # Enhance the if class with VCD support.
     class If
+        # Enhance the if class with VCD support.
         ## Shows the hierarchy of the variables.
         def show_hierarchy(vcdout)
             # Recurse on the yes.
@@ -502,9 +504,9 @@ module HDLRuby::High
     end
 
 
-    ##
-    # Enhance the Case class with VCD support.
     class Case
+        # Enhance the Case class with VCD support.
+        
         ## Shows the hierarchy of the variables.
         def show_hierarchy(vcdout)
             # Recurse on each when.
@@ -538,9 +540,10 @@ module HDLRuby::High
         end
     end
 
-    ##
-    # Enhance the TimeRepeat class with VCD support.
+
     class TimeRepeat
+        # Enhance the TimeRepeat class with VCD support.
+        
         ## Shows the hierarchy of the variables.
         def show_hierarchy(vcdout)
             # Recurse on the statement.

data/lib/HDLRuby/hruby_values.rb

@@ -56,7 +56,7 @@ module HDLRuby
                 else
                     # Generate the resulting content.
                     res_content = self.content.send(op,val.content)
-                    # puts "op=#{op} self.content=#{self.content} (#{self.content.to_i}) val.content=#{val.content} (#{val.content.to_i}) res_content=#{res_content} (#{res_content.class})" if op == :^
+                    # puts "op=#{op} self.content=#{self.content} (#{self.content.to_i}) val.content=#{val.content} (#{val.content.to_i}) res_content=#{res_content} (#{res_content.class})"
                 end
                 res_type = self.type.resolve(val.type)
                 # # Adjust the result content size.
@@ -148,9 +148,11 @@ module HDLRuby
                 if self.content.is_a?(BitString) then
                     res_content = self.content[index*width..(index+1)*width-1]
                 else
+                    # puts "self.content=#{self.content} index=#{index}"
                     sh = index*width
                     mask = (-1 << sh) & ~(-1 << (index+1)*width)
                     res_content = (self.content & mask) >> sh
+                    # puts "res_content=#{res_content}"
                 end
                 # Return the resulting value.
                 return self.class.new(res_type,res_content)
@@ -240,7 +242,7 @@ module HDLRuby
                 # Generate the resulting type.
                 res_type = self.type
                 # Generate the resulting content.
-                # puts "op=#{op} content=#{content.to_s}"
+                # puts "op=#{op} content=#{content.to_s} width=#{res_type.width}"
                 res_content = self.content.send(op)
                 # puts "res_content=#{res_content}"
                 # Return the resulting value.
@@ -279,6 +281,9 @@ module HDLRuby
                     res_content.positive!
                 end
             end
+            if type.signed && res_content.is_a?(Numeric) && res_content >= (1 << (type.width-1)) then
+                res_content = (-1 << type.width) + res_content
+            end
             # # truncs to the right size if necessary.
             # if res_content.is_a?(BitString) then
             #     res_content.trunc!(type.width)
@@ -405,6 +410,12 @@ module HDLRuby
             end
         end
 
+        # Tell if the value is high impedance.
+        def impedence?
+            return false unless @content.is_a?(BitString)
+            return @content.raw_content.include?(2)
+        end
+
         ## Converts the value to a string of the right size.
         def to_vstr
             if self.content.is_a?(Numeric) then

data/lib/HDLRuby/hruby_verilog.rb

@@ -4,10 +4,8 @@ require "HDLRuby/hruby_verilog_name.rb"
 require 'HDLRuby/hruby_low_mutable'
 
 
-# module HDLRuby::Verilog
 include HDLRuby::Verilog
 
-#include HDLRuby::Low
 module HDLRuby::Low
 
 
@@ -38,12 +36,16 @@ module HDLRuby::Low
     $vector_reg = ""   # For storing signal type at structure declaration. (temporary)
     $vector_cnt = 0    # For allocating numbers at structure declaration.  (temporary)
 
+    
     class ::Integer
+        ## Extends the Integer class with generation of verilog text.
+
         def to_verilog
             to_s
         end
     end
 
+    
     # Class summarizing "hash" used for "par" or "seq" conversion.
     class Fm
         attr_reader :fm_seq, :fm_par, :rep, :rep_sharp
@@ -115,8 +117,9 @@ module HDLRuby::Low
     TruncersI = Truncers.new
 
 
-    # A class that translates the left-hand side, operator, and right-hand side into form of expression.
     class Binary
+        ## Enhances Binary with verilog generation.
+
         # Converts the system to Verilog code.
         def to_verilog
             return "(#{self.left.to_verilog} #{self.operator} #{self.right.to_verilog})"
@@ -158,9 +161,10 @@ module HDLRuby::Low
         end
     end
 
-    # class of Represent blocking substitution or nonblocking assignment.
-    # Enhance Transmit with generation of verilog code.
+
     class Transmit
+        ## Enhances Transmit with generation of verilog code.
+
         # Converts the system to Verilog code.
         def to_verilog(spc = 3)
             # Determine blocking assignment or nonblocking substitution from mode and return it.
@@ -169,8 +173,10 @@ module HDLRuby::Low
         end
     end
 
-    # Enhance Print with generation of verilog code.
+
     class Print
+        ## Enhances Print with generation of verilog code.
+
         # Converts the print to Verilog code.
         def to_verilog(spc = 3)
             code = "#{" " * spc}$write(#{self.each_arg.map do |arg|
@@ -180,17 +186,20 @@ module HDLRuby::Low
         end
     end
 
-    # Enhance TimeTerminate with generation of verilog code.
+
     class TimeTerminate
+        ## Enhances TimeTerminate with generation of verilog code.
+
         # Converts the terminate to Verilog code.
         def to_verilog(spc = 3)
             return "#{" " * spc}$finish;"
         end
     end
 
-    # To scheduling to the Block.
-    # Enhance Block with generation of verilog code.
+
     class Block
+        ## Enhances Block with generation of verilog code.
+        # To scheduling to the Block.
 
         # Converts the system to Verilog code adding 'spc' spaces at the begining
         # of each line.
@@ -1439,9 +1448,10 @@ module HDLRuby::Low
         end
     end
 
-    # Used to display variable names.
-    # Enhance RefName with generation of verilog code.
+
     class RefName
+        ## Enhances RefName with generation of verilog code.
+
         # Converts the system to Verilog code using +renamer+ for producing Verilog-compatible names.
         def to_verilog
             vname = name_to_verilog(self.name)
@@ -1463,9 +1473,10 @@ module HDLRuby::Low
         end
     end
 
-    # Used to convert an array.
-    # Enhance RefIndex with generation of verilog code.
+    
     class RefIndex
+        ## Enhances RefIndex with generation of verilog code.
+
         # Converts the system to Verilog code.
         def to_verilog
             return "#{self.ref.to_verilog}[#{self.index.to_verilog}]"
@@ -1473,9 +1484,9 @@ module HDLRuby::Low
     end
 
 
-    # Used to indicate the number of bits.
-    # Enhance TypeVector with generation of verilog code.
     class TypeVector
+        ## Enhances TypeVector with generation of verilog code.
+
         # Converts the system to Verilog code.
         def to_verilog
             # if self.base.name.to_s != "bit"
@@ -1486,16 +1497,22 @@ module HDLRuby::Low
         end
     end
 
-    # Necessary for displaying bit width (eg, specify and assign).
+
     class RefRange
+        ## Enhances RefRange with generation of verilog code.
+
+        # Necessary for displaying bit width (eg, specify and assign).
+
         # Converts the system to Verilog code.
         def to_verilog(unknown = false)
             return "#{self.ref.to_verilog}[#{self.range.first.to_getrange}:#{self.range.last.to_getrange}]"
         end
     end
 
-    # Use it when collecting references.
+
     class RefConcat
+        ## Enhances RefConcat with generation of verilog code.
+
         def to_verilog    
             ref = self.each_ref.to_a
 
@@ -1509,18 +1526,20 @@ module HDLRuby::Low
         end
     end
 
-    # Used to output bitstring.
-    # Enhance HDLRuby with generation of verilog code.
+
     class HDLRuby::BitString
+        ## Enhances BitString with generation of verilog code.
+
         # Converts the system to Verilog code.
         def to_verilog
             return "#{self.to_s}"
         end
     end
 
-    # Used for connection using choice.
-    # Enhance Select with generation of verilog code.
+
     class Select
+        ## Enhances Select with generation of verilog code.
+
         # Converts the system to Verilog code.
         def to_verilog
             # Outputs the first and second choices (choice (0) and choice (1)).
@@ -1535,9 +1554,10 @@ module HDLRuby::Low
         end
     end
 
-    # Used to output numbers.
-    # Enhance Value with generation of verilog code.
+
     class Value
+        ## Enhances Value with generation of verilog code.
+
         # Converts the system to Verilog code.
         # If it is bit, it is b, and if it is int, it is represented by d. (Example: 4'b0000, 32'd1)
         def to_verilog(unknown = nil)
@@ -1579,9 +1599,9 @@ module HDLRuby::Low
     end
 
 
-    # Used to transrate if.
-    # Enhance If with generation of verilog code.
     class If
+        ## Enhances If with generation of verilog code.
+
         # # Converts the system to Verilog code.
         # def to_verilog(mode = nil)
         # Converts to Verilog code, checking adding 'spc' spaces at the begining
@@ -1617,10 +1637,10 @@ module HDLRuby::Low
         end
     end
 
-    # Used to translate case
+
     class Case
-        # def to_verilog(mode = nil)
-        #
+        ## Enhances Case with generation of verilog code.
+
         # Converts to Verilog code, checking if variables are register
         # or wire adding 'spc' spaces at the begining of each line.
         def to_verilog(spc = 3)
@@ -1656,9 +1676,10 @@ module HDLRuby::Low
         end
     end
 
-    # Translate expression of combination circuit.
-    # Enhance Connection with generation of verilog code.
+    
     class Connection
+        ## Enhances Connection with generation of verilog code.
+
         # Converts the system to Verilog code.
 
         # Method used for array.
@@ -1715,23 +1736,29 @@ module HDLRuby::Low
         end
     end
 
-    # It could be used for instantiation.
+    
     class RefThis
+        ## Enhances RefThis with generation of verilog code.
+
         def to_another_verilog
             return ""
         end
     end
 
-    # Used when using "~" for expressions.
+    
     class Unary
+        ## Enhances Unary with generation of verilog code.
+
         # Converts the system to Verilog code.
         def to_verilog
             return "#{self.operator[0]}#{self.child.to_verilog}"
         end
     end
 
-    # Used when casting expressions.
+    
     class Cast
+        ## Enhances Cast with generation of verilog code.
+
         # Converts the system to Verilog code.
         # NOTE: the cast is rounded up size bit-width cast is not supported
         #       by traditional verilog.
@@ -1773,9 +1800,10 @@ module HDLRuby::Low
         end
     end
 
-    # For declaring variables.
-    # Enhance SignalI with generation of verilog code.
+
     class SignalI
+        ## Enhances SignalI with generation of verilog code.
+
         # Converts the system to Verilog code.
         def to_verilog
             # Convert unusable characters and return them.
@@ -1785,25 +1813,30 @@ module HDLRuby::Low
         end
     end
 
-    # If it is signed, it outputs signed.
-    # Enhance Type with generation of verilog code.
+    
     class Type
+        ## Enhances Type with generation of verilog code.
+
         # Converts the type to Verilog code.
         def to_verilog
             return self.name == :signed ? "#{self.name.to_s} " : ""
         end
     end
 
-    # Replace type by refered type.
+    
     class TypeDef
+        ## Enhances TypeDef with generation of verilog code.
+
         # Converts the type to verilog code.
         def to_verilog
             return self.def.to_verilog
         end
     end
 
-    # Use it when collecting.
+    
     class Concat
+        ## Enhances Concat with generation of verilog code.
+
         def to_verilog    
             expression = self.each_expression.to_a
 
@@ -1817,14 +1850,19 @@ module HDLRuby::Low
         end
     end
 
-    # Look at the unit of time, convert the time to ps and output it.
-    # One of two people, TimeWait and Delay.
+    
     class TimeWait
+        ## Enhances TimeWait with generation of verilog code.
+
         def to_verilog(spc = 3)
             return (" " * spc) + self.delay.to_verilog + "\n"
         end
     end
+
+
     class Delay
+        ## Enhances Delay with generation of verilog code.
+
         def to_verilog
             time = self.value.to_s
             if(self.unit.to_s == "ps") then
@@ -1842,8 +1880,9 @@ module HDLRuby::Low
     end
 
 
-    # Generate verilog code for the TimeRepeat.
     class TimeRepeat
+        ## Enhances TimeRepeat with generation of verilog code.
+
         def to_verilog(spc = 3)
             result = (" " * spc) + "repeat(#{self.number})" + "\n"
             result << self.statement.to_verilog(spc+3)
@@ -1855,8 +1894,9 @@ module HDLRuby::Low
     #class TypeTuple
     #class Event
 
-    # Enhance SystemT with generation of verilog code.
+    
     class SystemT
+        ## Enhances SystemT with generation of verilog code.
 
         ## Tells if a connection is actually a port connection.
         def port_output_connection?(connection)
@@ -2163,9 +2203,10 @@ module HDLRuby::Low
                         codeC << "),"
                     end
                 end
-                # Remove the last "," for conforming with Verilog syntax.
-                # and close the port connection.
-                codeC[-1] = ");\n"
+                # Remove the last "," if any for conforming with Verilog syntax.
+                codeC.chop! if codeC[-1] == ","
+                # And close the port connection.
+                codeC << ");\n"
             end
 
 
@@ -2254,8 +2295,9 @@ module HDLRuby::Low
     end
 
 
-    # Enhance StringE with generation of verilog code.
     class StringE
+        ## Enhances stringE with generation of verilog code.
+
         # Converts the system to Verilog code.
         def to_verilog(spc = 3)
             code = "\"#{Low.v_string(self.content)}" +
@@ -2270,8 +2312,8 @@ end
 
 
 
-## Extends the Numeric class with generation of verilog text.
 class ::Numeric
+## Extends the Numeric class with generation of verilog text.
 
     # Generates the text of the equivalent verilog code.
     # +level+ is the hierachical level of the object.