HDLRuby 2.11.12 → 3.0.0

data/lib/HDLRuby/soft/stacks.rb

@@ -0,0 +1,219 @@
+require 'std/bram'
+
+module HDLRuby::High::Soft
+
+
+    # Declare the possible commands for the stack.
+    PUSH  = 0   # Pushes the value of input din into the stack.
+    POP   = 1   # Pops din values for the stack. If din is negative, allocates din elements on the stack.
+    READ  = 2   # Read the value address din and output it on dout.
+    WRITE = 3   # Write the value at the top of the stack at address din.
+
+
+
+
+
+    # Describe a stack based on a BRAM (compatible with FPGA's)
+    # - 'widthD': data bit width
+    # - 'size'  : the size of the stack
+    system :bram_stack do |widthD, size|
+        # Compute the address width.
+        widthA = (size-1).width
+
+        # Compute the bit width of the stack pointer register.
+        widthS = (size+1).width
+
+        # Declare the inputs and outputs.
+        input :clk, :rst, :ce
+        input :cmd
+        [widthD].input  :din
+        [widthD].output :dout
+        output  :empty, :full
+
+        # Declare the BRAM containing the stack data.
+        inner rwb: 1
+        [widthA].inner :addr
+        [widthD].inner :brin, :brout
+        bram(widthA,widthD).(:bramI).(clk,rwb,addr,brin,brout)
+
+        # Declare the stack pointer register and the top of stack value.
+        [widthS].inner sp: size
+        [widthD].inner :top
+
+        # Tells if the stack is empty or full.
+        empty <= (sp == size)
+        full  <= (sp == 0)
+
+        # The output bus is the top of the stack.
+        dout <= top
+
+        # The clock process handling the access.
+        seq(clk.posedge) do
+            # By default, read before the top of the memory.
+            rwb <= 1
+            hif(rst) do
+                # sp is set to size (stack empty).
+                sp <= size
+                top <= 0
+            end
+            helsif(ce) do
+                # Now depending on the command.
+                hcase(cmd)
+                hwhen(PUSH) do
+                    # Is the stack full?
+                    hif(~full) do
+                        # No, can push onto the stack.
+                        # Update the top register.
+                        top <= din
+                        # Update the bram.
+                        brin <= din
+                        rwb  <= 0
+                        # Finally, decrease sp.
+                        sp <= sp - 1
+                        # The address is the top of the stack
+                        addr <= sp
+                    end
+                end
+                hwhen(POP) do
+                    # Is the stack empty?
+                    hif(~empty) do
+                        # No, can pop from the stack.
+                        # Update the top register.
+                        top <= brout
+                        # Finally, increase sp.
+                        sp <= sp + 1
+                    end
+                end
+            end
+            hif(~ce | cmd != PUSH) do
+                # By default the address is the top of the stack + 1
+                addr <= sp + 1
+            end
+        end
+        
+    end
+
+
+    # Describe a frame stack based on a BRAM (compatible with FPGA's)
+    # - 'widthD': data bit width
+    # - 'size'  : the size of the stack
+    # - 'depth' : the maximum number of frames.
+    system :bram_frame_stack do |widthD, size, depth|
+        # Compute the address width.
+        widthA = (size-1).width
+
+        # Compute the bit width of the frame pointers.
+        widthF = (size+1).width
+
+        # compute the bit width of the frame stack pointer.
+        widthS = (depth+1).width
+
+        # Create the type used for accessing the frame stack.
+        typedef(:locT) { { frame: bit[widthS], offset: bit[widthF] } }
+
+        # Declare the inputs and outputs.
+        input :clk, :rst, :ce
+        [2].input :cmd
+        locT.input :loc
+        [widthD].input  :din
+        [widthD].output :dout
+        output  :empty, :full
+
+        # Declare the frame index stac pointer.
+        [widthS].inner :sp
+
+        # Declare the frame index table.
+        bit[widthF][-depth].inner :indexes
+
+        # Declare the BRAM containing the frames data.
+        inner rwb: 1
+        [widthA].inner :addr
+        [widthD].inner :brin, :brout
+        bram(widthA,widthD).(:bramI).(clk,rwb,addr,brin,brout)
+
+        # Tells if the stack is empty or full.
+        empty <= (sp == depth)
+        full  <= (sp == 0)
+
+        # The input data is always the input of the bram.
+        brin <= din
+
+        # The output is always the output of the bram.
+        dout <= brout
+
+        # The clock process handling the access.
+        seq(clk.posedge) do
+            # By default, read before the top of the memory.
+            rwb <= 1
+            hif(rst) do
+                # sp is set to depth (stack empty).
+                sp <= depth
+            end
+            helsif(ce) do
+                # Now depending on the command.
+                hcase(cmd)
+                hwhen(PUSH) do
+                    # Is the stack full or is the frame to push empty? 
+                    hif(~(full | loc.offset == 0)) do
+                        # No, we can proceed.
+                        # Decrease sp.
+                        sp <= sp - 1
+                        # Adds the frame.
+                        hif(~empty) do
+                            indexes[sp] <= loc.offset + indexes[sp+1]
+                        end
+                        helse do
+                            indexes[sp] <= loc.offset
+                        end
+                    end
+                end
+                hwhen(POP) do
+                    # Is the stack empty?
+                    hif(~empty) do
+                        # No, can pop a frame from the stack.
+                        # Increase sp.
+                        sp <= sp + 1
+                    end
+                end
+                hwhen(READ) do
+                    # Read access, is the frame valid?
+                    cur_frame = sp+loc.frame
+                    hif (~(empty | cur_frame >= depth)) do
+                        # The frame is valid. Is the offset valid?
+                        addr_calc = indexes[cur_frame] - loc.offset - 1
+                        hif ((cur_frame < depth-1) & 
+                             (addr_calc > indexes[cur_frame+1])) do
+                            # Not the first frame and the address is valid.
+                            addr <= addr_calc
+                        end
+                        helsif ((cur_frame == depth-1) &
+                            (addr_calc + 1 > 0)) do
+                            # The first frame and the address is valid.
+                            addr <= addr_calc
+                        end
+                    end
+                end
+                hwhen(WRITE) do
+                    # Write access, is the frame valid?
+                    cur_frame = sp+loc.frame
+                    hif (~(empty | cur_frame >= depth)) do
+                        # The frame is valid. Is the offset valid?
+                        addr_calc = indexes[cur_frame] - loc.offset - 1
+                        hif ((cur_frame < depth-1) & 
+                             (addr_calc > indexes[cur_frame+1])) do
+                            # Not the first frame and the address is valid.
+                            addr <= addr_calc
+                            rwb  <= 0
+                        end
+                        helsif ((cur_frame == depth-1) &
+                            (addr_calc + 1 > 0)) do
+                            # The first frame and the address is valid.
+                            addr <= addr_calc
+                            rwb  <= 0
+                        end
+                    end
+                end
+            end
+        end
+    end
+end

data/lib/HDLRuby/std/bram.rb

@@ -3,18 +3,22 @@ module HDLRuby::High::Std
     # Describe a RAM compatibile with BRAM of FPGAs.
     # - 'widthA': address bit width
     # - 'widthD': data bit width
-    system :bram do |widthA, widthD|
+    # - 'size':   the size of the memory.
+    system :bram do |widthA, widthD, size = nil|
+        # Process size if required.
+        size = 2**widthA unless size
+        # puts "widthA=#{widthA} widthD=#{widthD} size=#{size}"
+
+        # Declares the io of the ram.
         input :clk, :rwb
         [widthA].input :addr
         [widthD].input :din
         [widthD].output :dout
 
-        # puts "widthA=#{widthA} widthD=#{widthD}"
-
-        bit[widthD][-2**widthA].inner mem: [ :"_b#{"0"*widthD}".to_value ] * 2**widthA
+        bit[widthD][-size].inner mem: [ :"_b#{"0"*widthD}".to_value ] * size
 
         par(clk.negedge) do
-            hif(rwb == 1) { mem[addr] <= din }
+            hif(rwb == 0) { mem[addr] <= din }
             dout <= mem[addr]
         end
     end

data/lib/HDLRuby/std/clocks.rb

@@ -135,8 +135,8 @@ module HDLRuby::High::Std
 end
 
 
-# Enhnace the events with multiply operator.
 class HDLRuby::High::Event
+    # Enhance the events with multiply operator.
 
     # Creates a new event activated every +times+ occurences of the 
     # current event.

data/lib/HDLRuby/std/fsm.rb

@@ -31,8 +31,10 @@ module HDLRuby::High::Std
 
         # Creates a new fsm type with +name+.
         # +options+ allows to specify the type of fsm:
-        # synchronous (default) / asynchronous and
-        # mono-front(default) / dual front
+        # - :sync, :synchronous : synchronous (default)
+        # - :async, :asynchronous : asynchronous
+        # - :dual : dual front
+        # - :seq, :blocking : use blocking assignments
         def initialize(name,*options)
             # Check and set the name
             @name = name.to_sym
@@ -40,6 +42,7 @@ module HDLRuby::High::Std
             @dual = false
             @type = :sync      # By default, the FSM is synchronous.
             @sequential = true # By default, the default next state is the next one in the list.
+            @blocking = false  # By default, use non-blocking assignments (par)
             options.each do |opt|
                 case opt
                 when :sync,:synchronous then
@@ -50,10 +53,23 @@ module HDLRuby::High::Std
                     @dual = true
                 when :static then
                     @sequential = false
+                when :seq then
+                    @blocking = true
+                when :blocking then
+                    @blocking = true
                 else
                     raise AnyError, "Invalid option for a fsm: :#{type}"
                 end
             end
+            if @blocking then
+                define_singleton_method(:fsm_block) do |*args,&ruby_block|
+                    send(:seq,*args,&ruby_block)
+                end
+            else
+                define_singleton_method(:fsm_block) do |*args,&ruby_block|
+                    send(:par,*args,&ruby_block)
+                end
+            end
 
             # Initialize the internals of the FSM.
 
@@ -127,7 +143,8 @@ module HDLRuby::High::Std
                 # sub do
                     HDLRuby::High.space_push(namespace)
                     # Execute the instantiation block
-                    return_value = HDLRuby::High.top_user.instance_exec(&ruby_block)
+                    # return_value = HDLRuby::High.top_user.instance_exec(&ruby_block)
+                    return_value = HDLRuby::High.top_user.instance_exec(&ruby_block) if ruby_block
 
                     # Expands the extra state processing so that al all the
                     # parts of the state machine are in par (clear synthesis).
@@ -171,7 +188,8 @@ module HDLRuby::High::Std
                     # Create the fsm code
 
                     # Control part: update of the state.
-                    par(mk_ev.call) do
+                    # par(mk_ev.call) do
+                    fsm_block(mk_ev.call) do
                         hif(mk_rst.call) do
                             # Reset: current state is to put to 0.
                             this.cur_state_sig <= 0
@@ -194,7 +212,8 @@ module HDLRuby::High::Std
                         event = []
                     end
                     # The process
-                    par(*event) do
+                    # par(*event) do
+                    fsm_block(*event) do
                         # The operative code.
                         oper_code =  proc do
                             # The default code.
@@ -241,8 +260,6 @@ module HDLRuby::High::Std
                                 st.gotos.each(&:call)
                             else
                                 # No gotos, by default the next step is
-                                # current + 1
-                                # this.next_state_sig <=  this.cur_state_sig + 1
                                 if sequential then
                                     this.next_state_sig <= this.cur_state_sig + 1
                                 end
@@ -251,6 +268,7 @@ module HDLRuby::High::Std
                     end
                     # By default set the next state to 0.
                     helse do
+                        # hprint("Unknow state case: ",this.cur_state_sig,"\n")
                         this.next_state_sig <= 0
                     end
 
@@ -260,7 +278,8 @@ module HDLRuby::High::Std
                         event = mk_ev.call
                         event = event.invert if @dual
                         # The extra code.
-                        par(*event) do
+                        # par(*event) do
+                        fsm_block(*event) do
                             # Build the extra synchronous part.
                             sync_code = proc do
                                 hcase(this.cur_state_sig)
@@ -289,7 +308,8 @@ module HDLRuby::High::Std
 
                     # Extra asynchronous operative part.
                     if extra_asyncs.any? then
-                        par do
+                        # par do
+                        fsm_block do
                             # Build the extra synchronous part.
                             async_code = proc do
                                 hcase(this.cur_state_sig)