HDLRuby 2.11.12 → 3.0.0
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- checksums.yaml +4 -4
- data/README.html +3274 -0
- data/README.md +556 -84
- data/ext/hruby_sim/hruby_sim_calc.c +2 -0
- data/lib/HDLRuby/backend/hruby_allocator.rb +2 -2
- data/lib/HDLRuby/backend/hruby_c_allocator.rb +7 -7
- data/lib/HDLRuby/hdr_samples/mei8_bench.rb +1 -1
- data/lib/HDLRuby/hdr_samples/with_bram.rb +3 -3
- data/lib/HDLRuby/hdr_samples/with_bram_frame_stack.rb +105 -0
- data/lib/HDLRuby/hdr_samples/with_bram_stack.rb +69 -0
- data/lib/HDLRuby/hdr_samples/with_register_stack.rb +150 -0
- data/lib/HDLRuby/hdr_samples/with_sequencer.rb +190 -0
- data/lib/HDLRuby/hdr_samples/with_sequencer_deep.rb +91 -0
- data/lib/HDLRuby/hdr_samples/with_sequencer_enumerable.rb +405 -0
- data/lib/HDLRuby/hdr_samples/with_sequencer_enumerator.rb +89 -0
- data/lib/HDLRuby/hdr_samples/with_sequencer_sync.rb +120 -0
- data/lib/HDLRuby/hdrcc.rb +15 -2
- data/lib/HDLRuby/hdrlib.rb +1 -1
- data/lib/HDLRuby/hruby_db.rb +2 -2
- data/lib/HDLRuby/hruby_high.rb +38 -20
- data/lib/HDLRuby/hruby_high_fullname.rb +3 -1
- data/lib/HDLRuby/hruby_low.rb +2 -2
- data/lib/HDLRuby/hruby_low2c.rb +58 -43
- data/lib/HDLRuby/hruby_low2hdr.rb +66 -40
- data/lib/HDLRuby/hruby_low2high.rb +86 -44
- data/lib/HDLRuby/hruby_low2seq.rb +26 -18
- data/lib/HDLRuby/hruby_low2sym.rb +14 -13
- data/lib/HDLRuby/hruby_low2vhd.rb +78 -43
- data/lib/HDLRuby/hruby_low_bool2select.rb +61 -46
- data/lib/HDLRuby/hruby_low_casts_without_expression.rb +56 -44
- data/lib/HDLRuby/hruby_low_cleanup.rb +18 -16
- data/lib/HDLRuby/hruby_low_fix_types.rb +64 -32
- data/lib/HDLRuby/hruby_low_mutable.rb +53 -118
- data/lib/HDLRuby/hruby_low_resolve.rb +26 -31
- data/lib/HDLRuby/hruby_low_with_bool.rb +33 -16
- data/lib/HDLRuby/hruby_low_with_port.rb +3 -3
- data/lib/HDLRuby/hruby_low_with_var.rb +23 -9
- data/lib/HDLRuby/hruby_low_without_concat.rb +19 -13
- data/lib/HDLRuby/hruby_low_without_namespace.rb +47 -32
- data/lib/HDLRuby/hruby_low_without_parinseq.rb +18 -12
- data/lib/HDLRuby/hruby_low_without_select.rb +36 -23
- data/lib/HDLRuby/hruby_low_without_subsignals.rb +29 -28
- data/lib/HDLRuby/hruby_rcsim.rb +79 -64
- data/lib/HDLRuby/hruby_rsim.rb +64 -15
- data/lib/HDLRuby/hruby_rsim_mute.rb +2 -3
- data/lib/HDLRuby/hruby_rsim_vcd.rb +28 -25
- data/lib/HDLRuby/hruby_values.rb +13 -2
- data/lib/HDLRuby/hruby_verilog.rb +90 -48
- data/lib/HDLRuby/soft/stacks.rb +219 -0
- data/lib/HDLRuby/std/bram.rb +9 -5
- data/lib/HDLRuby/std/clocks.rb +1 -1
- data/lib/HDLRuby/std/fsm.rb +29 -9
- data/lib/HDLRuby/std/sequencer.rb +1857 -0
- data/lib/HDLRuby/std/sequencer_sync.rb +400 -0
- data/lib/HDLRuby/std/std.rb +12 -0
- data/lib/HDLRuby/version.rb +1 -1
- data/tuto/adder_sat_flags_vcd.png +0 -0
- data/tuto/addsub_vcd.png +0 -0
- data/tuto/alu_vcd.png +0 -0
- data/tuto/bit_pong_vcd.png +0 -0
- data/tuto/checksum_vcd.png +0 -0
- data/tuto/circuit_hdr.odg +0 -0
- data/tuto/circuit_hdr.png +0 -0
- data/tuto/circuit_hie.odg +0 -0
- data/tuto/circuit_hie.png +0 -0
- data/tuto/circuit_view.odg +0 -0
- data/tuto/circuit_view.png +0 -0
- data/tuto/clock_counter_vcd.png +0 -0
- data/tuto/counter_ext_vcd.png +0 -0
- data/tuto/fact_vcd.png +0 -0
- data/tuto/hw_flow.odg +0 -0
- data/tuto/hw_flow.png +0 -0
- data/tuto/maxxer_vcd.png +0 -0
- data/tuto/pingpong0_vcd.png +0 -0
- data/tuto/pingpong1_vcd.png +0 -0
- data/tuto/pingpong2_vcd.png +0 -0
- data/tuto/ram_vcd.png +0 -0
- data/tuto/serializer_vcd.png +0 -0
- data/tuto/sw_flow.odg +0 -0
- data/tuto/sw_flow.png +0 -0
- data/tuto/the_counter_vcd.png +0 -0
- data/tuto/tutorial_sw.html +2359 -0
- data/tuto/tutorial_sw.md +2684 -0
- data/tuto/tutorial_sw.pdf +0 -0
- data/tuto/tutorial_sw_jp.md +417 -0
- metadata +44 -2
@@ -0,0 +1,219 @@
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require 'std/bram'
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module HDLRuby::High::Soft
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# Declare the possible commands for the stack.
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PUSH = 0 # Pushes the value of input din into the stack.
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POP = 1 # Pops din values for the stack. If din is negative, allocates din elements on the stack.
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READ = 2 # Read the value address din and output it on dout.
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WRITE = 3 # Write the value at the top of the stack at address din.
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# Describe a stack based on a BRAM (compatible with FPGA's)
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# - 'widthD': data bit width
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# - 'size' : the size of the stack
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system :bram_stack do |widthD, size|
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# Compute the address width.
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widthA = (size-1).width
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# Compute the bit width of the stack pointer register.
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widthS = (size+1).width
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# Declare the inputs and outputs.
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input :clk, :rst, :ce
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input :cmd
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[widthD].input :din
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[widthD].output :dout
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output :empty, :full
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# Declare the BRAM containing the stack data.
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inner rwb: 1
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[widthA].inner :addr
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[widthD].inner :brin, :brout
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bram(widthA,widthD).(:bramI).(clk,rwb,addr,brin,brout)
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# Declare the stack pointer register and the top of stack value.
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[widthS].inner sp: size
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[widthD].inner :top
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# Tells if the stack is empty or full.
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empty <= (sp == size)
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full <= (sp == 0)
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# The output bus is the top of the stack.
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dout <= top
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# The clock process handling the access.
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seq(clk.posedge) do
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# By default, read before the top of the memory.
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rwb <= 1
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hif(rst) do
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# sp is set to size (stack empty).
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sp <= size
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top <= 0
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end
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helsif(ce) do
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# Now depending on the command.
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hcase(cmd)
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hwhen(PUSH) do
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# Is the stack full?
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hif(~full) do
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# No, can push onto the stack.
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# Update the top register.
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top <= din
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# Update the bram.
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brin <= din
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rwb <= 0
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# Finally, decrease sp.
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sp <= sp - 1
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# The address is the top of the stack
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addr <= sp
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end
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end
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hwhen(POP) do
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# Is the stack empty?
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hif(~empty) do
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# No, can pop from the stack.
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# Update the top register.
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top <= brout
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# Finally, increase sp.
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sp <= sp + 1
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end
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end
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end
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hif(~ce | cmd != PUSH) do
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# By default the address is the top of the stack + 1
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addr <= sp + 1
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end
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end
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end
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# Describe a frame stack based on a BRAM (compatible with FPGA's)
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# - 'widthD': data bit width
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# - 'size' : the size of the stack
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# - 'depth' : the maximum number of frames.
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system :bram_frame_stack do |widthD, size, depth|
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# Compute the address width.
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widthA = (size-1).width
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# Compute the bit width of the frame pointers.
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widthF = (size+1).width
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# compute the bit width of the frame stack pointer.
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widthS = (depth+1).width
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# Create the type used for accessing the frame stack.
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typedef(:locT) { { frame: bit[widthS], offset: bit[widthF] } }
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# Declare the inputs and outputs.
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input :clk, :rst, :ce
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[2].input :cmd
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locT.input :loc
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[widthD].input :din
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[widthD].output :dout
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output :empty, :full
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# Declare the frame index stac pointer.
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[widthS].inner :sp
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# Declare the frame index table.
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bit[widthF][-depth].inner :indexes
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# Declare the BRAM containing the frames data.
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inner rwb: 1
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[widthA].inner :addr
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[widthD].inner :brin, :brout
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bram(widthA,widthD).(:bramI).(clk,rwb,addr,brin,brout)
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# Tells if the stack is empty or full.
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empty <= (sp == depth)
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full <= (sp == 0)
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# The input data is always the input of the bram.
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brin <= din
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# The output is always the output of the bram.
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dout <= brout
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# The clock process handling the access.
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seq(clk.posedge) do
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# By default, read before the top of the memory.
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rwb <= 1
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hif(rst) do
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# sp is set to depth (stack empty).
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sp <= depth
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end
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helsif(ce) do
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# Now depending on the command.
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hcase(cmd)
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hwhen(PUSH) do
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# Is the stack full or is the frame to push empty?
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hif(~(full | loc.offset == 0)) do
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# No, we can proceed.
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# Decrease sp.
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sp <= sp - 1
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# Adds the frame.
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hif(~empty) do
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indexes[sp] <= loc.offset + indexes[sp+1]
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end
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helse do
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indexes[sp] <= loc.offset
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end
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end
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end
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hwhen(POP) do
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# Is the stack empty?
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hif(~empty) do
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# No, can pop a frame from the stack.
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# Increase sp.
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sp <= sp + 1
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end
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end
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hwhen(READ) do
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# Read access, is the frame valid?
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cur_frame = sp+loc.frame
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hif (~(empty | cur_frame >= depth)) do
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# The frame is valid. Is the offset valid?
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addr_calc = indexes[cur_frame] - loc.offset - 1
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hif ((cur_frame < depth-1) &
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(addr_calc > indexes[cur_frame+1])) do
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# Not the first frame and the address is valid.
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addr <= addr_calc
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end
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helsif ((cur_frame == depth-1) &
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(addr_calc + 1 > 0)) do
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# The first frame and the address is valid.
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addr <= addr_calc
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end
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end
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end
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hwhen(WRITE) do
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# Write access, is the frame valid?
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cur_frame = sp+loc.frame
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hif (~(empty | cur_frame >= depth)) do
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# The frame is valid. Is the offset valid?
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addr_calc = indexes[cur_frame] - loc.offset - 1
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hif ((cur_frame < depth-1) &
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(addr_calc > indexes[cur_frame+1])) do
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# Not the first frame and the address is valid.
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addr <= addr_calc
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rwb <= 0
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end
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helsif ((cur_frame == depth-1) &
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(addr_calc + 1 > 0)) do
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# The first frame and the address is valid.
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addr <= addr_calc
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rwb <= 0
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end
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end
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end
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end
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end
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end
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end
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data/lib/HDLRuby/std/bram.rb
CHANGED
@@ -3,18 +3,22 @@ module HDLRuby::High::Std
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# Describe a RAM compatibile with BRAM of FPGAs.
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# - 'widthA': address bit width
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# - 'widthD': data bit width
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-
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# - 'size': the size of the memory.
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system :bram do |widthA, widthD, size = nil|
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# Process size if required.
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size = 2**widthA unless size
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# puts "widthA=#{widthA} widthD=#{widthD} size=#{size}"
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# Declares the io of the ram.
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input :clk, :rwb
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[widthA].input :addr
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[widthD].input :din
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[widthD].output :dout
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-
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-
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bit[widthD][-2**widthA].inner mem: [ :"_b#{"0"*widthD}".to_value ] * 2**widthA
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bit[widthD][-size].inner mem: [ :"_b#{"0"*widthD}".to_value ] * size
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par(clk.negedge) do
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hif(rwb ==
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hif(rwb == 0) { mem[addr] <= din }
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dout <= mem[addr]
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end
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end
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data/lib/HDLRuby/std/clocks.rb
CHANGED
@@ -135,8 +135,8 @@ module HDLRuby::High::Std
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end
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# Enhnace the events with multiply operator.
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class HDLRuby::High::Event
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# Enhance the events with multiply operator.
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# Creates a new event activated every +times+ occurences of the
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# current event.
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data/lib/HDLRuby/std/fsm.rb
CHANGED
@@ -31,8 +31,10 @@ module HDLRuby::High::Std
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# Creates a new fsm type with +name+.
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# +options+ allows to specify the type of fsm:
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# synchronous (default)
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#
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# - :sync, :synchronous : synchronous (default)
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# - :async, :asynchronous : asynchronous
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# - :dual : dual front
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# - :seq, :blocking : use blocking assignments
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def initialize(name,*options)
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# Check and set the name
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@name = name.to_sym
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@@ -40,6 +42,7 @@ module HDLRuby::High::Std
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@dual = false
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@type = :sync # By default, the FSM is synchronous.
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@sequential = true # By default, the default next state is the next one in the list.
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@blocking = false # By default, use non-blocking assignments (par)
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options.each do |opt|
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case opt
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when :sync,:synchronous then
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@@ -50,10 +53,23 @@ module HDLRuby::High::Std
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@dual = true
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when :static then
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@sequential = false
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when :seq then
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@blocking = true
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when :blocking then
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@blocking = true
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else
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raise AnyError, "Invalid option for a fsm: :#{type}"
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end
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end
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if @blocking then
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define_singleton_method(:fsm_block) do |*args,&ruby_block|
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send(:seq,*args,&ruby_block)
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end
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else
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define_singleton_method(:fsm_block) do |*args,&ruby_block|
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send(:par,*args,&ruby_block)
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end
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end
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# Initialize the internals of the FSM.
|
59
75
|
|
@@ -127,7 +143,8 @@ module HDLRuby::High::Std
|
|
127
143
|
# sub do
|
128
144
|
HDLRuby::High.space_push(namespace)
|
129
145
|
# Execute the instantiation block
|
130
|
-
return_value = HDLRuby::High.top_user.instance_exec(&ruby_block)
|
146
|
+
# return_value = HDLRuby::High.top_user.instance_exec(&ruby_block)
|
147
|
+
return_value = HDLRuby::High.top_user.instance_exec(&ruby_block) if ruby_block
|
131
148
|
|
132
149
|
# Expands the extra state processing so that al all the
|
133
150
|
# parts of the state machine are in par (clear synthesis).
|
@@ -171,7 +188,8 @@ module HDLRuby::High::Std
|
|
171
188
|
# Create the fsm code
|
172
189
|
|
173
190
|
# Control part: update of the state.
|
174
|
-
par(mk_ev.call) do
|
191
|
+
# par(mk_ev.call) do
|
192
|
+
fsm_block(mk_ev.call) do
|
175
193
|
hif(mk_rst.call) do
|
176
194
|
# Reset: current state is to put to 0.
|
177
195
|
this.cur_state_sig <= 0
|
@@ -194,7 +212,8 @@ module HDLRuby::High::Std
|
|
194
212
|
event = []
|
195
213
|
end
|
196
214
|
# The process
|
197
|
-
par(*event) do
|
215
|
+
# par(*event) do
|
216
|
+
fsm_block(*event) do
|
198
217
|
# The operative code.
|
199
218
|
oper_code = proc do
|
200
219
|
# The default code.
|
@@ -241,8 +260,6 @@ module HDLRuby::High::Std
|
|
241
260
|
st.gotos.each(&:call)
|
242
261
|
else
|
243
262
|
# No gotos, by default the next step is
|
244
|
-
# current + 1
|
245
|
-
# this.next_state_sig <= this.cur_state_sig + 1
|
246
263
|
if sequential then
|
247
264
|
this.next_state_sig <= this.cur_state_sig + 1
|
248
265
|
end
|
@@ -251,6 +268,7 @@ module HDLRuby::High::Std
|
|
251
268
|
end
|
252
269
|
# By default set the next state to 0.
|
253
270
|
helse do
|
271
|
+
# hprint("Unknow state case: ",this.cur_state_sig,"\n")
|
254
272
|
this.next_state_sig <= 0
|
255
273
|
end
|
256
274
|
|
@@ -260,7 +278,8 @@ module HDLRuby::High::Std
|
|
260
278
|
event = mk_ev.call
|
261
279
|
event = event.invert if @dual
|
262
280
|
# The extra code.
|
263
|
-
par(*event) do
|
281
|
+
# par(*event) do
|
282
|
+
fsm_block(*event) do
|
264
283
|
# Build the extra synchronous part.
|
265
284
|
sync_code = proc do
|
266
285
|
hcase(this.cur_state_sig)
|
@@ -289,7 +308,8 @@ module HDLRuby::High::Std
|
|
289
308
|
|
290
309
|
# Extra asynchronous operative part.
|
291
310
|
if extra_asyncs.any? then
|
292
|
-
par do
|
311
|
+
# par do
|
312
|
+
fsm_block do
|
293
313
|
# Build the extra synchronous part.
|
294
314
|
async_code = proc do
|
295
315
|
hcase(this.cur_state_sig)
|