tdl-xoa-driver 1.5.0b2__py3-none-any.whl → 1.6.0__py3-none-any.whl
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- {tdl_xoa_driver-1.5.0b2.dist-info → tdl_xoa_driver-1.6.0.dist-info}/METADATA +8 -8
- {tdl_xoa_driver-1.5.0b2.dist-info → tdl_xoa_driver-1.6.0.dist-info}/RECORD +91 -89
- xoa_driver/__init__.py +2 -2
- xoa_driver/enums.py +10 -10
- xoa_driver/functions/anlt.py +60 -78
- xoa_driver/functions/cli/__init__.py +5 -5
- xoa_driver/functions/cli/port_config.py +16 -7
- xoa_driver/functions/cli/{test_case_config.py → testbed_config.py} +53 -46
- xoa_driver/functions/cmis/_replies.py +4 -4
- xoa_driver/functions/mgmt.py +206 -250
- xoa_driver/functions/tools.py +11 -6
- xoa_driver/internals/commands/c_commands.py +59 -0
- xoa_driver/internals/commands/enums.py +101 -90
- xoa_driver/internals/commands/m4_commands.py +25 -0
- xoa_driver/internals/commands/m4e_commands.py +6 -0
- xoa_driver/internals/commands/m_commands.py +51 -1
- xoa_driver/internals/commands/p4_commands.py +63 -1
- xoa_driver/internals/commands/p4e_commands.py +9 -0
- xoa_driver/internals/commands/p4g_commands.py +139 -0
- xoa_driver/internals/commands/p_commands.py +493 -63
- xoa_driver/internals/commands/pc_commands.py +9 -0
- xoa_driver/internals/commands/pd_commands.py +11 -0
- xoa_driver/internals/commands/pe_commands.py +27 -0
- xoa_driver/internals/commands/pec_commands.py +9 -0
- xoa_driver/internals/commands/ped_commands.py +23 -0
- xoa_driver/internals/commands/pef_commands.py +43 -0
- xoa_driver/internals/commands/pf_commands.py +11 -0
- xoa_driver/internals/commands/pl1_commands.py +442 -118
- xoa_driver/internals/commands/pl_commands.py +8 -0
- xoa_driver/internals/commands/pm_commands.py +11 -0
- xoa_driver/internals/commands/pp_commands.py +128 -82
- xoa_driver/internals/commands/pr_commands.py +25 -0
- xoa_driver/internals/commands/ps_commands.py +47 -1
- xoa_driver/internals/commands/pt_commands.py +15 -0
- xoa_driver/internals/commands/px_commands.py +180 -136
- xoa_driver/internals/commands/subtypes.py +4 -3
- xoa_driver/internals/core/transporter/protocol/payload/base_struct.py +1 -1
- xoa_driver/internals/hli/indices/macsecscs/base_macsecsc.py +41 -3
- xoa_driver/internals/hli/modules/modules_l23/family_combi.py +0 -64
- xoa_driver/internals/hli/modules/modules_l23/family_edun.py +0 -2
- xoa_driver/internals/hli/modules/modules_l23/{family_g.py → family_loki.py} +29 -1
- xoa_driver/internals/hli/modules/modules_l23/family_odin.py +412 -0
- xoa_driver/internals/hli/modules/modules_l23/{family_l.py → family_thor.py} +44 -0
- xoa_driver/internals/hli/ports/port_l23/chimera/port_chimera.py +3 -3
- xoa_driver/internals/hli/ports/port_l23/family_edun.py +9 -44
- xoa_driver/internals/hli/ports/port_l23/{family_l1.py → family_freya.py} +10 -45
- xoa_driver/internals/hli/ports/port_l23/{family_g.py → family_loki.py} +33 -32
- xoa_driver/internals/hli/ports/port_l23/family_odin.py +225 -0
- xoa_driver/internals/hli/ports/port_l23/family_thor.py +67 -0
- xoa_driver/internals/hli/ports/port_l23/layer1/anlt.py +512 -0
- xoa_driver/internals/hli/ports/port_l23/layer1/brr.py +26 -0
- xoa_driver/internals/hli/ports/port_l23/layer1/eye_diagram.py +71 -0
- xoa_driver/internals/hli/ports/port_l23/{pcs_pma_ijkl_chimera.py → layer1/impair.py} +7 -7
- xoa_driver/internals/hli/ports/port_l23/layer1/laser_power.py +28 -0
- xoa_driver/internals/hli/ports/port_l23/{family_e.py → layer1/lower_power.py} +1 -51
- xoa_driver/internals/hli/ports/port_l23/{freya_l1.py → layer1/medium.py} +38 -358
- xoa_driver/internals/hli/ports/port_l23/layer1/pcs_fec.py +219 -0
- xoa_driver/internals/hli/ports/port_l23/layer1/pma.py +43 -0
- xoa_driver/internals/hli/ports/port_l23/layer1/prbs.py +39 -0
- xoa_driver/internals/hli/ports/port_l23/layer1/preamble.py +25 -0
- xoa_driver/internals/hli/ports/port_l23/{fault_jkl.py → layer1/rs_fault.py} +2 -2
- xoa_driver/internals/hli/ports/port_l23/layer1/siv.py +69 -0
- xoa_driver/internals/hli/ports/port_l23/layer1_edun.py +103 -0
- xoa_driver/internals/hli/ports/port_l23/layer1_freya.py +103 -0
- xoa_driver/internals/hli/ports/port_l23/layer1_loki.py +74 -0
- xoa_driver/internals/hli/ports/port_l23/layer1_thor.py +70 -0
- xoa_driver/internals/hli/ports/port_l23/port_l23ve.py +4 -4
- xoa_driver/internals/hli/ports/port_l23/sec/__init__.py +0 -0
- xoa_driver/internals/hli/ports/port_l23/sec/macsec.py +108 -0
- xoa_driver/internals/hli/ports/port_l23/tcvr/__init__.py +0 -0
- xoa_driver/internals/hli/ports/port_l23/{bases/port_transceiver.py → tcvr/cmis.py} +4 -118
- xoa_driver/internals/hli/ports/port_l23/tcvr/transceiver.py +124 -0
- xoa_driver/internals/hli/ports/port_l23/trafficgen/__init__.py +0 -0
- xoa_driver/internals/hli/ports/port_l23/{bases → trafficgen}/port_l23.py +1 -1
- xoa_driver/internals/hli/ports/port_l23/{bases → trafficgen}/port_l23_genuine.py +5 -45
- xoa_driver/internals/hli/ports/port_l23/{bases/port_reception_statistics.py → trafficgen/port_rx_stats.py} +0 -21
- xoa_driver/internals/hli/ports/port_l23/{bases/port_transmission_statistics.py → trafficgen/port_tx_stats.py} +2 -22
- xoa_driver/internals/hli/ports/port_l23/trafficgen/runt.py +32 -0
- xoa_driver/internals/hli/testers/l23_tester.py +1 -3
- xoa_driver/internals/utils/indices/_interfaces.py +18 -6
- xoa_driver/internals/utils/indices/index_manager.py +8 -2
- xoa_driver/internals/utils/managers/ports_manager.py +5 -2
- xoa_driver/misc.py +6 -6
- xoa_driver/modules.py +31 -47
- xoa_driver/ports.py +10 -29
- xoa_driver/internals/hli/modules/modules_l23/family_d.py +0 -75
- xoa_driver/internals/hli/modules/modules_l23/family_e.py +0 -85
- xoa_driver/internals/hli/modules/modules_l23/family_f.py +0 -145
- xoa_driver/internals/hli/modules/modules_l23/family_h.py +0 -40
- xoa_driver/internals/hli/modules/modules_l23/family_i.py +0 -25
- xoa_driver/internals/hli/modules/modules_l23/family_j.py +0 -25
- xoa_driver/internals/hli/modules/modules_l23/family_k.py +0 -39
- xoa_driver/internals/hli/modules/modules_l23/family_m.py +0 -25
- xoa_driver/internals/hli/modules/modules_l23/family_n.py +0 -40
- xoa_driver/internals/hli/ports/port_l23/family_combi.py +0 -37
- xoa_driver/internals/hli/ports/port_l23/family_d.py +0 -51
- xoa_driver/internals/hli/ports/port_l23/family_f.py +0 -151
- xoa_driver/internals/hli/ports/port_l23/family_h.py +0 -67
- xoa_driver/internals/hli/ports/port_l23/family_i.py +0 -84
- xoa_driver/internals/hli/ports/port_l23/family_j.py +0 -68
- xoa_driver/internals/hli/ports/port_l23/family_k.py +0 -73
- xoa_driver/internals/hli/ports/port_l23/family_l.py +0 -82
- xoa_driver/internals/hli/ports/port_l23/family_m.py +0 -29
- xoa_driver/internals/hli/ports/port_l23/pcs_pma_ghijkl.py +0 -369
- xoa_driver/internals/hli/ports/port_l23/pcs_pma_l.py +0 -78
- {tdl_xoa_driver-1.5.0b2.dist-info → tdl_xoa_driver-1.6.0.dist-info}/WHEEL +0 -0
- {tdl_xoa_driver-1.5.0b2.dist-info → tdl_xoa_driver-1.6.0.dist-info}/licenses/LICENSE +0 -0
- {tdl_xoa_driver-1.5.0b2.dist-info → tdl_xoa_driver-1.6.0.dist-info}/top_level.txt +0 -0
- /xoa_driver/internals/hli/modules/modules_l23/{family_l1.py → family_freya.py} +0 -0
- /xoa_driver/internals/hli/ports/port_l23/{bases → layer1}/__init__.py +0 -0
- /xoa_driver/internals/hli/ports/port_l23/{bases → trafficgen}/port_capture.py +0 -0
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"""Port Advanced Layer 1 Commands"""
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from __future__ import annotations
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from dataclasses import dataclass
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import typing
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OnOff,
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FreyaLinkTrainingMode,
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FreyaAutonegMode,
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AutoNegTecAbility,
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AutoNegFECAbility,
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AutoNegPauseAbility,
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AutoNegMode,
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AutoNegStatus,
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AutoNegTechAbilityHCDStatus,
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FECMode,
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PauseMode,
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FreyaOutOfSyncPreset,
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Layer1Control,
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FreyaPCSVariant,
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AutoNegTecAbilityHCD,
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class PL1_AUTONEGINFO:
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"""
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Get
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Get advanced auto-negotiation statistics. Statistics are split into a number of pages.
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code: typing.ClassVar[int] = 385
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"""Get the lower and the upper bound of transmit equalizer (native value) of the serdes, and how the serdes responds to an increment/decrement request when either bound is reached.
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:return: lower and upper bound of transmit equalizer (native value) and response mode
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:rtype: PL1_LT_PHYTXEQ_RANGE.GetDataAttr
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"""
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"""Set the lower and the upper bound of transmit equalizer (native value) of the serdes, and how the serdes responds to an increment/decrement request when either bound is reached.
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"""Set the lower and the upper bound of transmit equalizer (native value) of the serdes, and how the serdes responds to an increment/decrement request when either bound is reached.
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888
|
+
:param response: How to respond to the received IC request.
|
|
889
|
+
:type response: FreyaPresetResponse
|
|
890
|
+
:param pre3: The pre3 tap value, negative, scaled by 1E3.
|
|
891
|
+
:type pre3: int
|
|
892
|
+
:param pre2: The pre2 tap value, positive, scaled by 1E3.
|
|
893
|
+
:type pre2: int
|
|
894
|
+
:param pre: The pre tap value, negative, scaled by 1E3.
|
|
895
|
+
:type pre: int
|
|
896
|
+
:param main: The main tap value, positive, scaled by 1E3.
|
|
897
|
+
:type main: int
|
|
898
|
+
:param post: The post tap value, negative, scaled by 1E3.
|
|
899
|
+
:type post: int
|
|
900
|
+
"""
|
|
826
901
|
return Token(
|
|
827
902
|
self._connection,
|
|
828
903
|
build_set_request(self, module=self._module, port=self._port, indices=[self._serdes_xindex, self._preset_xindex], response=response, pre3=pre3, pre2=pre2, pre=pre, main=main, post=post))
|
|
@@ -832,11 +907,21 @@ class PL1_PRESET_CONFIG_COEFF:
|
|
|
832
907
|
@dataclass
|
|
833
908
|
class PL1_PHYTXEQ_LEVEL:
|
|
834
909
|
"""
|
|
835
|
-
Control and monitor the equalizer settings of the on-board PHY in the transmission direction (towards the transceiver cage).
|
|
910
|
+
Control and monitor the equalizer settings (mV/dB values) of the on-board PHY in the transmission direction (towards the transceiver cage).
|
|
911
|
+
|
|
912
|
+
This command returns a variable number of tap values with module-dependent ordering:
|
|
913
|
+
|
|
914
|
+
- **Regular Freya**: Original fixed format [pre3, pre2, pre, main, post]
|
|
915
|
+
- **Loki-4P and H-Freya/Edun**: Variable number in N*pre, main, M*post layout
|
|
916
|
+
|
|
917
|
+
``[pre_n, pre_n-1, ..., pre_1, main, post_1, post_2, ..., post_m]``
|
|
918
|
+
|
|
919
|
+
Query port capabilities for ``numtxeqtaps`` and ``numtxeqpretaps`` to determine
|
|
920
|
+
the number of taps and layout.
|
|
836
921
|
|
|
837
922
|
.. note::
|
|
838
923
|
|
|
839
|
-
PL1_PHYTXEQ
|
|
924
|
+
``PL1_PHYTXEQ``, ``PL1_PHYTXEQ_LEVEL``, and ``PL1_PHYTXEQ_COEFF`` facilitate the configuration and retrieval of TX tap values, each offering a unique perspective. Modifications made with any of these parameters will result in updates to the read results across all of them.
|
|
840
925
|
|
|
841
926
|
"""
|
|
842
927
|
|
|
@@ -849,44 +934,64 @@ class PL1_PHYTXEQ_LEVEL:
|
|
|
849
934
|
_serdes_xindex: int
|
|
850
935
|
|
|
851
936
|
class GetDataAttr(ResponseBodyStruct):
|
|
852
|
-
|
|
853
|
-
"""
|
|
854
|
-
|
|
855
|
-
|
|
856
|
-
|
|
857
|
-
|
|
858
|
-
|
|
859
|
-
|
|
860
|
-
post: int = field(XmpInt())
|
|
861
|
-
"""integer, post tap value in dB/10, ranges from 0 to 187 Default = 0 (neutral)"""
|
|
862
|
-
|
|
937
|
+
tap_values: typing.List[int] = field(XmpSequence(types_chunk=[XmpInt()]))
|
|
938
|
+
"""list of integers, TX EQ tap values in mV/dB. The number and layout depend on the platform:
|
|
939
|
+
|
|
940
|
+
- Regular Freya: [pre3, pre2, pre, main, post] where pre3/pre2 in dB/10 (0-71), pre/post in dB/10 (0-187), main in mV (507-998)
|
|
941
|
+
- Loki-4P and H-Freya/Edun: [pre_n, ..., pre_1, main, post_1, post_2, ..., post_m]
|
|
942
|
+
where N = numtxeqpretaps and M = numtxeqtaps - numtxeqpretaps - 1
|
|
943
|
+
"""
|
|
944
|
+
|
|
863
945
|
class SetDataAttr(RequestBodyStruct):
|
|
864
|
-
|
|
865
|
-
"""
|
|
866
|
-
|
|
867
|
-
|
|
868
|
-
|
|
869
|
-
|
|
870
|
-
|
|
871
|
-
"""integer, main tap value in mV, ranges from 507 to 998."""
|
|
872
|
-
post: int = field(XmpInt())
|
|
873
|
-
"""integer, post tap value in dB/10, ranges from 0 to 187 Default = 0 (neutral)"""
|
|
946
|
+
tap_values: typing.List[int] = field(XmpSequence(types_chunk=[XmpInt()]))
|
|
947
|
+
"""list of integers, TX EQ tap values in mV/dB. The number and layout depend on the platform:
|
|
948
|
+
|
|
949
|
+
- Regular Freya: [pre3, pre2, pre, main, post] where pre3/pre2 in dB/10 (0-71), pre/post in dB/10 (0-187), main in mV (507-998)
|
|
950
|
+
- Loki-4P and H-Freya/Edun: [pre_n, ..., pre_1, main, post_1, post_2, ..., post_m]
|
|
951
|
+
where N = numtxeqpretaps and M = numtxeqtaps - numtxeqpretaps - 1
|
|
952
|
+
"""
|
|
874
953
|
|
|
875
954
|
def get(self) -> Token[GetDataAttr]:
|
|
955
|
+
"""Get the TX equalizer settings (mV/dB values) of the on-board PHY.
|
|
956
|
+
|
|
957
|
+
The returned tap values layout depends on the platform. Query P_CAPABILITIES
|
|
958
|
+
for ``numtxeqtaps`` and ``numtxeqpretaps`` to determine the format.
|
|
959
|
+
|
|
960
|
+
:return: list of TX EQ tap values in mV/dB
|
|
961
|
+
:rtype: PL1_PHYTXEQ_LEVEL.GetDataAttr
|
|
962
|
+
"""
|
|
876
963
|
|
|
877
964
|
return Token(self._connection, build_get_request(self, module=self._module, port=self._port, indices=[self._serdes_xindex]))
|
|
878
965
|
|
|
879
|
-
def set(self,
|
|
966
|
+
def set(self, tap_values: typing.List[int]) -> Token[None]:
|
|
967
|
+
"""Set the TX equalizer settings (mV/dB values) of the on-board PHY.
|
|
968
|
+
|
|
969
|
+
The tap values layout depends on the platform. Query P_CAPABILITIES
|
|
970
|
+
for ``numtxeqtaps`` and ``numtxeqpretaps`` to determine the required format.
|
|
971
|
+
|
|
972
|
+
:param tap_values: list of TX EQ tap values in mV/dB in platform-specific order
|
|
973
|
+
:type tap_values: typing.List[int]
|
|
974
|
+
"""
|
|
880
975
|
|
|
881
976
|
return Token(
|
|
882
977
|
self._connection,
|
|
883
|
-
build_set_request(self, module=self._module, port=self._port, indices=[self._serdes_xindex],
|
|
884
|
-
|
|
978
|
+
build_set_request(self, module=self._module, port=self._port, indices=[self._serdes_xindex], tap_values=tap_values))
|
|
979
|
+
|
|
885
980
|
@register_command
|
|
886
981
|
@dataclass
|
|
887
982
|
class PL1_PHYTXEQ_COEFF:
|
|
888
983
|
"""
|
|
889
|
-
Control and monitor the equalizer settings of the on-board PHY in the transmission direction (towards the transceiver cage).
|
|
984
|
+
Control and monitor the equalizer settings (IEEE coefficient values) of the on-board PHY in the transmission direction (towards the transceiver cage).
|
|
985
|
+
|
|
986
|
+
This command returns a variable number of tap values with module-dependent ordering:
|
|
987
|
+
|
|
988
|
+
- **Regular Freya**: Original fixed format [pre3, pre2, pre, main, post]
|
|
989
|
+
- **Loki-4P and H-Freya/Edun**: Variable number in N*pre, main, M*post layout
|
|
990
|
+
|
|
991
|
+
``[pre_n, pre_n-1, ..., pre_1, main, post_1, post_2, ..., post_m]``
|
|
992
|
+
|
|
993
|
+
Use P_CAPABILITIES to query ``numtxeqtaps`` and ``numtxeqpretaps`` to determine
|
|
994
|
+
the number of taps and layout.
|
|
890
995
|
|
|
891
996
|
.. note::
|
|
892
997
|
|
|
@@ -894,12 +999,12 @@ class PL1_PHYTXEQ_COEFF:
|
|
|
894
999
|
|
|
895
1000
|
The following rules apply:
|
|
896
1001
|
|
|
897
|
-
* 0.5 approx.
|
|
898
|
-
* -0.4 approx
|
|
899
|
-
* -0.4 approx
|
|
900
|
-
* 0
|
|
901
|
-
* -0.25 approx
|
|
902
|
-
* The sum of the absolute value of each coefficients must be
|
|
1002
|
+
* 0.5 approx. <= main <= 1
|
|
1003
|
+
* -0.4 approx <= post <= 0
|
|
1004
|
+
* -0.4 approx <= pre <= 0
|
|
1005
|
+
* 0 <= pre2 <= 0.25 approx.
|
|
1006
|
+
* -0.25 approx <= pre3 <= 0
|
|
1007
|
+
* The sum of the absolute value of each coefficients must be <= 1.
|
|
903
1008
|
* A sum of 1 corresponds to a TX output voltage swing of 1000 mVpp approximately.
|
|
904
1009
|
|
|
905
1010
|
"""
|
|
@@ -913,38 +1018,48 @@ class PL1_PHYTXEQ_COEFF:
|
|
|
913
1018
|
_serdes_xindex: int
|
|
914
1019
|
|
|
915
1020
|
class GetDataAttr(ResponseBodyStruct):
|
|
916
|
-
|
|
917
|
-
"""
|
|
918
|
-
|
|
919
|
-
|
|
920
|
-
|
|
921
|
-
|
|
922
|
-
|
|
923
|
-
|
|
924
|
-
post: int = field(XmpInt())
|
|
925
|
-
"""integer, post tap value, negative, scaled by 1E3. Default = 0 (neutral)"""
|
|
926
|
-
|
|
1021
|
+
tap_values: typing.List[int] = field(XmpSequence(types_chunk=[XmpInt()]))
|
|
1022
|
+
"""list of integers, TX EQ tap values as IEEE coefficients scaled by 1E3. The number and layout depend on the platform:
|
|
1023
|
+
|
|
1024
|
+
- Regular Freya: [pre3, pre2, pre, main, post] where pre3/pre/post are negative, pre2/main are positive
|
|
1025
|
+
- Loki-4P and H-Freya/Edun: [pre_n, ..., pre_1, main, post_1, ..., post_m]
|
|
1026
|
+
where N = numtxeqpretaps and M = numtxeqtaps - numtxeqpretaps - 1
|
|
1027
|
+
"""
|
|
1028
|
+
|
|
927
1029
|
class SetDataAttr(RequestBodyStruct):
|
|
928
|
-
|
|
929
|
-
"""
|
|
930
|
-
|
|
931
|
-
|
|
932
|
-
|
|
933
|
-
|
|
934
|
-
|
|
935
|
-
"""integer, main tap value, positive, scaled by 1E3. Default = 1000"""
|
|
936
|
-
post: int = field(XmpInt())
|
|
937
|
-
"""integer, post tap value, negative, scaled by 1E3. Default = 0 (neutral)"""
|
|
1030
|
+
tap_values: typing.List[int] = field(XmpSequence(types_chunk=[XmpInt()]))
|
|
1031
|
+
"""list of integers, TX EQ tap values as IEEE coefficients scaled by 1E3. The number and layout depend on the platform:
|
|
1032
|
+
|
|
1033
|
+
- Regular Freya: [pre3, pre2, pre, main, post] where pre3/pre/post are negative, pre2/main are positive
|
|
1034
|
+
- Loki-4P and H-Freya/Edun: [pre_n, ..., pre_1, main, post_1, ..., post_m]
|
|
1035
|
+
where N = numtxeqpretaps and M = numtxeqtaps - numtxeqpretaps - 1
|
|
1036
|
+
"""
|
|
938
1037
|
|
|
939
1038
|
def get(self) -> Token[GetDataAttr]:
|
|
1039
|
+
"""Get the TX equalizer settings (IEEE coefficient values) of the on-board PHY.
|
|
1040
|
+
|
|
1041
|
+
The returned tap values layout depends on the platform. Query P_CAPABILITIES
|
|
1042
|
+
for ``numtxeqtaps`` and ``numtxeqpretaps`` to determine the format.
|
|
1043
|
+
|
|
1044
|
+
:return: list of TX EQ tap values as IEEE coefficients scaled by 1E3
|
|
1045
|
+
:rtype: PL1_PHYTXEQ_COEFF.GetDataAttr
|
|
1046
|
+
"""
|
|
940
1047
|
|
|
941
1048
|
return Token(self._connection, build_get_request(self, module=self._module, port=self._port, indices=[self._serdes_xindex]))
|
|
942
1049
|
|
|
943
|
-
def set(self,
|
|
1050
|
+
def set(self, tap_values: typing.List[int]) -> Token[None]:
|
|
1051
|
+
"""Set the TX equalizer settings (IEEE coefficient values) of the on-board PHY.
|
|
1052
|
+
|
|
1053
|
+
The tap values layout depends on the platform. Query P_CAPABILITIES
|
|
1054
|
+
for ``numtxeqtaps`` and ``numtxeqpretaps`` to determine the required format.
|
|
1055
|
+
|
|
1056
|
+
:param tap_values: list of TX EQ tap values as IEEE coefficients scaled by 1E3 in platform-specific order
|
|
1057
|
+
:type tap_values: typing.List[int]
|
|
1058
|
+
"""
|
|
944
1059
|
|
|
945
1060
|
return Token(
|
|
946
1061
|
self._connection,
|
|
947
|
-
build_set_request(self, module=self._module, port=self._port, indices=[self._serdes_xindex],
|
|
1062
|
+
build_set_request(self, module=self._module, port=self._port, indices=[self._serdes_xindex], tap_values=tap_values))
|
|
948
1063
|
|
|
949
1064
|
@register_command
|
|
950
1065
|
@dataclass
|
|
@@ -962,25 +1077,70 @@ class PL1_AUTONEG_STATUS:
|
|
|
962
1077
|
|
|
963
1078
|
class GetDataAttr(ResponseBodyStruct):
|
|
964
1079
|
mode: AutoNegMode = field(XmpInt())
|
|
965
|
-
"""Autoneg mode
|
|
1080
|
+
"""Autoneg mode
|
|
1081
|
+
|
|
1082
|
+
:type mode: AutoNegMode
|
|
1083
|
+
"""
|
|
966
1084
|
autoneg_state: AutoNegStatus = field(XmpInt())
|
|
967
|
-
"""Autoneg
|
|
1085
|
+
"""Autoneg status
|
|
1086
|
+
|
|
1087
|
+
:type autoneg_state: AutoNegStatus
|
|
1088
|
+
"""
|
|
1089
|
+
|
|
968
1090
|
received_tech_abilities: Hex = field(XmpHex(size=8))
|
|
969
|
-
"""Received technology abilities from the remote port
|
|
1091
|
+
"""Received technology abilities bitmask from the remote port
|
|
1092
|
+
|
|
1093
|
+
To parse the bitmask, refer to the :class:`AutoNegTecAbility` enum IntFlag.
|
|
1094
|
+
|
|
1095
|
+
:type received_tech_abilities: Hex, 16 characters long.
|
|
1096
|
+
"""
|
|
1097
|
+
|
|
970
1098
|
received_fec_abilities: Hex = field(XmpHex(size=1))
|
|
971
|
-
"""Received FEC capabilities from the remote port
|
|
1099
|
+
"""Received FEC capabilities bitmask from the remote port
|
|
1100
|
+
|
|
1101
|
+
To parse the bitmask, refer to the :class:`AutoNegFECAbility` enum IntFlag.
|
|
1102
|
+
|
|
1103
|
+
:type received_fec_abilities: Hex, 2 characters long.
|
|
1104
|
+
"""
|
|
1105
|
+
|
|
972
1106
|
received_pause_mode: Hex = field(XmpHex(size=1))
|
|
973
|
-
"""Received pause capabilities from the remote port
|
|
974
|
-
|
|
975
|
-
|
|
976
|
-
|
|
977
|
-
|
|
1107
|
+
"""Received pause capabilities bitmask from the remote port
|
|
1108
|
+
|
|
1109
|
+
To parse the bitmask, refer to the :class:`AutoNegPauseAbility` enum IntFlag.
|
|
1110
|
+
|
|
1111
|
+
:type received_pause_mode: Hex, 2 characters long.
|
|
1112
|
+
"""
|
|
1113
|
+
|
|
1114
|
+
tech_ability_hcd_status: AutoNegTechAbilityHCDStatus = field(XmpInt())
|
|
1115
|
+
"""HCD technology ability negotiation status
|
|
1116
|
+
|
|
1117
|
+
:type tech_ability_hcd_status: AutoNegTechAbilityHCDStatus
|
|
1118
|
+
"""
|
|
1119
|
+
|
|
1120
|
+
tech_ability_hcd_value: AutoNegTecAbilityHCD = field(XmpInt())
|
|
1121
|
+
"""HCD technology ability negotiation result
|
|
1122
|
+
|
|
1123
|
+
:type tech_ability_hcd_value: AutoNegTecAbilityHCD
|
|
1124
|
+
"""
|
|
1125
|
+
|
|
978
1126
|
fec_mode_result: FECMode = field(XmpInt())
|
|
979
|
-
"""FEC mode negotiation result
|
|
1127
|
+
"""FEC mode negotiation result
|
|
1128
|
+
|
|
1129
|
+
:type fec_mode_result: FECMode
|
|
1130
|
+
"""
|
|
1131
|
+
|
|
980
1132
|
pause_mode_result: PauseMode = field(XmpInt())
|
|
981
|
-
"""Pause mode negotiation result
|
|
1133
|
+
"""Pause mode negotiation result
|
|
1134
|
+
|
|
1135
|
+
:type pause_mode_result: PauseMode
|
|
1136
|
+
"""
|
|
982
1137
|
|
|
983
1138
|
def get(self) -> Token[GetDataAttr]:
|
|
1139
|
+
"""Get the autonegotiation status.
|
|
1140
|
+
|
|
1141
|
+
:return: The autonegotiation status
|
|
1142
|
+
:rtype: PL1_AUTONEG_STATUS.GetDataAttr
|
|
1143
|
+
"""
|
|
984
1144
|
|
|
985
1145
|
return Token(self._connection, build_get_request(self, module=self._module, port=self._port))
|
|
986
1146
|
|
|
@@ -1000,16 +1160,30 @@ class PL1_AUTONEG_ABILITIES:
|
|
|
1000
1160
|
|
|
1001
1161
|
class GetDataAttr(ResponseBodyStruct):
|
|
1002
1162
|
tech_abilities_supported: Hex = field(XmpHex(size=8))
|
|
1003
|
-
"""
|
|
1163
|
+
"""Supported technology abilities by the port. This returns a value in Hex of the format HHHHHHHH (64 bits). Each bit corresponds to technology ability as defined in :class:`AutoNegTecAbility`. A bit of 1 means the corresponding technology ability is supported by the port.
|
|
1164
|
+
|
|
1165
|
+
|
|
1166
|
+
:type tech_abilities_supported: Hex, 16 characters long.
|
|
1167
|
+
"""
|
|
1004
1168
|
|
|
1005
1169
|
fec_modes_supported: Hex = field(XmpHex(size=1))
|
|
1006
|
-
"""
|
|
1170
|
+
"""Supported FEC modes by the port. This returns a value in Hex of the format HH (8 bits). Each bit corresponds to FEC mode as defined in :class:`AutoNegFECAbility`. A bit of 1 means the corresponding FEC mode is supported by the port.
|
|
1171
|
+
|
|
1172
|
+
:type fec_modes_supported: Hex, 2 characters long.
|
|
1173
|
+
"""
|
|
1007
1174
|
|
|
1008
1175
|
pause_modes_supported: Hex = field(XmpHex(size=1))
|
|
1009
|
-
"""
|
|
1176
|
+
"""Pause abilities supported by the port. This returns a value in Hex of the format HH (8 bits). Each bit corresponds to pause mode as defined in :class:`AutoNegPauseAbility`. A bit of 1 means the corresponding FEC mode is supported by the port.
|
|
1177
|
+
|
|
1178
|
+
:type pause_modes_supported: Hex, 2 characters long.
|
|
1179
|
+
"""
|
|
1010
1180
|
|
|
1011
1181
|
def get(self) -> Token[GetDataAttr]:
|
|
1182
|
+
"""Get the supported technology abilities, FEC abilities, and pause abilities of the port.
|
|
1012
1183
|
|
|
1184
|
+
:return: The supported abilities
|
|
1185
|
+
:rtype: Token[GetDataAttr]
|
|
1186
|
+
"""
|
|
1013
1187
|
return Token(self._connection, build_get_request(self, module=self._module, port=self._port))
|
|
1014
1188
|
|
|
1015
1189
|
@register_command
|
|
@@ -1035,11 +1209,21 @@ class PL1_PCS_VARIANT:
|
|
|
1035
1209
|
"""PCS variant"""
|
|
1036
1210
|
|
|
1037
1211
|
def get(self) -> Token[GetDataAttr]:
|
|
1212
|
+
"""Get the PCS variant configuration.
|
|
1213
|
+
|
|
1214
|
+
:return: The PCS variant configuration
|
|
1215
|
+
:rtype: PL1_PCS_VARIANT.GetDataAttr
|
|
1216
|
+
"""
|
|
1038
1217
|
|
|
1039
1218
|
return Token(self._connection, build_get_request(self, module=self._module, port=self._port))
|
|
1040
1219
|
|
|
1041
1220
|
def set(self, variant: FreyaPCSVariant) -> Token[None]:
|
|
1221
|
+
"""Set the PCS variant configuration.
|
|
1042
1222
|
|
|
1223
|
+
:param variant: The PCS variant configuration to set
|
|
1224
|
+
:type variant: FreyaPCSVariant
|
|
1225
|
+
:return: A token indicating the completion of the set operation
|
|
1226
|
+
"""
|
|
1043
1227
|
return Token(self._connection, build_set_request(self, module=self._module, port=self._port, variant=variant))
|
|
1044
1228
|
|
|
1045
1229
|
|
|
@@ -1075,11 +1259,23 @@ class PL1_CWE_CYCLE:
|
|
|
1075
1259
|
"""The number of consecutive errored FEC codewords in a cycle, must not be larger than cycle_len"""
|
|
1076
1260
|
|
|
1077
1261
|
def get(self) -> Token[GetDataAttr]:
|
|
1262
|
+
"""Get the FEC codeword error injection cycle configuration.
|
|
1078
1263
|
|
|
1264
|
+
:return: The FEC codeword error injection cycle configuration
|
|
1265
|
+
:rtype: PL1_CWE_CYCLE.GetDataAttr
|
|
1266
|
+
"""
|
|
1079
1267
|
return Token(self._connection, build_get_request(self, module=self._module, port=self._port))
|
|
1080
1268
|
|
|
1081
1269
|
def set(self, loop: int, cycle_len: int, error_len: int) -> Token[None]:
|
|
1082
|
-
|
|
1270
|
+
"""Set the FEC codeword error injection cycle configuration.
|
|
1271
|
+
|
|
1272
|
+
:param loop: Loop count of the FEC codeword error injection cycle. <loop> == 0 means continuous.
|
|
1273
|
+
:type loop: int
|
|
1274
|
+
:param cycle_len: The number of FEC codewords in the cycle, must be larger than 0 and an even number.
|
|
1275
|
+
:type cycle_len: int
|
|
1276
|
+
:param error_len: The number of consecutive errored FEC codewords in a cycle, must not be larger than cycle_len
|
|
1277
|
+
:type error_len: int
|
|
1278
|
+
"""
|
|
1083
1279
|
return Token(self._connection, build_set_request(self, module=self._module, port=self._port, loop=loop, cycle_len=cycle_len, error_len=error_len))
|
|
1084
1280
|
|
|
1085
1281
|
set_continuous = functools.partialmethod(set, 0)
|
|
@@ -1130,9 +1326,19 @@ class PL1_CWE_ERR_SYM_INDICES:
|
|
|
1130
1326
|
"""
|
|
1131
1327
|
|
|
1132
1328
|
def get(self) -> Token[GetDataAttr]:
|
|
1329
|
+
"""Get the positions of the errored symbols in errored codewords.
|
|
1330
|
+
|
|
1331
|
+
:return: The positions of the errored symbols in errored codewords
|
|
1332
|
+
:rtype: PL1_CWE_ERR_SYM_INDICES.GetDataAttr
|
|
1333
|
+
"""
|
|
1133
1334
|
return Token(self._connection, build_get_request(self, module=self._module, port=self._port))
|
|
1134
1335
|
|
|
1135
1336
|
def set(self, error_sym_indices: typing.List[int]) -> Token[None]:
|
|
1337
|
+
"""Set the positions of the errored symbols in errored codewords.
|
|
1338
|
+
|
|
1339
|
+
:param error_sym_indices: The positions of the errored symbols in errored codewords
|
|
1340
|
+
:type error_sym_indices: typing.List[int]
|
|
1341
|
+
"""
|
|
1136
1342
|
return Token(self._connection, build_set_request(self, module=self._module, port=self._port, error_sym_indices=error_sym_indices))
|
|
1137
1343
|
|
|
1138
1344
|
|
|
@@ -1163,9 +1369,21 @@ class PL1_CWE_BIT_ERR_MASK:
|
|
|
1163
1369
|
"""bit error mask for the errored symbols, big endian, only 10 bits are effective."""
|
|
1164
1370
|
|
|
1165
1371
|
def get(self) -> Token[GetDataAttr]:
|
|
1372
|
+
"""Get the bit error mask configuration.
|
|
1373
|
+
|
|
1374
|
+
:return: The bit error mask mode and bitmask
|
|
1375
|
+
:rtype: PL1_CWE_BIT_ERR_MASK.GetDataAttr
|
|
1376
|
+
"""
|
|
1166
1377
|
return Token(self._connection, build_get_request(self, module=self._module, port=self._port))
|
|
1167
1378
|
|
|
1168
1379
|
def set(self, mode: FecCodewordBitErrorMaskMode, bitmask: Hex) -> Token[None]:
|
|
1380
|
+
"""Set the bit error mask configuration.
|
|
1381
|
+
|
|
1382
|
+
:param mode: Bit error mask mode
|
|
1383
|
+
:type mode: FecCodewordBitErrorMaskMode
|
|
1384
|
+
:param bitmask: Bit error mask for the errored symbols, big endian, only 10 bits are effective
|
|
1385
|
+
:type bitmask: Hex
|
|
1386
|
+
"""
|
|
1169
1387
|
return Token(self._connection, build_set_request(self, module=self._module, port=self._port, mode=mode, bitmask=bitmask))
|
|
1170
1388
|
|
|
1171
1389
|
set_all_bits = functools.partialmethod(set, FecCodewordBitErrorMaskMode.STATIC, Hex("03FF"))
|
|
@@ -1212,9 +1430,19 @@ class PL1_CWE_FEC_ENGINE:
|
|
|
1212
1430
|
"""
|
|
1213
1431
|
|
|
1214
1432
|
def get(self) -> Token[GetDataAttr]:
|
|
1433
|
+
"""Get which FEC engines are used.
|
|
1434
|
+
|
|
1435
|
+
:return: The FEC engines bitmask
|
|
1436
|
+
:rtype: PL1_CWE_FEC_ENGINE.GetDataAttr
|
|
1437
|
+
"""
|
|
1215
1438
|
return Token(self._connection, build_get_request(self, module=self._module, port=self._port))
|
|
1216
1439
|
|
|
1217
1440
|
def set(self, bitmask: Hex) -> Token[None]:
|
|
1441
|
+
"""Set which FEC engines to use.
|
|
1442
|
+
|
|
1443
|
+
:param bitmask: FEC engines bitmask
|
|
1444
|
+
:type bitmask: Hex
|
|
1445
|
+
"""
|
|
1218
1446
|
return Token(self._connection, build_set_request(self, module=self._module, port=self._port, bitmask=bitmask))
|
|
1219
1447
|
|
|
1220
1448
|
set_all_engines = functools.partialmethod(set, Hex("0F"))
|
|
@@ -1249,6 +1477,11 @@ class PL1_CWE_FEC_STATS:
|
|
|
1249
1477
|
"""Total injected symbol errors."""
|
|
1250
1478
|
|
|
1251
1479
|
def get(self) -> Token[GetDataAttr]:
|
|
1480
|
+
"""Get FEC error injection statistics.
|
|
1481
|
+
|
|
1482
|
+
:return: FEC error injection statistics
|
|
1483
|
+
:rtype: PL1_CWE_FEC_STATS.GetDataAttr
|
|
1484
|
+
"""
|
|
1252
1485
|
|
|
1253
1486
|
return Token(self._connection, build_get_request(self, module=self._module, port=self._port))
|
|
1254
1487
|
|
|
@@ -1268,22 +1501,36 @@ class PL1_AUTONEG_CONFIG:
|
|
|
1268
1501
|
_port: int
|
|
1269
1502
|
|
|
1270
1503
|
class GetDataAttr(ResponseBodyStruct):
|
|
1271
|
-
|
|
1272
|
-
|
|
1273
|
-
|
|
1504
|
+
tech_abilities: Hex = field(XmpHex(size=8))
|
|
1505
|
+
fec_abilities: Hex = field(XmpHex(size=1))
|
|
1506
|
+
pause_mode: Hex = field(XmpHex(size=1))
|
|
1274
1507
|
|
|
1275
1508
|
class SetDataAttr(RequestBodyStruct):
|
|
1276
|
-
|
|
1277
|
-
|
|
1278
|
-
|
|
1509
|
+
tech_abilities: Hex = field(XmpHex(size=8))
|
|
1510
|
+
fec_abilities: Hex = field(XmpHex(size=1))
|
|
1511
|
+
pause_mode: Hex = field(XmpHex(size=1))
|
|
1279
1512
|
|
|
1280
1513
|
def get(self) -> Token[GetDataAttr]:
|
|
1514
|
+
"""Get the advertised technology abilities, FEC abilities, and pause abilities of the port.
|
|
1515
|
+
|
|
1516
|
+
:return: The advertised abilities
|
|
1517
|
+
:rtype: PL1_AUTONEG_CONFIG.GetDataAttr
|
|
1518
|
+
"""
|
|
1281
1519
|
|
|
1282
1520
|
return Token(self._connection, build_get_request(self, module=self._module, port=self._port))
|
|
1283
1521
|
|
|
1284
|
-
def set(self,
|
|
1522
|
+
def set(self, tech_abilities: Hex, fec_abilities: Hex, pause_mode: Hex) -> Token[None]:
|
|
1523
|
+
"""Set the advertised technology abilities, FEC abilities, and pause abilities of the port.
|
|
1285
1524
|
|
|
1286
|
-
|
|
1525
|
+
:param tech_abilities: Advertised technology abilities bitmask
|
|
1526
|
+
:type tech_abilities: Hex
|
|
1527
|
+
:param fec_abilities: Advertised FEC abilities bitmask
|
|
1528
|
+
:type fec_abilities: Hex
|
|
1529
|
+
:param pause_mode: Advertised pause mode bitmask
|
|
1530
|
+
:type pause_mode: Hex
|
|
1531
|
+
"""
|
|
1532
|
+
|
|
1533
|
+
return Token(self._connection, build_set_request(self, module=self._module, port=self._port, advertised_tech_abilities=tech_abilities, advertised_fec_abilities=fec_abilities, advertised_pause_mode=pause_mode))
|
|
1287
1534
|
|
|
1288
1535
|
@register_command
|
|
1289
1536
|
@dataclass
|
|
@@ -1345,7 +1592,16 @@ class PL1_ANLT:
|
|
|
1345
1592
|
@dataclass
|
|
1346
1593
|
class PL1_PHYTXEQ:
|
|
1347
1594
|
"""
|
|
1348
|
-
Control and monitor the equalizer settings of the on-board PHY in the transmission direction (towards the transceiver cage).
|
|
1595
|
+
Control and monitor the equalizer settings (native values) of the on-board PHY in the transmission direction (towards the transceiver cage).
|
|
1596
|
+
|
|
1597
|
+
This command returns a variable number of tap values with module-dependent ordering:
|
|
1598
|
+
|
|
1599
|
+
- **Regular Freya**: Original fixed format [pre3, pre2, pre, main, post]
|
|
1600
|
+
- **Loki-4P and H-Freya/Edun**: Variable number in N*pre, main, M*post layout
|
|
1601
|
+
[pre_n, pre_n-1, ..., pre_1, main, post_1, post_2, ..., post_m]
|
|
1602
|
+
|
|
1603
|
+
Use P_CAPABILITIES to query ``numtxeqtaps`` and ``numtxeqpretaps`` to determine
|
|
1604
|
+
the number of taps and layout.
|
|
1349
1605
|
|
|
1350
1606
|
.. note::
|
|
1351
1607
|
|
|
@@ -1362,38 +1618,48 @@ class PL1_PHYTXEQ:
|
|
|
1362
1618
|
_serdes_xindex: int
|
|
1363
1619
|
|
|
1364
1620
|
class GetDataAttr(ResponseBodyStruct):
|
|
1365
|
-
|
|
1366
|
-
"""
|
|
1367
|
-
|
|
1368
|
-
|
|
1369
|
-
|
|
1370
|
-
|
|
1371
|
-
|
|
1372
|
-
|
|
1373
|
-
post: int = field(XmpInt())
|
|
1374
|
-
"""integer, post tap value. Default = 0 (neutral)"""
|
|
1375
|
-
|
|
1621
|
+
tap_values: typing.List[int] = field(XmpSequence(types_chunk=[XmpInt()]))
|
|
1622
|
+
"""list of integers, TX EQ tap values (native values). The number and layout depend on the platform:
|
|
1623
|
+
|
|
1624
|
+
- Regular Freya: [pre3, pre2, pre, main, post]
|
|
1625
|
+
- Loki-4P and H-Freya/Edun: [pre_n, ..., pre_1, main, post_1, ..., post_m]
|
|
1626
|
+
where N = numtxeqpretaps and M = numtxeqtaps - numtxeqpretaps - 1
|
|
1627
|
+
"""
|
|
1628
|
+
|
|
1376
1629
|
class SetDataAttr(RequestBodyStruct):
|
|
1377
|
-
|
|
1378
|
-
"""
|
|
1379
|
-
|
|
1380
|
-
|
|
1381
|
-
|
|
1382
|
-
|
|
1383
|
-
|
|
1384
|
-
"""integer, main tap value."""
|
|
1385
|
-
post: int = field(XmpInt())
|
|
1386
|
-
"""integer, post tap value. Default = 0 (neutral)"""
|
|
1630
|
+
tap_values: typing.List[int] = field(XmpSequence(types_chunk=[XmpInt()]))
|
|
1631
|
+
"""list of integers, TX EQ tap values (native values). The number and layout depend on the platform:
|
|
1632
|
+
|
|
1633
|
+
- Regular Freya: [pre3, pre2, pre, main, post]
|
|
1634
|
+
- Loki-4P and H-Freya/Edun: [pre_n, ..., pre_1, main, post_1, ..., post_m]
|
|
1635
|
+
where N = numtxeqpretaps and M = numtxeqtaps - numtxeqpretaps - 1
|
|
1636
|
+
"""
|
|
1387
1637
|
|
|
1388
1638
|
def get(self) -> Token[GetDataAttr]:
|
|
1639
|
+
"""Get the TX equalizer settings (native values) of the on-board PHY.
|
|
1640
|
+
|
|
1641
|
+
The returned tap values layout depends on the platform. Query P_CAPABILITIES
|
|
1642
|
+
for ``numtxeqtaps`` and ``numtxeqpretaps`` to determine the format.
|
|
1643
|
+
|
|
1644
|
+
:return: list of TX EQ tap values (native values)
|
|
1645
|
+
:rtype: PL1_PHYTXEQ.GetDataAttr
|
|
1646
|
+
"""
|
|
1389
1647
|
|
|
1390
1648
|
return Token(self._connection, build_get_request(self, module=self._module, port=self._port, indices=[self._serdes_xindex]))
|
|
1391
1649
|
|
|
1392
|
-
def set(self,
|
|
1650
|
+
def set(self, tap_values: typing.List[int]) -> Token[None]:
|
|
1651
|
+
"""Set the TX equalizer settings (native values) of the on-board PHY.
|
|
1652
|
+
|
|
1653
|
+
The tap values layout depends on the platform. Query P_CAPABILITIES
|
|
1654
|
+
for ``numtxeqtaps`` and ``numtxeqpretaps`` to determine the required format.
|
|
1655
|
+
|
|
1656
|
+
:param tap_values: list of TX EQ tap values (native values) in platform-specific order
|
|
1657
|
+
:type tap_values: typing.List[int]
|
|
1658
|
+
"""
|
|
1393
1659
|
|
|
1394
1660
|
return Token(
|
|
1395
1661
|
self._connection,
|
|
1396
|
-
build_set_request(self, module=self._module, port=self._port, indices=[self._serdes_xindex],
|
|
1662
|
+
build_set_request(self, module=self._module, port=self._port, indices=[self._serdes_xindex], tap_values=tap_values))
|
|
1397
1663
|
|
|
1398
1664
|
@register_command
|
|
1399
1665
|
@dataclass
|
|
@@ -1418,11 +1684,23 @@ class PL1_LINKTRAIN_CONFIG:
|
|
|
1418
1684
|
timeout_mode: TimeoutMode = field(XmpByte())
|
|
1419
1685
|
|
|
1420
1686
|
def get(self) -> Token[GetDataAttr]:
|
|
1687
|
+
"""Get the current per-port link training settings.
|
|
1688
|
+
|
|
1689
|
+
:return: The current per-port link training settings
|
|
1690
|
+
:rtype: PL1_LINKTRAIN_CONFIG.GetDataAttr
|
|
1691
|
+
"""
|
|
1421
1692
|
|
|
1422
1693
|
return Token(self._connection, build_get_request(self, module=self._module, port=self._port))
|
|
1423
1694
|
|
|
1424
1695
|
def set(self, oos_preset: FreyaOutOfSyncPreset, timeout_mode: TimeoutMode) -> Token[None]:
|
|
1696
|
+
"""Set the current per-port link training settings.
|
|
1425
1697
|
|
|
1698
|
+
:param oos_preset: Out-of-sync preset value
|
|
1699
|
+
:type oos_preset: FreyaOutOfSyncPreset
|
|
1700
|
+
:param timeout_mode: Timeout mode value
|
|
1701
|
+
:type timeout_mode: TimeoutMode
|
|
1702
|
+
:return: A token indicating the completion of the set operation
|
|
1703
|
+
"""
|
|
1426
1704
|
return Token(self._connection, build_set_request(self, module=self._module, port=self._port, oos_preset=oos_preset, timeout_mode=timeout_mode))
|
|
1427
1705
|
|
|
1428
1706
|
@register_command
|
|
@@ -1480,9 +1758,20 @@ class PL1_CWE_CONTROL:
|
|
|
1480
1758
|
"""Control action for FEC codeword error injection"""
|
|
1481
1759
|
|
|
1482
1760
|
def get(self) -> Token[GetDataAttr]:
|
|
1761
|
+
"""Get the current control action for FEC codeword error injection.
|
|
1762
|
+
|
|
1763
|
+
:return: The current control action for FEC codeword error injection
|
|
1764
|
+
:rtype: PL1_CWE_CONTROL.GetDataAttr
|
|
1765
|
+
"""
|
|
1483
1766
|
return Token(self._connection, build_get_request(self, module=self._module, port=self._port))
|
|
1484
1767
|
|
|
1485
1768
|
def set(self, action: StartOrStop) -> Token[None]:
|
|
1769
|
+
"""Set the control action for FEC codeword error injection.
|
|
1770
|
+
|
|
1771
|
+
:param action: Control action for FEC codeword error injection
|
|
1772
|
+
:type action: StartOrStop
|
|
1773
|
+
:return: A token indicating the completion of the set operation
|
|
1774
|
+
"""
|
|
1486
1775
|
return Token(self._connection, build_set_request(self, module=self._module, port=self._port, action=action))
|
|
1487
1776
|
|
|
1488
1777
|
set_start = functools.partialmethod(set, StartOrStop.START)
|
|
@@ -1610,4 +1899,39 @@ class PL1_PNSWAP_RX:
|
|
|
1610
1899
|
|
|
1611
1900
|
set_off = functools.partialmethod(set, OnOff.OFF)
|
|
1612
1901
|
"""Set P/N polarity swap of the SerDes in the receiving direction to OFF
|
|
1613
|
-
"""
|
|
1902
|
+
"""
|
|
1903
|
+
|
|
1904
|
+
__all__ = [
|
|
1905
|
+
"PL1_ANLT",
|
|
1906
|
+
"PL1_AUTONEGINFO",
|
|
1907
|
+
"PL1_AUTONEG_ABILITIES",
|
|
1908
|
+
"PL1_AUTONEG_CONFIG",
|
|
1909
|
+
"PL1_AUTONEG_STATUS",
|
|
1910
|
+
"PL1_CFG_TMP",
|
|
1911
|
+
"PL1_CTRL",
|
|
1912
|
+
"PL1_CWE_BIT_ERR_MASK",
|
|
1913
|
+
"PL1_CWE_CONTROL",
|
|
1914
|
+
"PL1_CWE_CYCLE",
|
|
1915
|
+
"PL1_CWE_ERR_SYM_INDICES",
|
|
1916
|
+
"PL1_CWE_FEC_ENGINE",
|
|
1917
|
+
"PL1_CWE_FEC_STATS",
|
|
1918
|
+
"PL1_CWE_FEC_STATS_CLEAR",
|
|
1919
|
+
"PL1_GET_DATA",
|
|
1920
|
+
"PL1_LINKTRAININFO",
|
|
1921
|
+
"PL1_LINKTRAIN_CMD",
|
|
1922
|
+
"PL1_LINKTRAIN_CONFIG",
|
|
1923
|
+
"PL1_LINKTRAIN_STATUS",
|
|
1924
|
+
"PL1_LOG",
|
|
1925
|
+
"PL1_LT_PHYTXEQ_RANGE",
|
|
1926
|
+
"PL1_LT_PHYTXEQ_RANGE_COEFF",
|
|
1927
|
+
"PL1_PCS_VARIANT",
|
|
1928
|
+
"PL1_PHYTXEQ",
|
|
1929
|
+
"PL1_PHYTXEQ_COEFF",
|
|
1930
|
+
"PL1_PHYTXEQ_LEVEL",
|
|
1931
|
+
"PL1_PNSWAP_RX",
|
|
1932
|
+
"PL1_PNSWAP_TX",
|
|
1933
|
+
"PL1_PRESET_CONFIG",
|
|
1934
|
+
"PL1_PRESET_CONFIG_COEFF",
|
|
1935
|
+
"PL1_PRESET_CONFIG_LEVEL",
|
|
1936
|
+
"PL1_PRESET_RESET",
|
|
1937
|
+
]
|