tdl-xoa-driver 1.5.0b2__py3-none-any.whl → 1.6.0__py3-none-any.whl

xoa_driver/internals/hli/ports/port_l23/layer1/pcs_fec.py

@@ -0,0 +1,219 @@
+from typing import (
+    TYPE_CHECKING,
+    Tuple,
+    Union,
+    Self,
+)
+if TYPE_CHECKING:
+    from xoa_driver.internals.core import interfaces as itf
+    from xoa_driver.internals.hli.ports.port_l23.family_edun import FamilyEdun
+    from xoa_driver.internals.hli.ports.port_l23.family_freya import FamilyFreya
+    from xoa_driver.internals.hli.ports.port_l23.family_loki import FamilyLoki
+    from xoa_driver.internals.hli.ports.port_l23.family_thor import FamilyThor
+from xoa_driver.internals.commands import (
+    PP_ALARMS_ERRORS,
+    PP_TXLANECONFIG,
+    PP_TXLANEINJECT,
+    PP_TXERRORRATE,
+    PP_TXINJECTONE,
+    PP_RXTOTALSTATS,
+    PP_RXFECSTATS,
+    PP_RXLANELOCK,
+    PP_RXLANESTATUS,
+    PP_RXLANEERRORS,
+    PP_RXCLEAR,
+    PP_FECMODE,
+    PL1_CWE_CYCLE,
+    PL1_CWE_ERR_SYM_INDICES,
+    PL1_CWE_BIT_ERR_MASK,
+    PL1_CWE_FEC_ENGINE,
+    PL1_CWE_FEC_STATS,
+    PL1_CWE_CONTROL,
+    PL1_CWE_FEC_STATS_CLEAR,
+)
+from xoa_driver import enums
+
+
+class PcsAlarms:
+    """L23 high-speed port PCS/PMA alarms"""
+
+    def __init__(self, conn: "itf.IConnection", module_id: int, port_id: int) -> None:
+        self.errors = PP_ALARMS_ERRORS(conn, module_id, port_id)
+        """Error count of each alarm on a L23 high-speed port.
+
+        :type: PP_ALARMS_ERRORS
+        """
+
+
+class PcsFecLaneStatus:
+    """PCS/FEC lane status"""
+
+    def __init__(self, conn: "itf.IConnection", module_id: int, port_id: int, lane_idx: int) -> None:
+        self.errors = PP_RXLANEERRORS(conn, module_id, port_id, lane_idx)
+        """RX lane error statistics.
+
+        :type: PP_RXLANEERRORS
+        """
+
+        self.lock = PP_RXLANELOCK(conn, module_id, port_id, lane_idx)
+        """RX lane lock.
+
+        :type: PP_RXLANELOCK
+        """
+
+        self.status = PP_RXLANESTATUS(conn, module_id, port_id, lane_idx)
+        """RX lane status
+
+        :type: PP_RXLANESTATUS
+        """
+
+
+class PcsErrorGeneration:
+    """PCS/FEC TX error generation."""
+
+    def __init__(self, conn: "itf.IConnection", module_id: int, port_id: int) -> None:
+        self.error_rate = PP_TXERRORRATE(conn, module_id, port_id)
+        """The rate of continuous bit-level error injection.
+
+        :type: PP_TXERRORRATE
+        """
+
+        self.inject_one = PP_TXINJECTONE(conn, module_id, port_id)
+        """Inject a single bit-level error.
+
+        :type: PP_TXINJECTONE
+        """
+
+
+class PcsFecSymbolStatus:
+    """PCS/FEC RX symbol status"""
+
+    def __init__(self, conn: "itf.IConnection", module_id: int, port_id: int) -> None:
+        self.total_status = PP_RXTOTALSTATS(conn, module_id, port_id)
+        """RX FEC total counters.
+
+        :type: PP_RXTOTALSTATS
+        """
+
+        self.fec_status = PP_RXFECSTATS(conn, module_id, port_id)
+        """RX FEC statistics.
+
+        :type: PP_RXFECSTATS
+        """
+
+
+# class PcsPmaPhy:
+#     """L23 high-speed port PCS/PMA PHY settings."""
+
+#     def __init__(self, conn: "itf.IConnection", module_id: int, port_id: int) -> None:
+#         self.auto_neg = PP_PHYAUTONEG(conn, module_id, port_id)
+#         """ Auto-negotiation settings of the PHY.
+
+#         :type: PP_PHYAUTONEG
+#         """
+
+#         self.signal_status = PP_PHYSIGNALSTATUS(conn, module_id, port_id)
+#         """The PHY signal status.
+
+#         :type: PP_PHYSIGNALSTATUS
+#         """
+
+#         self.settings = PP_PHYSETTINGS(conn, module_id, port_id)
+#         """Low-level PHY settings
+
+#         :type: PP_PHYSETTINGS
+#         """
+
+
+class PcsLane:
+    """PCS lane configuration and status."""
+
+    def __init__(self, conn: "itf.IConnection", module_id: int, port_id: int, lane_idx: int) -> None:
+        self.rx_status = PcsFecLaneStatus(conn, module_id, port_id, lane_idx)
+        """PCS/PMA RX lane status.
+        """
+
+        self.tx_error_inject = PP_TXLANEINJECT(conn, module_id, port_id, lane_idx)
+        """Inject CAUI error into a TX lane.
+
+        :type: PP_TXLANEINJECT
+        """
+
+        self.tx_config = PP_TXLANECONFIG(conn, module_id, port_id, lane_idx)
+        """TX lane configuration.
+
+        :type: PP_TXLANECONFIG
+        """
+
+class FreyaFecCodewordErrorInject:
+    """Freya FEC Codeword Error Injection
+    """
+    def __init__(self, conn: "itf.IConnection", module_id: int, port_id: int) -> None:
+        self.cycle = PL1_CWE_CYCLE(conn, module_id, port_id)
+        """FEC codeword error injection cycle.
+        """
+        self.err_symbols = PL1_CWE_ERR_SYM_INDICES(conn, module_id, port_id)
+        """The positions of the errored symbols in errored codewords.
+        """
+        self.bit_err_mask = PL1_CWE_BIT_ERR_MASK(conn, module_id, port_id)
+        """The bit error mask for the errored symbols.
+        """
+        self.engine = PL1_CWE_FEC_ENGINE(conn, module_id, port_id)
+        """The FEC engines to use.
+        """
+        self.statistics = PL1_CWE_FEC_STATS(conn, module_id, port_id)
+        """FEC error injection statistics
+        """
+        self.clear_stats = PL1_CWE_FEC_STATS_CLEAR(conn, module_id, port_id)
+        """Clear FEC codeword injection stats
+        """
+        self.control = PL1_CWE_CONTROL(conn, module_id, port_id)
+        """Control the FEC codeword error injection
+        """
+
+class PcsLayer:
+    """PCS/FEC layer configuration and status."""
+
+    def __init__(self, conn: "itf.IConnection", port: "Union[FamilyLoki, FamilyThor, FamilyFreya, FamilyEdun]") -> None:
+        self._conn = conn
+        self.__port = port
+        module_id, port_id = port.kind
+
+        self.alarms = PcsAlarms(conn, module_id, port_id)
+        """PCS alarms
+
+        :type: PcsAlarms
+        """
+
+        self.error_gen = PcsErrorGeneration(conn, module_id, port_id)
+        """Error generation
+
+        :type: PcsPmaTxErrorGeneration
+        """
+
+        self.fec_symbol_status = PcsFecSymbolStatus(conn, module_id, port_id)
+        """Rx FEC symbol status
+
+        :type: FecSymbolStatus
+        """
+
+        self.clear = PP_RXCLEAR(conn, module_id, port_id)
+        """Clear all the PCS receiver statistics.
+
+        :type: PP_RXCLEAR
+        """
+
+        self.fec_mode = PP_FECMODE(conn, module_id, port_id)
+        """FEC mode configuration.
+
+        :type: PP_FECMODE
+        """
+
+        self.lane: Tuple["PcsLane", ...] = tuple(
+            PcsLane(self._conn, module_id, port_id, lane_idx=idx)
+            for idx in range(self.__port.info.capabilities.lane_count)
+        )  # TODO: need to fix, currently port.info.capabilities must be none because lanes are created before awaiting the port
+        """PCS Lane
+        
+        :type: Tuple[PcsLane, ...]
+        """

xoa_driver/internals/hli/ports/port_l23/layer1/pma.py

@@ -0,0 +1,43 @@
+from typing import (
+    TYPE_CHECKING,
+    Tuple,
+)
+if TYPE_CHECKING:
+    from xoa_driver.internals.core import interfaces as itf
+from xoa_driver.internals.commands import (
+    PP_PRECODING,
+    PP_GRAYCODING,
+    PL1_PNSWAP_RX,
+    PL1_PNSWAP_TX,
+)
+
+from xoa_driver import enums
+
+
+class FreyaPMA:
+    """Freya PMA"""
+
+    def __init__(self, conn: "itf.IConnection", module_id: int, port_id: int, serdes_xindex: int) -> None:
+        self.precoding = PP_PRECODING(conn, module_id, port_id, serdes_xindex)
+        """GET/SET Pre-Coding Configurations. (only for Freya)
+
+        :type: PP_PRECODING
+        """
+
+        self.graycoding = PP_GRAYCODING(conn, module_id, port_id, serdes_xindex)
+        """GET/SET Gray-Coding Configurations. (only for Freya)
+
+        :type: PP_GRAYCODING
+        """
+
+        self.pn_swap_rx = PL1_PNSWAP_RX(conn, module_id, port_id, serdes_xindex)
+        """GET/SET PN-Swap RX Configurations. (only for Freya)
+
+        :type: PL1_PNSWAP_RX
+        """
+
+        self.pn_swap_tx = PL1_PNSWAP_TX(conn, module_id, port_id, serdes_xindex)
+        """GET/SET PN-Swap TX Configurations. (only for Freya)
+        
+        :type: PL1_PNSWAP_TX
+        """

xoa_driver/internals/hli/ports/port_l23/layer1/prbs.py

@@ -0,0 +1,39 @@
+from typing import (
+    TYPE_CHECKING,
+    Tuple,
+)
+from typing import Self
+if TYPE_CHECKING:
+    from xoa_driver.internals.core import interfaces as itf
+from xoa_driver.internals.commands import (
+    PP_TXPRBSCONFIG,
+    PP_RXPRBSSTATUS,
+    PP_PRBSTYPE,
+)
+from xoa_driver import enums
+
+class PrbsConfig:
+    """L23 high-speed port PRBS configuration."""
+
+    def __init__(self, conn: "itf.IConnection", module_id: int, port_id: int) -> None:
+        self.type = PP_PRBSTYPE(conn, module_id, port_id)
+        """PRBS type used when in PRBS mode.
+
+        :type: PP_PRBSTYPE
+        """
+
+class Prbs:
+    """L23 high-speed port SerDes PRBS configuration and status."""
+
+    def __init__(self, conn: "itf.IConnection", module_id: int, port_id: int, serdes_xindex: int) -> None:
+        self.control = PP_TXPRBSCONFIG(conn, module_id, port_id, serdes_xindex)
+        """TX PRBS configuration of a SerDes.
+
+        :type: PP_TXPRBSCONFIG
+        """
+
+        self.status = PP_RXPRBSSTATUS(conn, module_id, port_id, serdes_xindex)
+        """RX PRBS status on a SerDes
+
+        :type: PP_RXPRBSSTATUS
+        """

xoa_driver/internals/hli/ports/port_l23/layer1/preamble.py

@@ -0,0 +1,25 @@
+import functools
+from typing import TYPE_CHECKING
+from xoa_driver.internals.commands import (
+    P_TXPREAMBLE_REMOVE,
+    P_RXPREAMBLE_INSERT,
+
+)
+if TYPE_CHECKING:
+    from xoa_driver.internals.core import interfaces as itf
+
+class Preamble:
+    """Preamble settings."""
+
+    def __init__(self, conn: "itf.IConnection", module_id: int, port_id: int) -> None:
+        self.tx_remove = P_TXPREAMBLE_REMOVE(conn, module_id, port_id)
+        """L23 port's removal of preamble from outgoing packets.
+        
+        :type: P_TXPREAMBLE_REMOVE
+        """
+
+        self.rx_insert = P_RXPREAMBLE_INSERT(conn, module_id, port_id)
+        """L23 port's insertion of preamble into incoming packets.
+        
+        :type: P_RXPREAMBLE_INSERT
+        """

xoa_driver/internals/hli/ports/port_l23/{fault_jkl.py → layer1/rs_fault.py}

@@ -7,8 +7,8 @@ if TYPE_CHECKING:
     from xoa_driver.internals.core import interfaces as itf
 
 
-class Fault:
-    """L23 port fault settings."""
+class RsFault:
+    """RS Fault Management"""
 
     def __init__(self, conn: "itf.IConnection", module_id: int, port_id: int) -> None:
         self.signaling = P_FAULTSIGNALING(conn, module_id, port_id)

xoa_driver/internals/hli/ports/port_l23/layer1/siv.py

@@ -0,0 +1,69 @@
+from typing import (
+    TYPE_CHECKING,
+    Tuple,
+)
+if TYPE_CHECKING:
+    from xoa_driver.internals.core import interfaces as itf
+from xoa_driver.internals.commands import (
+    PL1_CTRL,
+    PL1_GET_DATA,
+)
+from xoa_driver import enums
+
+class FreyaSIV:
+    """Freya Signal Integrity View"""
+
+    def __init__(self, conn: "itf.IConnection", module_id: int, port_id: int, serdes_xindex: int) -> None:
+        self.control = PL1_CTRL(conn, module_id, port_id, serdes_xindex, enums.Layer1Control.SAMPLED_SIGNAL_INTEGRITY_SCAN)
+        """Control SIV scan.
+
+        The Signal Integrity feature offers the equivalent of an Equivalent Time oscilloscope trace of the RX PAM4 signal (later, also PAM2). The trace is done with the A/D converter in the GTM receiver also doing the data sampling / CDR function, i.e. the trace is taken after the RX equalizer.
+
+        The HW characteristics of the Versal GTM used in Freya are: Trace length = 2000 samples, sample resolution = 7 bits 2's complement, i.e. range = -64..63.
+
+        Using the sampled eye scan feature through CLI involves two steps:
+
+        Trigger the acquisition of a trace (PL1_CTRL)
+
+        Retrieve the trace data (PL1_GET_DATA)
+
+        This command is a generic control function related to Layer 1 / SERDES. For now, only used for signal integrity scan.
+
+        :type: PL1_CTRL
+        """
+
+        self.data = PL1_GET_DATA(conn, module_id, port_id, serdes_xindex, enums.Layer1Control.SAMPLED_SIGNAL_INTEGRITY_SCAN)
+        """Get SIV scan data.
+
+        The Signal Integrity feature offers the equivalent of an Equivalent Time oscilloscope trace of the RX PAM4 signal (later, also PAM2). The trace is done with the A/D converter in the GTM receiver also doing the data sampling / CDR function, i.e. the trace is taken after the RX equalizer.
+
+        The HW characteristics of the Versal GTM used in Freya are: Trace length = 2000 samples, sample resolution = 7 bits 2’s complement, i.e. range = -64..63.
+
+        Using the sampled eye scan feature through CLI involves two steps:
+
+        Trigger the acquisition of a trace (PL1_CTRL)
+
+        Retrieve the trace data (PL1_GET_DATA)
+
+        This command is a generic function to retrieve dynamic data related to Layer 1 / SERDES. For now, only used for signal integrity scan.
+
+        For ``func==0``, sampled eye scan:
+
+        * ``result==0``: No data available.
+
+            "No data available" means that either a scan was never started, an acquisition was started and in progress, or the acquired data has become too old (e.g. older than 500 ms). The acquisition time for a trace is in the very low ms-range. If ``result==0``, ``sweep_no`` and ``age_us`` are dummy (=0), and no additional data are returned.
+
+        * ``result==1``: Data returned. In that case, the rest of the parameters apply:
+
+            ``sweep_no``: per-SERDES trace acquisition counter: 1,2,3… Each trace can be returned multiple times, to different users, within its lifetime. A new trace acquisition is triggered with the PL1_CTRL command.
+
+            ``age_us``: The “age” of the trace data in microseconds, i.e. the time from data acquisition from hardware was completed until the time the command reply data is generated.
+
+            ``value``: The rest of the reply is a set of 16 bit signed 2-complement sample values. With present hardware, the range of each sample is -64..63. In XMP scripting, each sample value is represented as two bytes, msb first.
+
+            With present implementation, 2006 sample values (4012 bytes) are returned.
+
+            The first 6 sample values are so-called “sampled levels”: <p1> <p2> < p3> <m1> <m2> <m3>
+
+        :type: PL1_GET_DATA
+        """

xoa_driver/internals/hli/ports/port_l23/layer1_edun.py

@@ -0,0 +1,103 @@
+from typing import (
+    TYPE_CHECKING,
+    Tuple,
+)
+if TYPE_CHECKING:
+    from xoa_driver.internals.core import interfaces as itf
+    from xoa_driver.internals.hli.ports.port_l23.family_edun import FamilyEdun
+from xoa_driver.internals.commands import (
+    PL1_PCS_VARIANT,
+    PP_PRBSTYPE,
+    PP_LINKTRAINSTATUS,
+)
+from .layer1.pcs_fec import PcsLayer, FreyaFecCodewordErrorInject
+from .layer1.impair import Impair
+from .layer1.prbs import Prbs
+from .layer1.pma import FreyaPMA
+from .layer1.medium import EdunMedium
+from .layer1.rs_fault import RsFault
+from .tcvr.transceiver import Transceiver
+from .layer1.anlt import AnltBasic
+from .layer1.siv import FreyaSIV
+
+
+
+class SerDesEdun:
+    """L23 high-speed port SerDes configuration and status."""
+
+    def __init__(self, conn: "itf.IConnection", module_id: int, port_id: int, serdes_xindex: int) -> None:
+
+        self.prbs = Prbs(conn, module_id, port_id, serdes_xindex)
+        """PRBS
+        :type: Prbs
+        """
+        
+        self.pma = FreyaPMA(conn, module_id, port_id, serdes_xindex)
+        """Edun PMA
+
+        :type: FreyaPMA
+        """
+
+        self.medium = EdunMedium(conn, module_id, port_id, serdes_xindex)
+        """Edun medium
+
+        :type: EdunMedium
+        """
+
+        self.lt_status = PP_LINKTRAINSTATUS(conn, module_id, port_id, serdes_xindex)
+        """LT status for Edun
+        :type: PP_LINKTRAINSTATUS
+        """
+
+        self.siv = FreyaSIV(conn, module_id, port_id, serdes_xindex)
+        """Signal Integrity
+        """
+
+class EdunPcsLayer(PcsLayer):
+    """Edun PCS and FEC configuration and status
+    """
+
+    def __init__(self, conn: "itf.IConnection", port: "FamilyEdun") -> None:
+        module_id, port_id = port.kind
+        PcsLayer.__init__(self, conn, port)
+    
+        self.pcs_variant = PL1_PCS_VARIANT(conn, module_id, port_id)
+        """PCS variant configuration
+        """
+
+        self.fec_error_inject = FreyaFecCodewordErrorInject(conn, module_id, port_id)
+        """FEC codeword error injection
+        """
+
+class Layer1:
+    def __init__(self, conn: "itf.IConnection", port: "FamilyEdun") -> None:
+        module_id, port_id = port.kind
+        self.serdes: Tuple[SerDesEdun, ...] = tuple(
+                SerDesEdun(conn, module_id, port_id, serdes_xindex=idx)
+                for idx in range(port.info.capabilities.serdes_count)
+                )
+        
+        self.impairment = Impair(conn, module_id, port_id)
+        """Impairment functions"""
+
+        self.rs_fault = RsFault(conn, module_id, port_id)
+        """RS Fault configuration and status
+        """
+
+        self.pcs_fec = EdunPcsLayer(conn, port)
+        """Edun PCS and FEC configuration and status
+        """
+
+        self.prbs_config = PP_PRBSTYPE(conn, module_id, port_id)
+        """PRBS configuration, including PRBS polynomial, invert mode, and statistic collection mode (for RX).
+        """
+
+        self.anlt = AnltBasic(conn, module_id, port_id)
+        """Edun ANLT settings
+        """
+
+        self.transceiver = Transceiver(conn, module_id, port_id)
+        """Edun Transceiver configuration and status
+        """
+        
+        

xoa_driver/internals/hli/ports/port_l23/layer1_freya.py

@@ -0,0 +1,103 @@
+from typing import (
+    TYPE_CHECKING,
+    Tuple,
+)
+if TYPE_CHECKING:
+    from xoa_driver.internals.core import interfaces as itf
+    from xoa_driver.internals.hli.ports.port_l23.family_freya import FamilyFreya
+from xoa_driver.internals.commands import (
+    PL1_PCS_VARIANT,
+    PP_PRBSTYPE,
+)
+from .layer1.prbs import Prbs
+from .layer1.impair import Impair
+from .layer1.pcs_fec import PcsLayer, FreyaFecCodewordErrorInject
+from .tcvr.transceiver import Transceiver
+from .layer1.rs_fault import RsFault
+from .layer1.medium import FreyaMedium
+from .layer1.siv import FreyaSIV
+from .layer1.pma import FreyaPMA
+from .layer1.anlt import AnltAdvanced, LinkTrainingAdvanced
+
+
+class SerDesFreya:
+    """L23 high-speed port SerDes configuration and status."""
+
+    def __init__(self, conn: "itf.IConnection", module_id: int, port_id: int, serdes_xindex: int) -> None:
+
+        self.prbs = Prbs(conn, module_id, port_id, serdes_xindex)
+        """PRBS
+        :type: Prbs
+        """
+        
+        self.pma = FreyaPMA(conn, module_id, port_id, serdes_xindex)
+        """Freya PMA
+
+        :type: FreyaPMA
+        """
+
+        self.medium = FreyaMedium(conn, module_id, port_id, serdes_xindex)
+        """Freya medium
+
+        :type: FreyaMedium
+        """
+
+        self.lt = LinkTrainingAdvanced(conn, module_id, port_id, serdes_xindex)
+        """Freya Link Training on serdes level
+
+        :type: FreyaLinkTraining
+        """
+
+        self.siv = FreyaSIV(conn, module_id, port_id, serdes_xindex)
+        """Freya Signal Integrity
+        """
+
+        
+class FreyaPcsLayer(PcsLayer):
+    """Freya PCS and FEC configuration and status
+    """
+
+    def __init__(self, conn: "itf.IConnection", port: "FamilyFreya") -> None:
+        module_id, port_id = port.kind
+        PcsLayer.__init__(self, conn, port)
+    
+        self.pcs_variant = PL1_PCS_VARIANT(conn, module_id, port_id)
+        """PCS variant configuration
+        """
+
+        self.fec_error_inject = FreyaFecCodewordErrorInject(conn, module_id, port_id)
+        """FEC codeword error injection
+        """
+    
+class Layer1:
+    def __init__(self, conn: "itf.IConnection", port: "FamilyFreya") -> None:
+        module_id, port_id = port.kind
+        self.serdes: Tuple[SerDesFreya, ...] = tuple(
+                SerDesFreya(conn, module_id, port_id, serdes_xindex=idx)
+                for idx in range(port.info.capabilities.serdes_count)
+                )
+        
+        self.impairment = Impair(conn, module_id, port_id)
+        """Impairment functions
+        """
+        
+        self.rs_fault = RsFault(conn, module_id, port_id)
+        """RS Fault configuration and status
+        """
+
+        self.pcs_fec = FreyaPcsLayer(conn, port)
+        """Freya PCS and FEC configuration and status
+        """
+
+        self.prbs_config = PP_PRBSTYPE(conn, module_id, port_id)
+        """PRBS configuration, including PRBS polynomial, invert mode, and statistic collection mode (for RX).
+        """
+
+        self.anlt = AnltAdvanced(conn, module_id, port_id)
+        """Freya port-level anlt. For per-serdes configuration and status, use serdes[x]
+        """
+        
+        self.transceiver = Transceiver(conn, module_id, port_id)
+        """Freya Transceiver configuration and status
+        """
+        

xoa_driver/internals/hli/ports/port_l23/layer1_loki.py

@@ -0,0 +1,74 @@
+from typing import (
+    TYPE_CHECKING,
+    Tuple,
+    Self,
+)
+if TYPE_CHECKING:
+    from xoa_driver.internals.core import interfaces as itf
+    from xoa_driver.internals.hli.ports.port_l23.family_loki import FamilyLoki
+from xoa_driver.internals.commands import (
+    PP_PRBSTYPE,
+)
+from .layer1.prbs import Prbs
+from .layer1.pcs_fec import PcsLayer
+from .layer1.impair import Impair
+from .layer1.medium import BasicMedium
+from .layer1.eye_diagram import EyeDiagram
+from .layer1.rs_fault import RsFault
+from .tcvr.transceiver import Transceiver
+
+class SerDesLoki:
+    """L23 high-speed port SerDes configuration and status."""
+
+    def __init__(self, conn: "itf.IConnection", module_id: int, port_id: int, serdes_xindex: int) -> None:
+
+        self.prbs = Prbs(conn, module_id, port_id, serdes_xindex)
+        """PRBS
+
+        :type: Prbs
+        """
+
+        self.medium = BasicMedium(conn, module_id, port_id, serdes_xindex)
+        """Basic medium
+
+        :type: BasicMedium
+        """
+
+        self.eye_diagram = EyeDiagram(conn, module_id, port_id, serdes_xindex)
+        """Eye diagram
+
+        :type: EyeDiagram
+        """
+    
+    def __await__(self):
+        return self._setup().__await__()
+
+    async def _setup(self) -> Self:
+        await self.eye_diagram
+        return self
+
+
+class Layer1:
+    def __init__(self, conn: "itf.IConnection", port: "FamilyLoki") -> None:
+        module_id, port_id = port.kind
+        self.serdes: Tuple[SerDesLoki, ...] = tuple(
+                SerDesLoki(conn, module_id, port_id, serdes_xindex=idx)
+                for idx in range(port.info.capabilities.serdes_count)
+                )
+        
+        self.impairment = Impair(conn, module_id, port_id)
+        """Impairment functions"""
+
+        self.rs_fault = RsFault(conn, module_id, port_id)
+        """RS Fault Management"""
+
+        self.pcs_fec = PcsLayer(conn, port)
+        """PCS/FEC layer"""
+
+        self.prbs_config = PP_PRBSTYPE(conn, module_id, port_id)
+        """PRBS configuration, including PRBS polynomial, invert mode, and statistic collection mode (for RX).
+        """
+        
+        self.transceiver = Transceiver(conn, module_id, port_id)
+        """Loki Transceiver configuration and status
+        """