tdl-xoa-driver 1.5.0b2__py3-none-any.whl → 1.6.0__py3-none-any.whl

xoa_driver/internals/hli/ports/port_l23/layer1_thor.py

@@ -0,0 +1,70 @@
+from typing import (
+    TYPE_CHECKING,
+    Tuple,
+    Self,
+)
+if TYPE_CHECKING:
+    from xoa_driver.internals.core import interfaces as itf
+    from xoa_driver.internals.hli.ports.port_l23.family_thor import FamilyThor
+from xoa_driver.internals.commands import (
+    PP_PRBSTYPE,
+    PP_LINKTRAINSTATUS,
+)
+from .layer1.prbs import Prbs
+from .layer1.pcs_fec import PcsLayer
+from .layer1.impair import Impair
+from .layer1.medium import BasicMedium
+from .layer1.rs_fault import RsFault
+from .layer1.anlt import AnltBasic
+from .tcvr.transceiver import Transceiver
+
+class SerDesThor:
+    """L23 high-speed port SerDes configuration and status."""
+
+    def __init__(self, conn: "itf.IConnection", module_id: int, port_id: int, serdes_xindex: int) -> None:
+
+        self.prbs = Prbs(conn, module_id, port_id, serdes_xindex)
+        """PRBS
+
+        :type: Prbs
+        """
+
+        self.medium = BasicMedium(conn, module_id, port_id, serdes_xindex)
+        """Basic medium
+
+        :type: BasicMedium
+        """
+
+        self.lt_status = PP_LINKTRAINSTATUS(conn, module_id, port_id, serdes_xindex)
+        """LT status for Edun
+        :type: PP_LINKTRAINSTATUS
+        """
+
+class Layer1:
+    def __init__(self, conn: "itf.IConnection", port: "FamilyThor") -> None:
+        module_id, port_id = port.kind
+        self.serdes: Tuple[SerDesThor, ...] = tuple(
+                SerDesThor(conn, module_id, port_id, serdes_xindex=idx)
+                for idx in range(port.info.capabilities.serdes_count)
+                )
+        
+        self.impairment = Impair(conn, module_id, port_id)
+        """Impairment functions"""
+
+        self.rs_fault = RsFault(conn, module_id, port_id)
+        """RS Fault Management"""
+
+        self.pcs_fec = PcsLayer(conn, port)
+        """PCS/FEC layer"""
+
+        self.prbs_config = PP_PRBSTYPE(conn, module_id, port_id)
+        """PRBS configuration, including PRBS polynomial, invert mode, and statistic collection mode (for RX).
+        """
+        
+        self.anlt = AnltBasic(conn, module_id, port_id)
+        """Thor ANLT settings
+        """
+        
+        self.transceiver = Transceiver(conn, module_id, port_id)
+        """Thor Transceiver configuration and status
+        """        

xoa_driver/internals/hli/ports/port_l23/port_l23ve.py

@@ -1,7 +1,7 @@
 from typing import TYPE_CHECKING
-from .bases.port_l23 import BasePortL23
-from .bases.port_reception_statistics import PortReceptionStatistics
-from .bases.port_transmission_statistics import PortTransmissionStatistics
+from .trafficgen.port_l23 import BasePortL23
+from .trafficgen.port_rx_stats import PortReceptionStatistics
+from .trafficgen.port_tx_stats import PortTxStats
 
 from xoa_driver.internals.commands import (
     P_MDIXMODE,
@@ -36,7 +36,7 @@ class L23VEPortStatistics:
         :type: PortReceptionStatistics
         """
 
-        self.tx = PortTransmissionStatistics(conn, module_id, port_id)
+        self.tx = PortTxStats(conn, module_id, port_id)
         """L23 VE port's TX statistics.
         
         :type: PortTransmissionStatistics

xoa_driver/internals/hli/ports/port_l23/sec/macsec.py

@@ -0,0 +1,108 @@
+import functools
+from typing import TYPE_CHECKING
+if TYPE_CHECKING:
+    from xoa_driver.internals.core import interfaces as itf
+from xoa_driver.internals.commands import (
+    P_MACSEC_RX_ENABLE,
+    P_MACSEC_TX_STATS,
+    P_MACSEC_TX_CLEAR,
+    P_MACSEC_RX_STATS,
+    P_MACSEC_RX_CLEAR,
+)
+from xoa_driver.internals.utils import attributes as utils
+from xoa_driver.internals.utils.indices import index_manager as idx_mgr
+from xoa_driver.internals.hli.indices.macsecscs.genuine_macsecsc import GenuineMacSecTxScIdx, GenuineMacSecRxScIdx
+
+MacSecTxScIndices = idx_mgr.IndexManager[GenuineMacSecTxScIdx]
+MacSecRxScIndices = idx_mgr.IndexManager[GenuineMacSecRxScIdx]
+
+class MACSecTxStats:
+    """MACSec TX SC Statistics"""
+    def __init__(self, conn: "itf.IConnection", module_id: int, port_id: int) -> None:
+
+        self.total = P_MACSEC_TX_STATS(conn, module_id, port_id)
+        """Port's total MACsec TX statistics
+
+        :type: P_MACSEC_TX_STATS
+        """
+
+        self.clear = P_MACSEC_TX_CLEAR(conn, module_id, port_id)
+        """Clear Port's MACsec TX statistics
+
+        :type: P_MACSEC_TX_CLEAR
+        """
+
+class MACSecRxStats:
+    """MACSec RX SC Statistics"""
+    def __init__(self, conn: "itf.IConnection", module_id: int, port_id: int) -> None:
+
+        self.total = P_MACSEC_RX_STATS(conn, module_id, port_id)
+        """Port's total MACsec RX statistics
+
+        :type: P_MACSEC_RX_STATS
+        """
+
+        self.clear = P_MACSEC_RX_CLEAR(conn, module_id, port_id)
+        """Clear Port's MACsec RX statistics
+
+        :type: P_MACSEC_RX_CLEAR
+        """
+
+class MacSecPortStats:
+    """MACSec Port Statistics"""
+
+    def __init__(self, conn: "itf.IConnection", module_id: int, port_id: int) -> None:
+        self.tx = MACSecTxStats(conn, module_id, port_id)
+        """L23 port's MACsec TX statistics.
+
+        :type: MACSecTxStats
+        """
+
+        self.rx = MACSecRxStats(conn, module_id, port_id)
+        """L23 port's MACsec RX statistics.
+
+        :type: MACSecRxStats
+        """
+
+
+class MacSec:
+    """MACsec configuration and status."""
+
+    def __init__(self, conn: "itf.IConnection", module_id: int, port_id: int) -> None:
+        self.txscs: MacSecTxScIndices = idx_mgr.IndexManager(
+            conn,
+            GenuineMacSecTxScIdx,
+            module_id,
+            port_id
+        )
+        """MACSec TX SC index manager.
+
+        :type: MacSecTxScIndices
+        """
+
+        self.rxscs: MacSecRxScIndices = idx_mgr.IndexManager(
+            conn,
+            GenuineMacSecRxScIdx,
+            module_id,
+            port_id
+        )
+        """MACSec RX SC index manager.
+
+        :type: MacSecRxScIndices
+        """
+
+        self.decode = P_MACSEC_RX_ENABLE(conn, module_id, port_id)
+        """L23 port MACSec RX enable.
+
+        :type: P_MACSEC_RX_ENABLE        
+        """
+
+        self.statistics = MacSecPortStats(conn, module_id, port_id)
+        """L23 port MACSec statistics.
+        
+        :type: MacSecPortStats
+        """
+
+        on_macsec_rx_enable_change = functools.partialmethod(utils.on_event, P_MACSEC_RX_ENABLE)
+        """Register a callback to the event that the port MACsec RX enable status changes."""
+        

xoa_driver/internals/hli/ports/port_l23/{bases/port_transceiver.py → tcvr/cmis.py}

@@ -2,12 +2,6 @@ from typing import TYPE_CHECKING
 if TYPE_CHECKING:
     from xoa_driver.internals.core import interfaces as itf
 from xoa_driver.internals.commands import (
-    PX_RW,
-    PX_MII,
-    PX_TEMPERATURE,
-    PX_RW_SEQ,
-    PX_I2C_CONFIG,
-    PX_RW_SEQ_BANK,
     PX_CDB_SUPPORT,
     PX_CDB_ABORT_PROCESSING,
     PX_CDB_CHANGE_PASSWORD,
@@ -33,115 +27,7 @@ from xoa_driver.internals.commands import (
     PX_CUST_CMD,
 )
 
-
-class PortTransceiver:
-    """Transceiver access class."""
-
-    def __init__(self, conn: "itf.IConnection", module_id: int, port_id: int) -> None:
-        self.__conn = conn
-        self.__module_id = module_id
-        self.__port_id = port_id
-
-        self.i2c_config = PX_I2C_CONFIG(conn, module_id, port_id)
-        """
-        Access speed on a transceiver I2C access in the unit of KHz. Default to 100. 
-        
-        When the transceiver is plugged out and in again, the speed will be reset to the default value 100. The speed has a minimum and a maximum, which can be obtained from port.capabilities(). 
-        
-        The I2C speed configuration will not be included in the port configuration file (.xpc). When you load a port configuration to a port, the transceiver I2C access speed will be reset to default.
-        """
-
-        self.temperature = PX_TEMPERATURE(conn, module_id, port_id)
-        """Transceiver temperature in Celsius.
-
-        Temperature value before the decimal digit, and 1/256th of a degree Celsius after the decimal digit.
-        """
-
-        self.cmis = CMIS(conn, module_id, port_id)
-        """
-        Access CMIS interface.
-        """
-
-    def access_rw(self, page_address: int, register_address: int) -> "PX_RW":
-        """Access to register interface by the transceiver.
-
-        :param page_address: page address
-        :type page_address: int
-        :param register_address: register address
-        :type register_address: int
-        :return: transceiver register values
-        :rtype: PX_RW
-        """
-
-        return PX_RW(
-            self.__conn,
-            self.__module_id,
-            self.__port_id,
-            page_address,
-            register_address
-        )
-
-    def access_mii(self, register_address: int) -> "PX_MII":
-        """Access to the register interface supported by the media-independent interface (MII) transceiver.
-
-        :param register_address: register address
-        :type register_address: int
-        :return: register values
-        :rtype: PX_MII
-        """
-        return PX_MII(
-            self.__conn,
-            self.__module_id,
-            self.__port_id,
-            register_address
-        )
-
-    def access_rw_seq(self, page_address: int, register_address: int, byte_count: int) -> "PX_RW_SEQ":
-        """Sequential read/write a number of bytes to the register interface supported by the media-independent interface (MII) transceiver.
-
-        :param page_address: page address (0-255)
-        :type page_address: int
-        :param register_address: register address (0-255)
-        :type register_address: int
-        :param byte_count: the number of bytes to read/write
-        :type byte_count: int
-        :return: transceiver register values
-        :rtype: PX_RW_SEQ
-        """
-        return PX_RW_SEQ(
-            self.__conn,
-            self.__module_id,
-            self.__port_id,
-            page_address,
-            register_address,
-            byte_count
-        )
-    
-    def access_rw_seq_bank(self, bank_address: int, page_address: int, register_address: int, byte_count: int) -> "PX_RW_SEQ_BANK":
-        """Sequential read/write a number of bytes to the register interface supported by the media-independent interface (MII) transceiver.
-
-        :param bank_address: bank address (0-255)
-        :type bank_address: int
-        :param page_address: page address (0-255)
-        :type page_address: int
-        :param register_address: register address (0-255)
-        :type register_address: int
-        :param byte_count: the number of bytes to read/write
-        :type byte_count: int
-        :return: transceiver register values
-        :rtype: PX_RW_SEQ_BANK
-        """
-        return PX_RW_SEQ_BANK(
-            self.__conn,
-            self.__module_id,
-            self.__port_id,
-            bank_address,
-            page_address,
-            register_address,
-            byte_count
-        )
-
-class CMIS():
+class Cmis():
     """CMIS access class.
     """
     def __init__(self, conn: "itf.IConnection", module_id: int, port_id: int) -> None:
@@ -153,16 +39,16 @@ class CMIS():
         """Return the number of supported CDB instances.
         """
 
-    def cdb(self, cdb_instance_id: int) -> "CDB":
+    def cdb(self, cdb_instance_id: int) -> "Cbd":
         """Access CMIS CDB command interface.
 
         :param cdb_instance_id: 0 for CDB Instance 1, 1 for CDB Instance 2
         :type cdb_instance_id: int
         """
-        return CDB(self.__conn, self.__module_id, self.__port_id, cdb_instance_id)
+        return Cbd(self.__conn, self.__module_id, self.__port_id, cdb_instance_id)
         
 
-class CDB():
+class Cbd():
     """CMIS CDB command access class.
     """
     def __init__(self, conn: "itf.IConnection", module_id: int, port_id: int, cdb_instance_id: int) -> None:

xoa_driver/internals/hli/ports/port_l23/tcvr/transceiver.py

@@ -0,0 +1,124 @@
+from typing import TYPE_CHECKING
+if TYPE_CHECKING:
+    from xoa_driver.internals.core import interfaces as itf
+from xoa_driver.internals.commands import (
+    PX_RW,
+    PX_MII,
+    PX_TEMPERATURE,
+    PX_RW_SEQ,
+    PX_I2C_CONFIG,
+    PX_RW_SEQ_BANK,
+)
+from xoa_driver.internals.hli.ports.port_l23.layer1.laser_power import LaserPower
+from xoa_driver.internals.hli.ports.port_l23.tcvr.cmis import Cmis
+
+
+class Transceiver:
+    """Transceiver access class."""
+
+    def __init__(self, conn: "itf.IConnection", module_id: int, port_id: int) -> None:
+        self.__conn = conn
+        self.__module_id = module_id
+        self.__port_id = port_id
+
+        self.i2c_config = PX_I2C_CONFIG(conn, module_id, port_id)
+        """
+        Access speed on a transceiver I2C access in the unit of KHz. Default to 100. 
+        
+        When the transceiver is plugged out and in again, the speed will be reset to the default value 100. The speed has a minimum and a maximum, which can be obtained from port.capabilities(). 
+        
+        The I2C speed configuration will not be included in the port configuration file (.xpc). When you load a port configuration to a port, the transceiver I2C access speed will be reset to default.
+        """
+
+        self.temperature = PX_TEMPERATURE(conn, module_id, port_id)
+        """Transceiver temperature in Celsius.
+
+        Temperature value before the decimal digit, and 1/256th of a degree Celsius after the decimal digit.
+        """
+
+        self.laser_power = LaserPower(conn, module_id, port_id)
+        """Laser power status.
+        """
+
+        self.cmis = Cmis(conn, module_id, port_id)
+        """CMIS transceiver configuration and status
+        """
+
+    def access_rw(self, page_address: int, register_address: int) -> "PX_RW":
+        """Access to register interface by the transceiver.
+
+        :param page_address: page address
+        :type page_address: int
+        :param register_address: register address
+        :type register_address: int
+        :return: transceiver register values
+        :rtype: PX_RW
+        """
+
+        return PX_RW(
+            self.__conn,
+            self.__module_id,
+            self.__port_id,
+            page_address,
+            register_address
+        )
+
+    def access_mii(self, register_address: int) -> "PX_MII":
+        """Access to the register interface supported by the media-independent interface (MII) transceiver.
+
+        :param register_address: register address
+        :type register_address: int
+        :return: register values
+        :rtype: PX_MII
+        """
+        return PX_MII(
+            self.__conn,
+            self.__module_id,
+            self.__port_id,
+            register_address
+        )
+
+    def access_rw_seq(self, page_address: int, register_address: int, byte_count: int) -> "PX_RW_SEQ":
+        """Sequential read/write a number of bytes to the register interface supported by the media-independent interface (MII) transceiver.
+
+        :param page_address: page address (0-255)
+        :type page_address: int
+        :param register_address: register address (0-255)
+        :type register_address: int
+        :param byte_count: the number of bytes to read/write
+        :type byte_count: int
+        :return: transceiver register values
+        :rtype: PX_RW_SEQ
+        """
+        return PX_RW_SEQ(
+            self.__conn,
+            self.__module_id,
+            self.__port_id,
+            page_address,
+            register_address,
+            byte_count
+        )
+    
+    def access_rw_seq_bank(self, bank_address: int, page_address: int, register_address: int, byte_count: int) -> "PX_RW_SEQ_BANK":
+        """Sequential read/write a number of bytes to the register interface supported by the media-independent interface (MII) transceiver.
+
+        :param bank_address: bank address (0-255)
+        :type bank_address: int
+        :param page_address: page address (0-255)
+        :type page_address: int
+        :param register_address: register address (0-255)
+        :type register_address: int
+        :param byte_count: the number of bytes to read/write
+        :type byte_count: int
+        :return: transceiver register values
+        :rtype: PX_RW_SEQ_BANK
+        """
+        return PX_RW_SEQ_BANK(
+            self.__conn,
+            self.__module_id,
+            self.__port_id,
+            bank_address,
+            page_address,
+            register_address,
+            byte_count
+        )

xoa_driver/internals/hli/ports/port_l23/{bases → trafficgen}/port_l23.py

@@ -337,7 +337,7 @@ class BasePortL23(base_port.BasePort[ports_state.PortL23LocalState]):
     def __init__(self, conn: "itf.IConnection", module_id: int, port_id: int) -> None:
         super().__init__(conn, module_id, port_id)
         self.capabilities = P_CAPABILITIES(conn, module_id, port_id)
-        """L23 port capabilities.
+        """L23 Port capabilities
 
         :type: P_CAPABILITIES
         """

xoa_driver/internals/hli/ports/port_l23/{bases → trafficgen}/port_l23_genuine.py

@@ -12,7 +12,6 @@ from xoa_driver.internals.commands import (
     P_TCVRSTATUS,
     P_LOADMODE,
     PP_FECMODE,
-    P_MACSEC_RX_ENABLE
 )
 from xoa_driver.internals.utils import attributes as utils
 from xoa_driver.internals.utils.indices import index_manager as idx_mgr
@@ -20,7 +19,6 @@ from xoa_driver.internals.hli.indices.streams.genuine_stream import GenuineStrea
 from xoa_driver.internals.hli.indices.filter.genuine_filter import GenuineFilterIdx
 from xoa_driver.internals.hli.indices.port_dataset import PortDatasetIdx
 from xoa_driver.internals.state_storage import ports_state
-from xoa_driver.internals.hli.indices.macsecscs.genuine_macsecsc import GenuineMacSecTxScIdx, GenuineMacSecRxScIdx
 
 from .port_l23 import (
     BasePortL23,
@@ -28,15 +26,13 @@ from .port_l23 import (
     # TxConfiguration,
 )
 
-from .port_transceiver import PortTransceiver
-from .port_reception_statistics import GenuinePortReceptionStatistics
-from .port_transmission_statistics import GenuinePortTransmissionStatistics
+from ..tcvr.transceiver import Transceiver
+from .port_rx_stats import GenuinePortReceptionStatistics
+from .port_tx_stats import GenuinePortTransmissionStatistics
 
 StreamIndices = idx_mgr.IndexManager[GenuineStreamIdx]
 FilterIndices = idx_mgr.IndexManager[GenuineFilterIdx]
 PortDatasetIndices = idx_mgr.IndexManager[PortDatasetIdx]
-MacSecTxScIndices = idx_mgr.IndexManager[GenuineMacSecTxScIdx]
-MacSecRxScIndices = idx_mgr.IndexManager[GenuineMacSecRxScIdx]
 
 class SpeedMode:
     """L23 port's speed mode"""
@@ -122,12 +118,6 @@ class BasePortL23Genuine(BasePortL23):
         :type: P_TCVRSTATUS
         """
 
-        self.fec_mode = PP_FECMODE(conn, module_id, port_id)
-        """L23 port FEC mode.
-
-        :type: PP_FECMODE
-        """
-
         self.speed = GenuineSpeed(conn, module_id, port_id)
         """L23 port speed configuration.
 
@@ -140,7 +130,7 @@ class BasePortL23Genuine(BasePortL23):
         :type: UnAvailableTime
         """
 
-        self.transceiver = PortTransceiver(conn, module_id, port_id)
+        self.transceiver = Transceiver(conn, module_id, port_id)
         """L23 port transceiver configuration.
 
         :type: PortTransceiver
@@ -152,12 +142,6 @@ class BasePortL23Genuine(BasePortL23):
         :type: PortStatistics
         """
 
-        self.macsec_rx = P_MACSEC_RX_ENABLE(conn, module_id, port_id)
-        """L23 port MACSec RX enable.
-
-        :type: P_MACSEC_RX_ENABLE        
-        """
-
         self.streams: StreamIndices = idx_mgr.IndexManager(
             conn,
             GenuineStreamIdx,
@@ -191,27 +175,6 @@ class BasePortL23Genuine(BasePortL23):
         :type: PortDatasetIndices
         """
 
-        self.macsec_txscs: MacSecTxScIndices = idx_mgr.IndexManager(
-            conn,
-            GenuineMacSecTxScIdx,
-            module_id,
-            port_id
-        )
-        """L23 port MACSec TX SC index manager.
-
-        :type: MacSecTxScIndices
-        """
-
-        self.macsec_rxscs: MacSecRxScIndices = idx_mgr.IndexManager(
-            conn,
-            GenuineMacSecRxScIdx,
-            module_id,
-            port_id
-        )
-        """L23 port MACSec RX SC index manager.
-
-        :type: MacSecRxScIndices
-        """
 
     @property
     def info(self) -> ports_state.PortL23GenuineLocalState:
@@ -223,7 +186,4 @@ class BasePortL23Genuine(BasePortL23):
         return self
 
     on_speed_selection_change = functools.partialmethod(utils.on_event, P_SPEEDSELECTION)
-    """Register a callback to the event that the port's speed mode changes."""
-
-    on_macsec_rx_enable_change = functools.partialmethod(utils.on_event, P_MACSEC_RX_ENABLE)
-    """Register a callback to the event that the port MACsec RX enable status changes."""
+    """Register a callback to the event that the port's speed mode changes."""

xoa_driver/internals/hli/ports/port_l23/{bases/port_reception_statistics.py → trafficgen/port_rx_stats.py}

@@ -25,8 +25,6 @@ from xoa_driver.internals.commands import (
     PR_CALIBRATE,
     PR_UAT_STATUS,
     PR_UAT_TIME,
-    P_MACSEC_RX_STATS,
-    P_MACSEC_RX_CLEAR
 
 )
 
@@ -190,22 +188,6 @@ class GPrsUat():
         """
 
 
-class MACSecRxStats:
-    """MACSec RX SC Statistics"""
-    def __init__(self, conn: "itf.IConnection", module_id: int, port_id: int) -> None:
-
-        self.total = P_MACSEC_RX_STATS(conn, module_id, port_id)
-        """Port's total MACsec RX statistics
-
-        :type: P_MACSEC_RX_STATS
-        """
-
-        self.clear = P_MACSEC_RX_CLEAR(conn, module_id, port_id)
-        """Clear Port's MACsec RX statistics
-
-        :type: P_MACSEC_RX_CLEAR
-        """
-
 
 class GenuinePortReceptionStatistics(PortReceptionStatistics):
     """L23 port RX statistics."""
@@ -224,8 +206,5 @@ class GenuinePortReceptionStatistics(PortReceptionStatistics):
         :type: GPrsUat
         """
 
-        self.macsec = MACSecRxStats(conn, module_id, port_id)
-        """L23 port's MACsec RX statistics.
-        """
 
 # endregion

xoa_driver/internals/hli/ports/port_l23/{bases/port_transmission_statistics.py → trafficgen/port_tx_stats.py}

@@ -14,13 +14,11 @@ from xoa_driver.internals.commands import (
     PT_TOTALEXT,
     PT_NOTPLDEXT,
     PT_STREAMEXT,
-    P_MACSEC_TX_STATS,
-    P_MACSEC_TX_CLEAR,
 )
 
 # region All Ports
 
-class PortTransmissionStatistics:
+class PortTxStats:
     """L23 port TX statistics"""
 
     def __init__(self, conn: "itf.IConnection", module_id: int, port_id: int) -> None:
@@ -101,31 +99,13 @@ class PortTransmissionStatistics:
 
 # region Genuine Ports
 
-class MACSecTxStats:
-    """MACSec TX SC Statistics"""
-    def __init__(self, conn: "itf.IConnection", module_id: int, port_id: int) -> None:
-
-        self.total = P_MACSEC_TX_STATS(conn, module_id, port_id)
-        """Port's total MACsec TX statistics
-
-        :type: P_MACSEC_TX_STATS
-        """
 
-        self.clear = P_MACSEC_TX_CLEAR(conn, module_id, port_id)
-        """Clear Port's MACsec TX statistics
 
-        :type: P_MACSEC_TX_CLEAR
-        """
-
-
-class GenuinePortTransmissionStatistics(PortTransmissionStatistics):
+class GenuinePortTransmissionStatistics(PortTxStats):
     """L23 port RX statistics."""
 
     def __init__(self, conn: "itf.IConnection", module_id: int, port_id: int) -> None:
         super().__init__(conn, module_id, port_id)
 
-        self.macsec = MACSecTxStats(conn, module_id, port_id)
-        """L23 port's MACsec TX statistics.
-        """
 
 # endregion