tdl-xoa-driver 1.5.0b2__py3-none-any.whl → 1.6.0__py3-none-any.whl

This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
Files changed (111) hide show
  1. {tdl_xoa_driver-1.5.0b2.dist-info → tdl_xoa_driver-1.6.0.dist-info}/METADATA +8 -8
  2. {tdl_xoa_driver-1.5.0b2.dist-info → tdl_xoa_driver-1.6.0.dist-info}/RECORD +91 -89
  3. xoa_driver/__init__.py +2 -2
  4. xoa_driver/enums.py +10 -10
  5. xoa_driver/functions/anlt.py +60 -78
  6. xoa_driver/functions/cli/__init__.py +5 -5
  7. xoa_driver/functions/cli/port_config.py +16 -7
  8. xoa_driver/functions/cli/{test_case_config.py → testbed_config.py} +53 -46
  9. xoa_driver/functions/cmis/_replies.py +4 -4
  10. xoa_driver/functions/mgmt.py +206 -250
  11. xoa_driver/functions/tools.py +11 -6
  12. xoa_driver/internals/commands/c_commands.py +59 -0
  13. xoa_driver/internals/commands/enums.py +101 -90
  14. xoa_driver/internals/commands/m4_commands.py +25 -0
  15. xoa_driver/internals/commands/m4e_commands.py +6 -0
  16. xoa_driver/internals/commands/m_commands.py +51 -1
  17. xoa_driver/internals/commands/p4_commands.py +63 -1
  18. xoa_driver/internals/commands/p4e_commands.py +9 -0
  19. xoa_driver/internals/commands/p4g_commands.py +139 -0
  20. xoa_driver/internals/commands/p_commands.py +493 -63
  21. xoa_driver/internals/commands/pc_commands.py +9 -0
  22. xoa_driver/internals/commands/pd_commands.py +11 -0
  23. xoa_driver/internals/commands/pe_commands.py +27 -0
  24. xoa_driver/internals/commands/pec_commands.py +9 -0
  25. xoa_driver/internals/commands/ped_commands.py +23 -0
  26. xoa_driver/internals/commands/pef_commands.py +43 -0
  27. xoa_driver/internals/commands/pf_commands.py +11 -0
  28. xoa_driver/internals/commands/pl1_commands.py +442 -118
  29. xoa_driver/internals/commands/pl_commands.py +8 -0
  30. xoa_driver/internals/commands/pm_commands.py +11 -0
  31. xoa_driver/internals/commands/pp_commands.py +128 -82
  32. xoa_driver/internals/commands/pr_commands.py +25 -0
  33. xoa_driver/internals/commands/ps_commands.py +47 -1
  34. xoa_driver/internals/commands/pt_commands.py +15 -0
  35. xoa_driver/internals/commands/px_commands.py +180 -136
  36. xoa_driver/internals/commands/subtypes.py +4 -3
  37. xoa_driver/internals/core/transporter/protocol/payload/base_struct.py +1 -1
  38. xoa_driver/internals/hli/indices/macsecscs/base_macsecsc.py +41 -3
  39. xoa_driver/internals/hli/modules/modules_l23/family_combi.py +0 -64
  40. xoa_driver/internals/hli/modules/modules_l23/family_edun.py +0 -2
  41. xoa_driver/internals/hli/modules/modules_l23/{family_g.py → family_loki.py} +29 -1
  42. xoa_driver/internals/hli/modules/modules_l23/family_odin.py +412 -0
  43. xoa_driver/internals/hli/modules/modules_l23/{family_l.py → family_thor.py} +44 -0
  44. xoa_driver/internals/hli/ports/port_l23/chimera/port_chimera.py +3 -3
  45. xoa_driver/internals/hli/ports/port_l23/family_edun.py +9 -44
  46. xoa_driver/internals/hli/ports/port_l23/{family_l1.py → family_freya.py} +10 -45
  47. xoa_driver/internals/hli/ports/port_l23/{family_g.py → family_loki.py} +33 -32
  48. xoa_driver/internals/hli/ports/port_l23/family_odin.py +225 -0
  49. xoa_driver/internals/hli/ports/port_l23/family_thor.py +67 -0
  50. xoa_driver/internals/hli/ports/port_l23/layer1/anlt.py +512 -0
  51. xoa_driver/internals/hli/ports/port_l23/layer1/brr.py +26 -0
  52. xoa_driver/internals/hli/ports/port_l23/layer1/eye_diagram.py +71 -0
  53. xoa_driver/internals/hli/ports/port_l23/{pcs_pma_ijkl_chimera.py → layer1/impair.py} +7 -7
  54. xoa_driver/internals/hli/ports/port_l23/layer1/laser_power.py +28 -0
  55. xoa_driver/internals/hli/ports/port_l23/{family_e.py → layer1/lower_power.py} +1 -51
  56. xoa_driver/internals/hli/ports/port_l23/{freya_l1.py → layer1/medium.py} +38 -358
  57. xoa_driver/internals/hli/ports/port_l23/layer1/pcs_fec.py +219 -0
  58. xoa_driver/internals/hli/ports/port_l23/layer1/pma.py +43 -0
  59. xoa_driver/internals/hli/ports/port_l23/layer1/prbs.py +39 -0
  60. xoa_driver/internals/hli/ports/port_l23/layer1/preamble.py +25 -0
  61. xoa_driver/internals/hli/ports/port_l23/{fault_jkl.py → layer1/rs_fault.py} +2 -2
  62. xoa_driver/internals/hli/ports/port_l23/layer1/siv.py +69 -0
  63. xoa_driver/internals/hli/ports/port_l23/layer1_edun.py +103 -0
  64. xoa_driver/internals/hli/ports/port_l23/layer1_freya.py +103 -0
  65. xoa_driver/internals/hli/ports/port_l23/layer1_loki.py +74 -0
  66. xoa_driver/internals/hli/ports/port_l23/layer1_thor.py +70 -0
  67. xoa_driver/internals/hli/ports/port_l23/port_l23ve.py +4 -4
  68. xoa_driver/internals/hli/ports/port_l23/sec/__init__.py +0 -0
  69. xoa_driver/internals/hli/ports/port_l23/sec/macsec.py +108 -0
  70. xoa_driver/internals/hli/ports/port_l23/tcvr/__init__.py +0 -0
  71. xoa_driver/internals/hli/ports/port_l23/{bases/port_transceiver.py → tcvr/cmis.py} +4 -118
  72. xoa_driver/internals/hli/ports/port_l23/tcvr/transceiver.py +124 -0
  73. xoa_driver/internals/hli/ports/port_l23/trafficgen/__init__.py +0 -0
  74. xoa_driver/internals/hli/ports/port_l23/{bases → trafficgen}/port_l23.py +1 -1
  75. xoa_driver/internals/hli/ports/port_l23/{bases → trafficgen}/port_l23_genuine.py +5 -45
  76. xoa_driver/internals/hli/ports/port_l23/{bases/port_reception_statistics.py → trafficgen/port_rx_stats.py} +0 -21
  77. xoa_driver/internals/hli/ports/port_l23/{bases/port_transmission_statistics.py → trafficgen/port_tx_stats.py} +2 -22
  78. xoa_driver/internals/hli/ports/port_l23/trafficgen/runt.py +32 -0
  79. xoa_driver/internals/hli/testers/l23_tester.py +1 -3
  80. xoa_driver/internals/utils/indices/_interfaces.py +18 -6
  81. xoa_driver/internals/utils/indices/index_manager.py +8 -2
  82. xoa_driver/internals/utils/managers/ports_manager.py +5 -2
  83. xoa_driver/misc.py +6 -6
  84. xoa_driver/modules.py +31 -47
  85. xoa_driver/ports.py +10 -29
  86. xoa_driver/internals/hli/modules/modules_l23/family_d.py +0 -75
  87. xoa_driver/internals/hli/modules/modules_l23/family_e.py +0 -85
  88. xoa_driver/internals/hli/modules/modules_l23/family_f.py +0 -145
  89. xoa_driver/internals/hli/modules/modules_l23/family_h.py +0 -40
  90. xoa_driver/internals/hli/modules/modules_l23/family_i.py +0 -25
  91. xoa_driver/internals/hli/modules/modules_l23/family_j.py +0 -25
  92. xoa_driver/internals/hli/modules/modules_l23/family_k.py +0 -39
  93. xoa_driver/internals/hli/modules/modules_l23/family_m.py +0 -25
  94. xoa_driver/internals/hli/modules/modules_l23/family_n.py +0 -40
  95. xoa_driver/internals/hli/ports/port_l23/family_combi.py +0 -37
  96. xoa_driver/internals/hli/ports/port_l23/family_d.py +0 -51
  97. xoa_driver/internals/hli/ports/port_l23/family_f.py +0 -151
  98. xoa_driver/internals/hli/ports/port_l23/family_h.py +0 -67
  99. xoa_driver/internals/hli/ports/port_l23/family_i.py +0 -84
  100. xoa_driver/internals/hli/ports/port_l23/family_j.py +0 -68
  101. xoa_driver/internals/hli/ports/port_l23/family_k.py +0 -73
  102. xoa_driver/internals/hli/ports/port_l23/family_l.py +0 -82
  103. xoa_driver/internals/hli/ports/port_l23/family_m.py +0 -29
  104. xoa_driver/internals/hli/ports/port_l23/pcs_pma_ghijkl.py +0 -369
  105. xoa_driver/internals/hli/ports/port_l23/pcs_pma_l.py +0 -78
  106. {tdl_xoa_driver-1.5.0b2.dist-info → tdl_xoa_driver-1.6.0.dist-info}/WHEEL +0 -0
  107. {tdl_xoa_driver-1.5.0b2.dist-info → tdl_xoa_driver-1.6.0.dist-info}/licenses/LICENSE +0 -0
  108. {tdl_xoa_driver-1.5.0b2.dist-info → tdl_xoa_driver-1.6.0.dist-info}/top_level.txt +0 -0
  109. /xoa_driver/internals/hli/modules/modules_l23/{family_l1.py → family_freya.py} +0 -0
  110. /xoa_driver/internals/hli/ports/port_l23/{bases → layer1}/__init__.py +0 -0
  111. /xoa_driver/internals/hli/ports/port_l23/{bases → trafficgen}/port_capture.py +0 -0
@@ -24,7 +24,7 @@ def dictionize_autoneg_status(
24
24
  ) -> dict[str, Any]:
25
25
  _is_enabled = True if status.mode == enums.AutoNegMode.ANEG_ON else False
26
26
  _ta_hcd_status = status.tech_ability_hcd_status
27
- if _ta_hcd_status == enums.FreyaTechAbilityHCDStatus.FAILED:
27
+ if _ta_hcd_status == enums.AutoNegTechAbilityHCDStatus.FAILED:
28
28
  _ta_hcd_value = "N/A"
29
29
  _fec_result_value = "N/A"
30
30
  else:
@@ -138,12 +138,17 @@ def dictionize_lt_status(
138
138
 
139
139
 
140
140
  def dictionize_txtap_get(r: commands.PP_PHYTXEQ.GetDataAttr) -> dict[str, int]:
141
+ _pre = r.tap_values[0]
142
+ _main = r.tap_values[1]
143
+ _post = r.tap_values[2]
144
+ _pre2 = r.tap_values[3]
145
+ _pre3 = r.tap_values[4]
141
146
  return {
142
- "c(-3)": r.pre3_post2,
143
- "c(-2)": r.pre2,
144
- "c(-1)": r.pre,
145
- "c(0)": r.main,
146
- "c(1)": r.post,
147
+ "c(-3)": _pre3,
148
+ "c(-2)": _pre2,
149
+ "c(-1)": _pre,
150
+ "c(0)": _main,
151
+ "c(1)": _post,
147
152
  }
148
153
 
149
154
 
@@ -1,3 +1,4 @@
1
+ """Chassis Commands"""
1
2
  from __future__ import annotations
2
3
  from dataclasses import dataclass
3
4
  import ipaddress
@@ -2061,3 +2062,61 @@ class C_USED_TPLDID:
2061
2062
  """
2062
2063
 
2063
2064
  return Token(self._connection, build_get_request(self))
2065
+
2066
+ __all__ = [
2067
+ "C_BUILDSTRING",
2068
+ "C_CAPABILITIES",
2069
+ "C_COMMENT",
2070
+ "C_DEBUGCMD",
2071
+ "C_DEBUGLOGS",
2072
+ "C_DHCP",
2073
+ "C_DOWN",
2074
+ "C_FILEDATA",
2075
+ "C_FILEFINISH",
2076
+ "C_FILESTART",
2077
+ "C_FLASH",
2078
+ "C_HEALTH",
2079
+ "C_HOSTNAME",
2080
+ "C_INDICES",
2081
+ "C_IPADDRESS",
2082
+ "C_KEEPALIVE",
2083
+ "C_LOGOFF",
2084
+ "C_LOGON",
2085
+ "C_MACADDRESS",
2086
+ "C_MODEL",
2087
+ "C_MODEL_NAME",
2088
+ "C_MODEL_NUMBER",
2089
+ "C_MULTIUSER",
2090
+ "C_NAME",
2091
+ "C_OWNER",
2092
+ "C_PASSWORD",
2093
+ "C_PORTCOUNTS",
2094
+ "C_PORTERRORS",
2095
+ "C_REMOTEPORTCOUNTS",
2096
+ "C_RESERVATION",
2097
+ "C_RESERVEDBY",
2098
+ "C_RESTCONTROL",
2099
+ "C_RESTENABLE",
2100
+ "C_RESTPORT",
2101
+ "C_RESTSTATUS",
2102
+ "C_SCRIPT",
2103
+ "C_SERIALNO",
2104
+ "C_STATSESSION",
2105
+ "C_TEMPERATURE",
2106
+ "C_TIME",
2107
+ "C_TIMEOUT",
2108
+ "C_TKCONFIG",
2109
+ "C_TKGPSSTATE",
2110
+ "C_TKLICFILE",
2111
+ "C_TKLICSTATE",
2112
+ "C_TKSTATUS",
2113
+ "C_TKSTATUSEXT",
2114
+ "C_TKSVCSTATE",
2115
+ "C_TRAFFIC",
2116
+ "C_TRAFFICSYNC",
2117
+ "C_USED_TPLDID",
2118
+ "C_VERSIONNO",
2119
+ "C_VERSIONNO_MINOR",
2120
+ "C_VERSIONSTR",
2121
+ "C_WATCHDOG",
2122
+ ]
@@ -1,5 +1,7 @@
1
+ """Enums used in various commands."""
1
2
 
2
3
  from enum import IntEnum, IntFlag
4
+ from typing import Union
3
5
 
4
6
 
5
7
  # region L23 enums
@@ -2072,61 +2074,61 @@ class AutoNegMode(IntEnum):
2072
2074
  """Auto Neg On"""
2073
2075
 
2074
2076
 
2075
- class AutoNegTecAbility(IntEnum):
2076
- """Auto Neg Technical Abilities"""
2077
-
2078
- DEFAULT_TECH_MODE = 0
2079
- """Default Tech Mode"""
2080
- IEEE_10G_KR = 4
2081
- """IEEE 10G KR"""
2082
- IEEE_40G_CR4 = 16
2083
- """IEEE 40G CR4"""
2084
- IEEE_100G_KR4 = 128
2085
- """IEEE 100G KR4"""
2086
- IEEE_100G_CR4 = 256
2087
- """IEEE 100G CR4"""
2088
- IEEE_25GBASE_CRS_KRS = 512
2089
- """IEEE 25GBASE CRS KRS"""
2090
- IEEE_25GBASE_CR_KR = 1024
2091
- """IEEE 25GBASE CR KR"""
2092
- IEEE_50GBASE_CR_KR = 8192
2093
- """IEEE 50GBASE CR KR"""
2094
- IEEE_100GBASE_CR2_KR2 = 16384
2095
- """IEEE 100GBASE CR2 KR2"""
2096
- IEEE_200GBASE_CR4_KR4 = 32768
2097
- """IEEE 200GBASE CR4 KR4"""
2098
- IEEE_100GBASE_KR1 = 65536
2099
- """IEEE 100GBASE KR1"""
2100
- IEEE_200GBASE_KR2 = 131072
2101
- """IEEE 200GBASE KR2"""
2102
- IEEE_400GBASE_KR4 = 262144
2103
- """IEEE 400GBASE KR4"""
2104
- EC_25GBASE_KR1 = 16777216
2105
- """EC 25GBASE KR1"""
2106
- EC_25GBASE_CR1 = 33554432
2107
- """EC 25GBASE CR1"""
2108
- EC_50GBASE_KR2 = 67108864
2109
- """EC 50GBASE KR2"""
2110
- EC_50GBASE_CR2 = 134217728
2111
- """EC 50GBASE CR2"""
2112
- EC_400GBASE_KR8 = 268435456
2113
- """EC 400GBASE KR8"""
2114
- EC_800GBASE_KR8 = 536870912
2115
- """EC 800GBASE KR8"""
2116
- EC_50G_CR1_KR1 = 503
2117
- """EC 50G CR1 KR1"""
2118
- BAM_50G_CR1_KR1 = 504
2119
- """BAM 50G CR1 KR1"""
2120
- BAM_50G_CR2_KR2 = 505
2121
- """BAM 50G CR2 KR2"""
2122
- BAM_100G_CR2_KR2 = 1002
2123
- """BAM 100G CR2 KR2"""
2124
- BAM_100G_CR4_KR4 = 1003
2125
- """BAM 100G CR4 KR4"""
2126
- BAM_200G_CR2_KR2 = 2002
2127
- """BAM 200G CR2 KR2"""
2128
- BAM_400G_CR8_KR8 = 4001
2129
- """BAM 400G CR8 KR8"""
2077
+ # class AutoNegTecAbility(IntEnum):
2078
+ # """Auto Neg Technical Abilities"""
2079
+
2080
+ # DEFAULT_TECH_MODE = 0
2081
+ # """Default Tech Mode"""
2082
+ # IEEE_10G_KR = 4
2083
+ # """IEEE 10G KR"""
2084
+ # IEEE_40G_CR4 = 16
2085
+ # """IEEE 40G CR4"""
2086
+ # IEEE_100G_KR4 = 128
2087
+ # """IEEE 100G KR4"""
2088
+ # IEEE_100G_CR4 = 256
2089
+ # """IEEE 100G CR4"""
2090
+ # IEEE_25GBASE_CRS_KRS = 512
2091
+ # """IEEE 25GBASE CRS KRS"""
2092
+ # IEEE_25GBASE_CR_KR = 1024
2093
+ # """IEEE 25GBASE CR KR"""
2094
+ # IEEE_50GBASE_CR_KR = 8192
2095
+ # """IEEE 50GBASE CR KR"""
2096
+ # IEEE_100GBASE_CR2_KR2 = 16384
2097
+ # """IEEE 100GBASE CR2 KR2"""
2098
+ # IEEE_200GBASE_CR4_KR4 = 32768
2099
+ # """IEEE 200GBASE CR4 KR4"""
2100
+ # IEEE_100GBASE_KR1 = 65536
2101
+ # """IEEE 100GBASE KR1"""
2102
+ # IEEE_200GBASE_KR2 = 131072
2103
+ # """IEEE 200GBASE KR2"""
2104
+ # IEEE_400GBASE_KR4 = 262144
2105
+ # """IEEE 400GBASE KR4"""
2106
+ # EC_25GBASE_KR1 = 16777216
2107
+ # """EC 25GBASE KR1"""
2108
+ # EC_25GBASE_CR1 = 33554432
2109
+ # """EC 25GBASE CR1"""
2110
+ # EC_50GBASE_KR2 = 67108864
2111
+ # """EC 50GBASE KR2"""
2112
+ # EC_50GBASE_CR2 = 134217728
2113
+ # """EC 50GBASE CR2"""
2114
+ # EC_400GBASE_KR8 = 268435456
2115
+ # """EC 400GBASE KR8"""
2116
+ # EC_800GBASE_KR8 = 536870912
2117
+ # """EC 800GBASE KR8"""
2118
+ # EC_50G_CR1_KR1 = 503
2119
+ # """EC 50G CR1 KR1"""
2120
+ # BAM_50G_CR1_KR1 = 504
2121
+ # """BAM 50G CR1 KR1"""
2122
+ # BAM_50G_CR2_KR2 = 505
2123
+ # """BAM 50G CR2 KR2"""
2124
+ # BAM_100G_CR2_KR2 = 1002
2125
+ # """BAM 100G CR2 KR2"""
2126
+ # BAM_100G_CR4_KR4 = 1003
2127
+ # """BAM 100G CR4 KR4"""
2128
+ # BAM_200G_CR2_KR2 = 2002
2129
+ # """BAM 200G CR2 KR2"""
2130
+ # BAM_400G_CR8_KR8 = 4001
2131
+ # """BAM 400G CR8 KR8"""
2130
2132
 
2131
2133
 
2132
2134
  class AutoNegFECOption(IntFlag):
@@ -2134,19 +2136,19 @@ class AutoNegFECOption(IntFlag):
2134
2136
 
2135
2137
  DEFAULT_FEC = 0
2136
2138
  """Default FEC"""
2137
- NO_FEC = 1
2139
+ NO_FEC = 1<<0
2138
2140
  """No FEC"""
2139
- FCFEC = 2
2141
+ FCFEC = 1<<1
2140
2142
  """Firecode FEC"""
2141
- RSFEC_CL91 = 4
2143
+ RSFEC_CL91 = 1<<2
2142
2144
  """RS FEC Cl91"""
2143
- RS528 = 256
2145
+ RS528 = 1<<8
2144
2146
  """RS 528"""
2145
- RS544 = 512
2147
+ RS544 = 1<<9
2146
2148
  """RS 544"""
2147
- RS272 = 1024
2149
+ RS272 = 1<<10
2148
2150
  """RS 272"""
2149
- RSFEC_CL161 = 8
2151
+ RSFEC_CL161 = 1<<3
2150
2152
  """RS CL 161"""
2151
2153
 
2152
2154
 
@@ -2191,19 +2193,19 @@ class AutoNegFECStatus(IntFlag):
2191
2193
 
2192
2194
  DEFAULT_FEC = 0
2193
2195
  """Default FEC"""
2194
- NO_FEC = 1
2196
+ NO_FEC = 1<<0
2195
2197
  """No FEC"""
2196
- FC_FEC = 2
2198
+ FC_FEC = 1<<1
2197
2199
  """Firecode FEC"""
2198
- RSFEC_CL91 = 4
2200
+ RSFEC_CL91 = 1<<2
2199
2201
  """RS FEC Cl91"""
2200
- RS528 = 256
2202
+ RS528 = 1<<8
2201
2203
  """RS 528"""
2202
- RS544 = 512
2204
+ RS544 = 1<<9
2203
2205
  """RS 544"""
2204
- RS272 = 1024
2206
+ RS272 = 1<<10
2205
2207
  """RS 272"""
2206
- RSFEC_CL161 = 8
2208
+ RSFEC_CL161 = 1<<3
2207
2209
  """RS CL 161"""
2208
2210
 
2209
2211
 
@@ -2528,50 +2530,50 @@ class LinkTrainAnnounce(IntEnum):
2528
2530
  """The lane is trained"""
2529
2531
 
2530
2532
 
2531
- class AnLtLogControl(IntEnum):
2533
+ class AnLtLogControl(IntFlag):
2532
2534
  """
2533
2535
  ANLT log control bits
2534
2536
 
2535
2537
  """
2536
2538
 
2537
2539
  # 1st nibble
2538
- LOG_TYPE_DEBUG = 0x2
2540
+ LOG_TYPE_DEBUG = 1<<1
2539
2541
  """debug log output"""
2540
2542
 
2541
- LOG_TYPE_AN_TRACE = 0x4
2543
+ LOG_TYPE_AN_TRACE = 1<<2
2542
2544
  """autonegotiation trace output"""
2543
2545
 
2544
- LOG_TYPE_LT_TRACE = 0x8
2546
+ LOG_TYPE_LT_TRACE = 1<<3
2545
2547
  """link training trace output"""
2546
2548
 
2547
2549
  # 2nd nibble
2548
- LOG_TYPE_ALG_TRACE = 0x10
2550
+ LOG_TYPE_ALG_TRACE = 1<<4
2549
2551
  """link training algorithm trace"""
2550
2552
 
2551
2553
  # 5th nibble
2552
- LOG_TYPE_FSM_PORT = 0x10000
2554
+ LOG_TYPE_FSM_PORT = 1<<16
2553
2555
  """port state machine transitions"""
2554
2556
 
2555
- LOG_TYPE_FSM_ANEG = 0x20000
2557
+ LOG_TYPE_FSM_ANEG = 1<<17
2556
2558
  """autonegotiation state machine transitions. What we act on"""
2557
2559
 
2558
- LOG_TYPE_FSM_ANEG_STIMULI = 0x40000
2560
+ LOG_TYPE_FSM_ANEG_STIMULI = 1<<18
2559
2561
  """autonegotiation stimuli state machine transitions. What we ask"""
2560
2562
 
2561
- LOG_TYPE_FSM_LT = 0x80000
2563
+ LOG_TYPE_FSM_LT = 1<<19
2562
2564
  """link training state machine transitions"""
2563
2565
 
2564
2566
  # 6th nibble
2565
- LOG_TYPE_FSM_LT_COEFF = 0x100000
2567
+ LOG_TYPE_FSM_LT_COEFF = 1<<20
2566
2568
  """link training coefficient state machine transitions. What we act on"""
2567
2569
 
2568
- LOG_TYPE_FSM_LT_STIMULI = 0x200000
2570
+ LOG_TYPE_FSM_LT_STIMULI = 1<<21
2569
2571
  """link training stimuli state machine transitions. What we ask"""
2570
2572
 
2571
- LOG_TYPE_FSM_LT_ALG0 = 0x400000
2573
+ LOG_TYPE_FSM_LT_ALG0 = 1<<22
2572
2574
  """link training algorithm 0 state machine transitions"""
2573
2575
 
2574
- LOG_TYPE_FSM_LT_ALG1 = 0x800000
2576
+ LOG_TYPE_FSM_LT_ALG1 = 1<<23
2575
2577
  """link training algorithm -1 state machine transitions"""
2576
2578
 
2577
2579
 
@@ -2751,7 +2753,7 @@ class FreyaLinkTrainingMode(IntEnum):
2751
2753
  ENABLED_INTERACTIVE = 2
2752
2754
  """Link training in interactive mode, requiring manual operation."""
2753
2755
 
2754
- class FreyaTecAbility(IntFlag):
2756
+ class AutoNegTecAbility(IntFlag):
2755
2757
  """Auto Neg Technical Abilities"""
2756
2758
 
2757
2759
  ETC_800G_CR8_KR8 = 1<<29
@@ -2844,7 +2846,10 @@ class FreyaTecAbility(IntFlag):
2844
2846
  IEEE_1000BASE_KX = 1<<0
2845
2847
  """IEEE_1000BASE_KX"""
2846
2848
 
2847
- class FreyaFECAbility(IntFlag):
2849
+ DEFAULT_TECH = 0
2850
+ """Default Tech Ability"""
2851
+
2852
+ class AutoNegFECAbility(IntFlag):
2848
2853
  """Auto Neg FEC ability"""
2849
2854
 
2850
2855
  RS_FEC_Int = 1<<4
@@ -2862,8 +2867,14 @@ class FreyaFECAbility(IntFlag):
2862
2867
  FC_FEC_10G_ABILITY = 1<<0
2863
2868
  """FC_FEC_10G_ABILITY"""
2864
2869
 
2865
- class FreyaPauseAbility(IntFlag):
2866
- """Auto Neg Pause ability"""
2870
+ DEFAULT_FEC = 0
2871
+ """Default FEC Ability"""
2872
+
2873
+ class AutoNegPauseAbility(IntFlag):
2874
+ """AutoNeg Pause ability"""
2875
+
2876
+ NO_PAUSE = 0
2877
+ """NO_PAUSE"""
2867
2878
 
2868
2879
  ASYM_PAUSE = 1<<1
2869
2880
  """ASYM_PAUSE"""
@@ -2871,8 +2882,8 @@ class FreyaPauseAbility(IntFlag):
2871
2882
  SYM_PAUSE = 1<<0
2872
2883
  """SYM_PAUSE"""
2873
2884
 
2874
- class FreyaTechAbilityHCDStatus(IntEnum):
2875
- """Auto Neg Pause ability"""
2885
+ class AutoNegTechAbilityHCDStatus(IntEnum):
2886
+ """Auto Neg Tech Ability HCD Status"""
2876
2887
 
2877
2888
  SUCCESS = 1
2878
2889
  """SUCCESS"""
@@ -2911,8 +2922,8 @@ class FreyaPCSVariant(IntEnum):
2911
2922
  ETC = 2
2912
2923
  """ETC"""
2913
2924
 
2914
- class FreyaTecAbilityHCD(IntEnum):
2915
- """Auto Neg Technical Abilities"""
2925
+ class AutoNegTecAbilityHCD(IntEnum):
2926
+ """Auto Neg Technical Abilities HCD"""
2916
2927
 
2917
2928
  ETC_800G_CR8_KR8 = 29
2918
2929
  """ETC_800G_CR8_KR8"""
@@ -1,3 +1,4 @@
1
+ """Module (L47) Commands"""
1
2
  from __future__ import annotations
2
3
  from dataclasses import dataclass
3
4
  import typing
@@ -698,3 +699,27 @@ class M4_TLS_CIPHER_SUITES:
698
699
  """
699
700
 
700
701
  return Token(self._connection, build_get_request(self, module=self._module))
702
+
703
+
704
+ __all__ = [
705
+ "M4_CAPTURE_FILE_DELETE",
706
+ "M4_CAPTURE_FILE_LIST",
707
+ "M4_CAPTURE_FILE_LIST_BSON",
708
+ "M4_CAPTURE_SIZE",
709
+ "M4_COMPATIBLE_CLIENT_VERSION",
710
+ "M4_LICENSE_INFO",
711
+ "M4_MEM_INFO",
712
+ "M4_REPLAY_FILE_DELETE",
713
+ "M4_REPLAY_FILE_LIST",
714
+ "M4_REPLAY_FILE_LIST_BSON",
715
+ "M4_REPLAY_PARSER_PARAMS",
716
+ "M4_REPLAY_PARSE_START",
717
+ "M4_REPLAY_PARSE_STATE",
718
+ "M4_REPLAY_PARSE_STOP",
719
+ "M4_SYSTEMID",
720
+ "M4_SYSTEM_STATUS",
721
+ "M4_SYSTEM_TIME",
722
+ "M4_TIME",
723
+ "M4_TLS_CIPHER_SUITES",
724
+ "M4_VERSIONNO",
725
+ ]
@@ -1,3 +1,4 @@
1
+ """Module (L47) Packet Engine Commands"""
1
2
  from __future__ import annotations
2
3
  from dataclasses import dataclass
3
4
  import typing
@@ -105,3 +106,8 @@ class M4E_RESERVE:
105
106
  """
106
107
 
107
108
  return Token(self._connection, build_set_request(self, module=self._module, mask=mask))
109
+
110
+ __all__ = [
111
+ "M4E_MODE",
112
+ "M4E_RESERVE",
113
+ ]
@@ -1,3 +1,4 @@
1
+ """Module Commands"""
1
2
  from __future__ import annotations
2
3
  from dataclasses import dataclass
3
4
  import typing
@@ -1900,4 +1901,53 @@ class M_RECONFIG_STATUS:
1900
1901
  :rtype: M_RECONFIG_STATUS.GetDataAttr
1901
1902
  """
1902
1903
 
1903
- return Token(self._connection, build_get_request(self, module=self._module))
1904
+ return Token(self._connection, build_get_request(self, module=self._module))
1905
+
1906
+ __all__ = [
1907
+ "M_CAPABILITIES",
1908
+ "M_CFPCONFIG",
1909
+ "M_CFPCONFIGEXT",
1910
+ "M_CFPTYPE",
1911
+ "M_CLOCKPPB",
1912
+ "M_CLOCKPPBSWEEP",
1913
+ "M_CLOCKSWEEPSTATUS",
1914
+ "M_CLOCKSYNCSTATUS",
1915
+ "M_COMMENT",
1916
+ "M_EMULBYPASS",
1917
+ "M_FPGAREIMAGE",
1918
+ "M_HEALTH",
1919
+ "M_LATENCYMODE",
1920
+ "M_LICENSE_CWB_DETECTED",
1921
+ "M_LICENSE_DEMO_INFO",
1922
+ "M_LICENSE_LIST_BSON",
1923
+ "M_LICENSE_MAINTENANCE_INFO",
1924
+ "M_LICENSE_ONLINE",
1925
+ "M_LICENSE_UPDATE",
1926
+ "M_LICENSE_UPDATE_STATUS",
1927
+ "M_MEDIA",
1928
+ "M_MEDIASUPPORT",
1929
+ "M_MODEL",
1930
+ "M_MODEL_NAME",
1931
+ "M_MULTIUSER",
1932
+ "M_NAME",
1933
+ "M_PORTCOUNT",
1934
+ "M_RECONFIG_STATUS",
1935
+ "M_RESERVATION",
1936
+ "M_RESERVEDBY",
1937
+ "M_REVISION",
1938
+ "M_SERIALNO",
1939
+ "M_SMAINPUT",
1940
+ "M_SMAOUTPUT",
1941
+ "M_SMASTATUS",
1942
+ "M_STATUS",
1943
+ "M_TIMEADJUSTMENT",
1944
+ "M_TIMESYNC",
1945
+ "M_TXCLOCKFILTER_NEW",
1946
+ "M_TXCLOCKSOURCE_NEW",
1947
+ "M_TXCLOCKSTATUS_NEW",
1948
+ "M_UPGRADE",
1949
+ "M_UPGRADEPAR",
1950
+ "M_UPGRADEPROGRESS",
1951
+ "M_VERSIONNO",
1952
+ "M_VERSIONSTR",
1953
+ ]
@@ -1,3 +1,4 @@
1
+ """Port (L47) Commands"""
1
2
  from __future__ import annotations
2
3
  from dataclasses import dataclass
3
4
  import typing
@@ -1883,7 +1884,7 @@ class P4_DHCP_RESULT:
1883
1884
  _port: int
1884
1885
 
1885
1886
  class GetDataAttr(ResponseBodyStruct):
1886
- dhcp_chunks: typing.List[subtypes.DhcpChunk] = field(XmpSequence(types_chunk=[XmpIPv4Address(), XmpIPv4Address(), XmpIPv4Address(), XmpIPv4Address(), XmpInt(), XmpMacAddress()]))
1887
+ dhcp_chunks: typing.List[subtypes.DhcpEntry] = field(XmpSequence(types_chunk=[XmpIPv4Address(), XmpIPv4Address(), XmpIPv4Address(), XmpIPv4Address(), XmpInt(), XmpMacAddress()]))
1887
1888
 
1888
1889
  def get(self) -> "Token[GetDataAttr]":
1889
1890
  """Get the port's the result of the last DHCP client process
@@ -2219,3 +2220,64 @@ class P4_APTITUDES:
2219
2220
  """
2220
2221
 
2221
2222
  return Token(self._connection, build_get_request(self, module=self._module, port=self._port))
2223
+
2224
+
2225
+ __all__ = [
2226
+ "P4_APTITUDES",
2227
+ "P4_ARP_CONFIG",
2228
+ "P4_ARP_COUNTERS",
2229
+ "P4_ARP_RX_COUNTERS",
2230
+ "P4_ARP_TX_COUNTERS",
2231
+ "P4_CAPABILITIES",
2232
+ "P4_CAPTURE",
2233
+ "P4_CAPTURE_GET_FIRST",
2234
+ "P4_CAPTURE_GET_NEXT",
2235
+ "P4_CLEAR",
2236
+ "P4_CLEAR_COUNTERS",
2237
+ "P4_DEV_NAME",
2238
+ "P4_DHCP_CONFIG",
2239
+ "P4_DHCP_RESULT",
2240
+ "P4_DHCP_RUN",
2241
+ "P4_DHCP_STATE",
2242
+ "P4_DHCP_VLAN",
2243
+ "P4_ETH_COUNTERS",
2244
+ "P4_ETH_QUEUE_COUNTERS",
2245
+ "P4_ETH_RX_COUNTERS",
2246
+ "P4_ETH_TX_COUNTERS",
2247
+ "P4_FW_VER",
2248
+ "P4_ICMP_COUNTERS",
2249
+ "P4_ICMP_RX_COUNTERS",
2250
+ "P4_ICMP_TX_COUNTERS",
2251
+ "P4_IPV4_COUNTERS",
2252
+ "P4_IPV4_RX_COUNTERS",
2253
+ "P4_IPV4_TX_COUNTERS",
2254
+ "P4_IPV6_COUNTERS",
2255
+ "P4_IPV6_RX_COUNTERS",
2256
+ "P4_IPV6_TX_COUNTERS",
2257
+ "P4_LICENSE_INFO",
2258
+ "P4_MAX_PACKET_RATE",
2259
+ "P4_NDP_CONFIG",
2260
+ "P4_NDP_COUNTERS",
2261
+ "P4_NDP_RX_COUNTERS",
2262
+ "P4_NDP_TX_COUNTERS",
2263
+ "P4_PCI_INFO",
2264
+ "P4_PORT_COUNTERS",
2265
+ "P4_PORT_RX_COUNTERS",
2266
+ "P4_PORT_TX_COUNTERS",
2267
+ "P4_PORT_TYPE",
2268
+ "P4_RX_MTU",
2269
+ "P4_RX_PACKET_SIZE",
2270
+ "P4_SPEEDSELECTION",
2271
+ "P4_STATE",
2272
+ "P4_STATE_STATUS",
2273
+ "P4_TCP_COUNTERS",
2274
+ "P4_TCP_RX_COUNTERS",
2275
+ "P4_TCP_TX_COUNTERS",
2276
+ "P4_TRAFFIC",
2277
+ "P4_TX_MTU",
2278
+ "P4_TX_PACKET_SIZE",
2279
+ "P4_UDP_COUNTERS",
2280
+ "P4_UDP_RX_COUNTERS",
2281
+ "P4_UDP_TX_COUNTERS",
2282
+ "P4_VLAN_OFFLOAD",
2283
+ ]
@@ -1,3 +1,4 @@
1
+ """Port (L47) Packet Engine Commands"""
1
2
  from __future__ import annotations
2
3
  from dataclasses import dataclass
3
4
  import typing
@@ -158,3 +159,11 @@ class P4E_ALLOCATION_INFO:
158
159
  """
159
160
 
160
161
  return Token(self._connection, build_get_request(self, module=self._module, port=self._port))
162
+
163
+
164
+ __all__ = [
165
+ "P4E_ALLOCATE",
166
+ "P4E_ALLOCATION_INFO",
167
+ "P4E_ASSIGN",
168
+ "P4E_AVAILABLE",
169
+ ]