switchboard-hw 0.3.0__cp314-cp314-macosx_10_15_x86_64.whl

switchboard/cpp/switchboard.hpp

@@ -0,0 +1,257 @@
+// Copyright (c) 2024 Zero ASIC Corporation
+// This code is licensed under Apache License 2.0 (see LICENSE for details)
+
+#ifndef __SWITCHBOARD_HPP__
+#define __SWITCHBOARD_HPP__
+
+#include <array>
+#include <chrono>
+#include <cstdio>
+#include <stdexcept>
+#include <string>
+#include <thread>
+#include <vector>
+
+#include "spsc_queue.h"
+
+// packet type
+// TODO: make size runtime programmable
+#define SB_DATA_SIZE 52
+struct sb_packet {
+    uint32_t destination;
+    union {
+        struct {
+            unsigned int last : 1;
+        };
+        uint32_t flags;
+    };
+    uint8_t data[SB_DATA_SIZE];
+} __attribute__((packed));
+
+static inline long max_rate_timestamp_us() {
+    return std::chrono::duration_cast<std::chrono::microseconds>(
+        std::chrono::high_resolution_clock::now().time_since_epoch())
+        .count();
+}
+
+static inline void max_rate_tick(long& last_us, long min_period_us) {
+    if (min_period_us > 0) {
+        // measure the time now
+
+        long now_us = max_rate_timestamp_us();
+
+        // sleep if needed
+
+        if (last_us != -1) {
+            long dt_us = now_us - last_us;
+
+            if (dt_us < min_period_us) {
+                long sleep_us = min_period_us - dt_us;
+                std::this_thread::sleep_for(std::chrono::microseconds(sleep_us));
+            }
+        }
+
+        // update the time stamp.  it is not enough to set last_us = now_us,
+        // due to the sleep_for invocation
+
+        last_us = max_rate_timestamp_us();
+    }
+}
+
+static inline void start_delay(double value) {
+    if (value > 0) {
+        int value_us = (value * 1.0e6) + 0.5;
+        std::this_thread::sleep_for(std::chrono::microseconds(value_us));
+    }
+}
+
+class SB_base {
+  public:
+    SB_base() : m_active(false), m_q(NULL) {}
+
+    virtual ~SB_base() {
+        deinit();
+    }
+
+    void init(std::string uri, size_t capacity = 0, bool fresh = false, double max_rate = -1) {
+        init(uri.c_str(), capacity, fresh, max_rate);
+    }
+
+    void init(const char* uri, size_t capacity = 0, bool fresh = false, double max_rate = -1) {
+        // Default to one page of capacity
+        if (capacity == 0) {
+            capacity = spsc_capacity(getpagesize());
+        }
+
+        // delete old queue if "fresh" is set
+        if (fresh) {
+            spsc_remove_shmfile(uri);
+        }
+
+        m_q = spsc_open(uri, capacity);
+        m_active = true;
+        m_timestamp_us = -1;
+
+        set_max_rate(max_rate);
+    }
+
+    void deinit(void) {
+        spsc_close(m_q);
+        m_active = false;
+    }
+
+    bool is_active() {
+        return m_active;
+    }
+
+    int mlock(void) {
+        check_active();
+        assert(m_q);
+        return spsc_mlock(m_q);
+    }
+
+    int get_capacity(void) {
+        check_active();
+        return m_q->capacity;
+    }
+
+    void* get_shm_handle(void) {
+        check_active();
+        return m_q->shm;
+    }
+
+    void set_max_rate(double max_rate) {
+        if (max_rate > 0) {
+            m_min_period_us = (1.0e6 / max_rate) + 0.5;
+        } else {
+            m_min_period_us = -1;
+        }
+    }
+
+  protected:
+    void check_active(void) {
+        if (!m_active) {
+            throw std::runtime_error("Using an uninitialized SB queue!");
+        }
+    }
+
+    bool m_auto_deinit;
+    bool m_active;
+    long m_min_period_us;
+    long m_timestamp_us;
+    spsc_queue* m_q;
+};
+
+class SBTX : public SB_base {
+  public:
+    SBTX() {}
+
+    bool send(sb_packet& p) {
+        check_active();
+        max_rate_tick(m_timestamp_us, m_min_period_us);
+        return spsc_send(m_q, &p, sizeof p);
+    }
+
+    void send_blocking(sb_packet& p) {
+        bool success = false;
+
+        while (!success) {
+            success = send(p);
+
+            if ((!success) && (m_min_period_us == -1)) {
+                // maintain old behavior if max_rate isn't specified,
+                // i.e. yield on every iteration that the send isn't
+                // successful
+                std::this_thread::yield();
+            }
+        }
+    }
+
+    bool all_read() {
+        check_active();
+        return spsc_size(m_q) == 0;
+    }
+};
+
+class SBRX : public SB_base {
+  public:
+    SBRX() {}
+
+    bool recv(sb_packet& p) {
+        check_active();
+        max_rate_tick(m_timestamp_us, m_min_period_us);
+        return spsc_recv(m_q, &p, sizeof p);
+    }
+
+    bool recv() {
+        check_active();
+        sb_packet dummy_p;
+        max_rate_tick(m_timestamp_us, m_min_period_us);
+        return spsc_recv(m_q, &dummy_p, sizeof dummy_p);
+    }
+
+    void recv_blocking(sb_packet& p) {
+        bool success = false;
+
+        while (!success) {
+            success = recv(p);
+
+            if ((!success) && (m_min_period_us == -1)) {
+                // maintain old behavior if max_rate isn't specified,
+                // i.e. yield on every iteration that the send isn't
+                // successful
+                std::this_thread::yield();
+            }
+        }
+    }
+
+    bool recv_peek(sb_packet& p) {
+        check_active();
+        max_rate_tick(m_timestamp_us, m_min_period_us);
+        return spsc_recv_peek(m_q, &p, sizeof p);
+    }
+};
+
+static inline void delete_shared_queue(const char* name) {
+    spsc_remove_shmfile(name);
+}
+
+static inline void delete_shared_queue(std::string name) {
+    delete_shared_queue(name.c_str());
+}
+
+static inline std::string sb_packet_to_str(sb_packet p, ssize_t nbytes = -1) {
+    // determine how many bytes to print
+    size_t max_idx;
+    if (nbytes < 0) {
+        max_idx = sizeof(p.data);
+    } else {
+        max_idx = nbytes;
+    }
+
+    // used for convenient formatting with sprintf
+    char buf[128];
+
+    // build up return value
+    std::string retval;
+    retval = "";
+
+    // format control information
+    sprintf(buf, "dest: %08x, last: %d, data: {", p.destination, p.last);
+    retval += buf;
+
+    // format data
+    for (size_t i = 0; i < max_idx; i++) {
+        sprintf(buf, "%02x", p.data[i]);
+        retval += buf;
+        if (i != (max_idx - 1)) {
+            retval += ", ";
+        }
+    }
+
+    retval += "}";
+
+    return retval;
+}
+
+#endif // __SWITCHBOARD_HPP__

switchboard/cpp/switchboard_pcie.hpp

@@ -0,0 +1,234 @@
+// Switchboard FPGA/PCIe transactor driver
+
+// Copyright (c) 2024 Zero ASIC Corporation
+// This code is licensed under Apache License 2.0 (see LICENSE for details)
+
+#ifndef __SWITCHBOARD_PCIE_HPP__
+#define __SWITCHBOARD_PCIE_HPP__
+
+#include <array>
+#include <cstdio>
+#include <string>
+#include <thread>
+#include <vector>
+
+#include "pagemap.h"
+#include "pciedev.h"
+#include "spsc_queue.h"
+#include "switchboard.hpp"
+
+#undef D
+#define D(x)
+
+#define REG_ID 0x000
+#define REG_ID_FPGA 0x1234
+
+#define REG_CAP 0x004
+
+#define REG_ENABLE 0x100
+#define REG_RESET 0x104
+#define REG_STATUS 0x108
+#define REG_QUEUE_ADDRESS_LO 0x10c
+#define REG_QUEUE_ADDRESS_HI 0x110
+#define REG_QUEUE_CAPACITY 0x114
+
+#define REG_QUEUE_ADDR_SIZE 0x100 // size of addr space dedicated to each queue
+
+// Map enough space to configure 256 queues + global config.
+#define PCIE_BAR_MAP_SIZE (REG_QUEUE_ADDR_SIZE * 256 + REG_ENABLE)
+
+// Max nr of retries when resetting or disabling queue's.
+#define MAX_RETRY 3
+
+template <typename T> static inline void sb_pcie_deinit(T* s) {
+
+    // Needs to be done in reverse order.
+    s->deinit_dev();
+    s->deinit_host();
+}
+
+class SB_pcie {
+  public:
+    SB_pcie(int queue_id) : m_queue_id(queue_id), m_map(NULL), m_addr(0) {}
+
+    ~SB_pcie() {
+        sb_pcie_deinit(this);
+    }
+
+    virtual bool init_host(const char* uri, const char* bdf, int bar_num, void* handle) {
+        m_addr = pagemap_virt_to_phys(handle);
+        m_map = (char*)pcie_bar_map(bdf, bar_num, 0, PCIE_BAR_MAP_SIZE);
+        if (m_map == MAP_FAILED) {
+            m_map = NULL;
+            return false;
+        }
+        return true;
+    }
+
+    virtual void deinit_host(void) {
+        if (m_map) {
+            pcie_bar_unmap(m_map, PCIE_BAR_MAP_SIZE);
+            m_map = NULL;
+        }
+    }
+
+    bool init_dev(int capacity) {
+        int qoffset = m_queue_id * REG_QUEUE_ADDR_SIZE;
+        int reset_retry = 0;
+        uint32_t r;
+
+        r = dev_read32(REG_ID);
+        D(printf("SB pcie ID=%x\n", r));
+        if (r >> 16 != REG_ID_FPGA) {
+            printf("%s: Incompatible REG_ID=%x\n", __func__, r);
+            return false;
+        }
+
+        r = dev_read32(REG_CAP);
+        D(printf("SB pcie CAP=%x\n", r));
+
+        // Reset the device.
+        dev_write32(qoffset + REG_RESET, 0x1);
+        D(printf("Read reset state\n"));
+        while (dev_read32(qoffset + REG_STATUS) != 0x1) {
+            if (reset_retry++ >= MAX_RETRY) {
+                return false;
+            }
+            usleep(100 * 1000);
+        }
+
+        dev_write32(qoffset + REG_QUEUE_ADDRESS_LO, m_addr);
+        dev_write32(qoffset + REG_QUEUE_ADDRESS_HI, m_addr >> 32);
+        D(printf("SB QUEUE_ADDR=%lx\n", m_addr));
+
+        dev_write32(qoffset + REG_QUEUE_CAPACITY, capacity);
+        D(printf("SB CAPACITY=%d\n", capacity));
+
+        dev_write32_strong(qoffset + REG_ENABLE, 0x1);
+        return true;
+    }
+
+    void deinit_dev() {
+        int disable_retry = 0;
+
+        if (!m_map) {
+            return;
+        }
+        int qoffset = m_queue_id * REG_QUEUE_ADDR_SIZE;
+
+        // Must disable queue and wait for it to quiesce before unmapping
+        // queue shared memory, otherwise FPGA may read from/write to memory
+        // that gets reallocated to another process.
+        dev_write32_strong(qoffset + REG_ENABLE, 0x0);
+        while (dev_read32(qoffset + REG_STATUS) != 0x1) {
+            if (disable_retry++ >= MAX_RETRY) {
+                return;
+            }
+            usleep(100 * 1000);
+        }
+    }
+
+    virtual uint32_t dev_read32(uint64_t offset) {
+        assert(m_map);
+        assert(offset <= PCIE_BAR_MAP_SIZE - 4);
+        return pcie_read32(m_map + offset);
+    }
+
+    virtual void dev_write32(uint64_t offset, uint32_t v) {
+        assert(m_map);
+        assert(offset <= PCIE_BAR_MAP_SIZE - 4);
+        pcie_write32(m_map + offset, v);
+    }
+
+    virtual void dev_write32_strong(uint64_t offset, uint32_t v) {
+        assert(m_map);
+        assert(offset <= PCIE_BAR_MAP_SIZE - 4);
+        pcie_write32_strong(m_map + offset, v);
+    }
+
+  protected:
+    // Queue index.
+    int m_queue_id;
+
+    // m_map holds a pointer to a mapped memory area that can be
+    // used for register accesses. Not all implementations will use it.
+    char* m_map;
+
+    // m_addr holds an address to the SPSC queue's SHM area. For some
+    // implementations this will simply be a user-space virtual address
+    // and for others it may be a physical address for HW DMA implementations
+    // to access.
+    uint64_t m_addr;
+};
+
+static inline bool sb_init_queue(SB_base* s, const char* uri) {
+    int capacity;
+
+    // Create queue's that fit into a single page.
+    capacity = spsc_capacity(getpagesize());
+    s->init(uri, capacity);
+
+    // Lock pages into RAM (avoid ondemand allocation or swapping).
+    if (s->mlock()) {
+        perror("mlock");
+        s->deinit();
+        return false;
+    }
+    return true;
+}
+
+template <typename T>
+static inline bool sb_pcie_init(T* s, const char* uri, const char* bdf, int bar_num) {
+    sb_init_queue(s, uri);
+
+    if (!s->init_host(uri, bdf, bar_num, s->get_shm_handle())) {
+        s->deinit();
+        return false;
+    }
+
+    if (!s->init_dev(s->get_capacity())) {
+        s->deinit();
+        return false;
+    }
+    return true;
+}
+
+class SBTX_pcie : public SBTX, public SB_pcie {
+  public:
+    SBTX_pcie(int queue_id) : SB_pcie(queue_id) {}
+
+    bool init(std::string uri, std::string bdf, int bar_num) {
+        return init(uri.c_str(), bdf.c_str(), bar_num);
+    }
+
+    bool init(const char* uri, const char* bdf, int bar_num) {
+        return sb_pcie_init(this, uri, bdf, bar_num);
+    }
+
+    void deinit(void) {
+        sb_pcie_deinit(this);
+    }
+
+  private:
+};
+
+class SBRX_pcie : public SBRX, public SB_pcie {
+  public:
+    SBRX_pcie(int queue_id) : SB_pcie(queue_id) {}
+
+    bool init(std::string uri, std::string bdf, int bar_num) {
+        return init(uri.c_str(), bdf.c_str(), bar_num);
+    }
+
+    bool init(const char* uri, const char* bdf, int bar_num) {
+        return sb_pcie_init(this, uri, bdf, bar_num);
+    }
+
+    void deinit(void) {
+        sb_pcie_deinit(this);
+    }
+
+  private:
+};
+
+#endif // __SWITCHBOARD_PCIE_HPP__

switchboard/cpp/switchboard_tlm.hpp

@@ -0,0 +1,98 @@
+// Switchboard TLM transactor driver
+
+// Copyright (c) 2024 Zero ASIC Corporation
+// This code is licensed under Apache License 2.0 (see LICENSE for details)
+
+#ifndef __SWITCHBOARD_TLM_HPP__
+#define __SWITCHBOARD_TLM_HPP__
+
+#include <array>
+#include <cstdio>
+#include <string>
+#include <thread>
+#include <vector>
+
+#include "spsc_queue.h"
+#include "switchboard.hpp"
+#include "switchboard_pcie.hpp"
+
+#define SC_INCLUDE_DYNAMIC_PROCESSES
+
+#include "systemc"
+using namespace sc_core;
+using namespace sc_dt;
+using namespace std;
+
+#include "tlm.h"
+#include "tlm_utils/simple_initiator_socket.h"
+#include "tlm_utils/simple_target_socket.h"
+
+class SB_tlm : public SB_pcie {
+  public:
+    tlm_utils::simple_initiator_socket<SB_tlm> socket;
+
+    SB_tlm(int queue_id) : SB_pcie(queue_id) {}
+
+    bool init_host(const char* uri, const char* bdf, int bar_num, void* handle) {
+        assert(handle);
+        m_addr = (uintptr_t)handle;
+        return true;
+    }
+
+    void dev_access(tlm::tlm_command cmd, uint64_t offset, void* buf, unsigned int len) {
+        unsigned char* buf8 = (unsigned char*)buf;
+        sc_time delay = SC_ZERO_TIME;
+        tlm::tlm_generic_payload tr;
+
+        tr.set_command(cmd);
+        tr.set_address(offset);
+        tr.set_data_ptr(buf8);
+        tr.set_data_length(len);
+        tr.set_streaming_width(len);
+        tr.set_dmi_allowed(false);
+        tr.set_response_status(tlm::TLM_INCOMPLETE_RESPONSE);
+
+        socket->b_transport(tr, delay);
+        assert(tr.get_response_status() == tlm::TLM_OK_RESPONSE);
+    }
+
+    uint32_t dev_read32(uint64_t offset) {
+        uint32_t r;
+        assert((offset & 3) == 0);
+        dev_access(tlm::TLM_READ_COMMAND, offset, &r, sizeof(r));
+        return r;
+    }
+
+    void dev_write32(uint64_t offset, uint32_t v) {
+        assert((offset & 3) == 0);
+        dev_access(tlm::TLM_WRITE_COMMAND, offset, &v, sizeof(v));
+    }
+
+    void dev_write32_strong(uint64_t offset, uint32_t v) {
+        uint32_t dummy;
+
+        dev_write32(offset, v);
+        // Enforce PCIe ordering.
+        dummy = dev_read32(offset);
+        dummy = dummy;
+    }
+};
+
+class SBTX_tlm : public SBTX, public SB_tlm {
+  public:
+    SBTX_tlm(int queue_id) : SB_tlm(queue_id) {}
+
+    bool init(const char* uri) {
+        return sb_pcie_init(this, uri, NULL, -1);
+    }
+};
+
+class SBRX_tlm : public SBRX, public SB_tlm {
+  public:
+    SBRX_tlm(int queue_id) : SB_tlm(queue_id) {}
+
+    bool init(const char* uri) {
+        return sb_pcie_init(this, uri, NULL, -1);
+    }
+};
+#endif