switchboard-hw 0.3.0__cp314-cp314-macosx_10_15_x86_64.whl

switchboard/verilog/common/uart_xactor.sv

@@ -0,0 +1,247 @@
+// UMI/UART Transactor
+
+// Copyright (c) 2024 Zero ASIC Corporation
+// This code is licensed under Apache License 2.0 (see LICENSE for details)
+
+// Written by Edgar E. Iglesias
+
+`default_nettype none
+
+module uart_xactor
+  #(parameter BAUDRATE=115200,
+    parameter CLK_FREQ=100 * 1000 * 1000,
+    parameter DW=256,
+    parameter AW=64,
+    parameter CW=32
+)
+(
+   input clk,
+   input nreset,
+   output umi_req_ready,
+   input [CW-1:0] umi_req_cmd,
+   input [DW-1:0]  umi_req_data,
+   input [AW-1:0] umi_req_dstaddr,
+   input [AW-1:0] umi_req_srcaddr,
+   input umi_req_valid,
+
+   input umi_resp_ready,
+   output [CW-1:0] umi_resp_cmd,
+   output [DW-1:0]  umi_resp_data,
+   output [AW-1:0] umi_resp_dstaddr,
+   output [AW-1:0] umi_resp_srcaddr,
+   output umi_resp_valid,
+
+   output tx_pad,
+   input rx_pad
+);
+   localparam UART_DEBUG = 0;
+   localparam UART_CLKDIV = (CLK_FREQ / (16 * BAUDRATE) * 16 - 1);
+
+   localparam REG_TX  = 0;
+   localparam REG_RX  = 4;
+   localparam REG_SR  = 8;
+
+   wire [AW-1:0] loc_addr;   // memory address
+   wire          loc_write;  // write enable
+   wire          loc_read;   // read request
+   wire          loc_atomic; // atomic request
+   wire [7:0]    loc_opcode; // opcode
+   wire [2:0]    loc_size;   // size
+   wire [7:0]    loc_len;    // len
+   wire [7:0]    loc_atype;  // atomic type
+   wire [DW-1:0] loc_wrdata; // data to write
+   reg  [DW-1:0] loc_rddata; // data response
+   wire          loc_ready;  // device is ready
+
+   umi_endpoint #(.DW(DW))
+   ep(.*,
+      .udev_req_ready(umi_req_ready),
+      .udev_req_cmd(umi_req_cmd),
+      .udev_req_data(umi_req_data),
+      .udev_req_dstaddr(umi_req_dstaddr),
+      .udev_req_srcaddr(umi_req_srcaddr),
+      .udev_req_valid(umi_req_valid),
+
+      .udev_resp_ready(umi_resp_ready),
+      .udev_resp_cmd(umi_resp_cmd),
+      .udev_resp_data(umi_resp_data),
+      .udev_resp_dstaddr(umi_resp_dstaddr),
+      .udev_resp_srcaddr(umi_resp_srcaddr),
+      .udev_resp_valid(umi_resp_valid));
+
+   assign loc_ready = 1;
+
+   wire rxfifo_full;
+   wire rxfifo_empty;
+   wire [7:0] rxfifo_dout;
+
+   wire txfifo_full;
+   wire txfifo_empty;
+
+   wire [31:0] reg_sr = {16'b0,
+                         6'b0, txfifo_full, txfifo_empty,
+                         6'b0, rxfifo_full, rxfifo_empty};
+   wire        rxfifo_read = loc_read && loc_addr == REG_RX;
+   wire        txfifo_write = loc_write && loc_addr == REG_TX;
+
+   // Reg access logic.
+   always @(posedge clk or negedge nreset) begin
+       if (~nreset) begin
+           loc_rddata <= 0;
+       end else begin
+          if (loc_read) begin
+             case (loc_addr)
+                REG_RX: loc_rddata <= {24'b0, rxfifo_dout};
+                REG_SR: loc_rddata <= reg_sr;
+                default: loc_rddata <= 'hdeadbeef;
+             endcase
+          end
+       end
+   end
+
+   // UART
+   localparam STATE_START = 0;
+   localparam STATE_STOP  = 8;
+   localparam STATE_STOP2 = 9;
+
+   reg [$clog2(UART_CLKDIV):0] clk_i;
+   reg [$clog2(STATE_STOP):0]  rx_state;
+   reg [8-1:0]                 rx_data;
+   reg                         reset_sync;
+
+   wire                        clk_en = (clk_i == 0);
+   wire [8-1:0]                rx_next_data = {rx_pad, rx_data[7:1]};
+   wire                        rx_next_data_en = clk_en && rx_state == STATE_STOP;
+
+   reg tx_xmit;
+   wire txfifo_read = ~tx_xmit && ~txfifo_empty;
+   wire [7:0] txfifo_dout;
+
+   la_syncfifo #(.DW(8),
+      .DEPTH(80),        // FIFO Depth, can hold an 80 chars line?
+      .NS(1),            // Number of power supplies
+      .CHAOS(0),         // generates random full logic when set
+      .CTRLW(1),         // width of asic ctrl interface
+      .TESTW(1))         // width of asic test interface
+      rx_fifo(
+         .wr_full          (rxfifo_full),
+         .rd_dout          (rxfifo_dout),
+         .rd_empty         (rxfifo_empty),
+         .clk              (clk),
+         .nreset           (nreset),
+         .clear            (1'b0),
+         .vss              (1'b0),
+         .vdd              (1'b1),
+         .chaosmode        (1'b0),
+         .ctrl             (1'b0),
+         .test             (1'b0),
+         .wr_en            (rx_next_data_en),
+         .wr_din           (rx_next_data),
+         .rd_en            (rxfifo_read));
+
+   la_syncfifo #(.DW(8),
+      .DEPTH(80),        // FIFO Depth, can hold an 80 chars line?
+      .NS(1),            // Number of power supplies
+      .CHAOS(0),         // generates random full logic when set
+      .CTRLW(1),         // width of asic ctrl interface
+      .TESTW(1))         // width of asic test interface
+      tx_fifo(
+         .wr_full          (txfifo_full),
+         .rd_dout          (txfifo_dout),
+         .rd_empty         (txfifo_empty),
+         .clk              (clk),
+         .nreset           (nreset),
+         .clear            (1'b0),
+         .vss              (1'b0),
+         .vdd              (1'b1),
+         .chaosmode        (1'b0),
+         .ctrl             (1'b0),
+         .test             (1'b0),
+         .wr_en            (txfifo_write),
+         .wr_din           (loc_wrdata[7:0]),
+         .rd_en            (txfifo_read));
+
+   // UART CLK
+   always @(posedge clk or negedge nreset) begin
+      if (~nreset) begin
+         clk_i <= 0;
+      end else begin
+         clk_i <= clk_i + 1;
+         if (clk_i == UART_CLKDIV[$clog2(UART_CLKDIV):0]) begin
+            clk_i <= 0;
+         end
+      end
+   end
+
+   // RX logic
+   always @(posedge clk or negedge nreset) begin
+      if (~nreset) begin
+         //$display("clkdiv old=%d new=%d", UART_CLKDIV_OLD, UART_CLKDIV);
+         rx_state <= 0;
+         rx_data <= 0;
+         reset_sync <= 1;
+      end else begin
+         if (rx_pad == 1) begin
+            reset_sync <= 0;
+         end
+         if (clk_en) begin
+            if (rx_state == STATE_START) begin
+               /* Wait for start bit.  */
+               if (rx_pad == 0 && !reset_sync) begin
+                  rx_state <= rx_state + 1;
+               end
+            end else if (rx_state <= 8) begin
+               rx_state <= rx_state + 1;
+               rx_data <= rx_next_data;
+               if (rx_state == STATE_STOP) begin
+                  /* STOP.  */
+                  rx_state <= 0;
+                  rx_data <= 0;
+                  if (UART_DEBUG) begin
+                     $write("%c", rx_next_data); $fflush();
+                  end
+               end
+            end
+
+            if (UART_DEBUG) begin
+               $display("state=%d rx=%d data=%x.%x", rx_state, rx_pad, rx_data, rx_next_data);
+            end
+         end
+      end
+   end
+
+   // TX logic
+   reg [$clog2(STATE_STOP2):0] tx_state;
+   reg [8-1:0]                 tx_data;
+
+   reg tx;
+   assign tx_pad = tx;
+   always @(posedge clk or negedge nreset) begin
+      if (~nreset) begin
+         tx_state <= 0;
+         tx_xmit <= 0;
+         tx <= 1;
+      end else begin
+         if (txfifo_read) begin
+            tx_xmit <= 1;
+            tx_data <= txfifo_dout;
+         end
+
+         if (clk_en && tx_xmit) begin
+            tx_state <= tx_state + 1;
+
+            if (tx_state == STATE_START) begin
+                tx <= 0;
+            end else if (tx_state == STATE_STOP2) begin
+                tx_xmit <= 0;
+                tx_state <= STATE_START;
+                tx <= 1;
+            end else begin
+                tx <= tx_data[tx_state - 1];
+            end
+         end
+      end
+   end
+endmodule
+
+`default_nettype wire

switchboard/verilog/common/umi_gpio.v

@@ -0,0 +1,236 @@
+// Universal Memory Interface (UMI) GPIO
+
+// The output gpio_out is "updated" by any write to this module, and the
+// input "gpio_in" is read out by any read from this module.
+
+// Copyright (c) 2024 Zero ASIC Corporation
+// This code is licensed under Apache License 2.0 (see LICENSE for details)
+
+module umi_gpio #(
+    parameter integer DW=256,
+    parameter integer AW=64,
+    parameter integer CW=32,
+    parameter integer IWIDTH=32,
+    parameter integer OWIDTH=32,
+    parameter [OWIDTH-1:0] INITVAL=0
+) (
+    input clk,
+    input nreset,
+
+    // GPIO interface
+    input [IWIDTH-1:0] gpio_in,
+    output [OWIDTH-1:0] gpio_out,
+
+    // UMI inbound interface
+    input           udev_req_valid,
+    input [CW-1:0]  udev_req_cmd,
+    input [AW-1:0]  udev_req_dstaddr,
+    input [AW-1:0]  udev_req_srcaddr,
+    input [DW-1:0]  udev_req_data,
+    output          udev_req_ready,
+
+    // UMI outbound interface
+    output          udev_resp_valid,
+    output [CW-1:0] udev_resp_cmd,
+    output [AW-1:0] udev_resp_dstaddr,
+    output [AW-1:0] udev_resp_srcaddr,
+    output [DW-1:0] udev_resp_data,
+    input           udev_resp_ready
+);
+
+    `include "umi_messages.vh"
+
+    // interpret incoming packet
+
+    wire [4:0]   req_opcode;
+    wire [2:0]   req_size;
+    wire [7:0]   req_len;
+    wire [7:0]   req_atype;
+    wire [3:0]   req_qos;
+    wire [1:0]   req_prot;
+    wire         req_eom;
+    wire         req_eof;
+    wire         req_ex;
+    wire [1:0]   req_user;
+    wire [23:0]  req_user_extended;
+    wire [1:0]   req_err;
+    wire [4:0]   req_hostid;
+
+    /* verilator lint_off PINMISSING */
+    umi_unpack #(
+        .CW(CW)
+    ) umi_unpack_i (
+        .packet_cmd(udev_req_cmd),
+        .cmd_opcode(req_opcode),
+        .cmd_size(req_size),
+        .cmd_len(req_len),
+        .cmd_atype(req_atype),
+        .cmd_qos(req_qos),
+        .cmd_prot(req_prot),
+        .cmd_eom(req_eom),
+        .cmd_eof(req_eof),
+        .cmd_ex(req_ex),
+        .cmd_user(req_user),
+        .cmd_user_extended(req_user_extended),
+        .cmd_err(req_err),
+        .cmd_hostid(req_hostid)
+    );
+    /* verilator lint_on PINMISSING */
+
+    wire req_cmd_read;
+    assign req_cmd_read = (req_opcode == UMI_REQ_READ) ? 1'b1 : 1'b0;
+
+    wire req_cmd_write;
+    assign req_cmd_write = (req_opcode == UMI_REQ_WRITE) ? 1'b1 : 1'b0;
+
+    wire req_cmd_posted;
+    assign req_cmd_posted = (req_opcode == UMI_REQ_POSTED) ? 1'b1 : 1'b0;
+
+    // form outgoing packet (which can only be a read response)
+
+    reg [4:0]   resp_opcode;
+    reg [2:0]   resp_size;
+    reg [7:0]   resp_len;
+    reg [7:0]   resp_atype;
+    reg [3:0]   resp_qos;
+    reg [1:0]   resp_prot;
+    reg         resp_eom;
+    reg         resp_eof;
+    reg         resp_ex;
+    reg [1:0]   resp_user;
+    reg [23:0]  resp_user_extended;
+    reg [1:0]   resp_err;
+    reg [4:0]   resp_hostid;
+
+    umi_pack #(
+        .CW(CW)
+    ) umi_pack_i (
+        .cmd_opcode(resp_opcode),
+        .cmd_size(resp_size),
+        .cmd_len(resp_len),
+        .cmd_atype(resp_atype),
+        .cmd_prot(resp_prot),
+        .cmd_qos(resp_qos),
+        .cmd_eom(resp_eom),
+        .cmd_eof(resp_eof),
+        .cmd_user(resp_user),
+        .cmd_err(resp_err),
+        .cmd_ex(resp_ex),
+        .cmd_hostid(resp_hostid),
+        .cmd_user_extended(resp_user_extended),
+        .packet_cmd(udev_resp_cmd)
+    );
+
+    // main logic
+
+    reg [OWIDTH-1:0] gpio_out_r;
+    assign gpio_out = gpio_out_r;
+
+    reg [31:0] read_bytes_remaining;
+    reg resp_in_progress;
+    reg [AW-1:0] read_dstaddr;
+
+    wire [31:0] nbytes;
+    assign nbytes = (resp_in_progress ? read_bytes_remaining :
+        ({24'd0, req_len} + 32'd1)*(32'd1<<{29'd0, req_size}));
+
+    wire [31:0] flit_bytes;
+    assign flit_bytes = (nbytes <= (DW/8)) ? nbytes : (DW/8);
+
+    wire [31:0] resp_len_req_next32 = {((flit_bytes >> req_size) - 32'd1)};
+    wire [7:0] resp_len_req_next = resp_len_req_next32[7:0];
+
+    wire [31:0] resp_len_next32 = {((flit_bytes >> resp_size) - 32'd1)};
+    wire [7:0] resp_len_next = resp_len_next32[7:0];
+
+    reg active;
+    assign udev_req_ready = (active
+        && (!((udev_resp_valid && (!udev_resp_ready)) || resp_in_progress)));
+
+    reg udev_resp_valid_r;
+    assign udev_resp_valid = udev_resp_valid_r;
+
+    reg [DW-1:0] udev_resp_data_r;
+    assign udev_resp_data = udev_resp_data_r;
+
+    reg [AW-1:0] udev_resp_dstaddr_r;
+    assign udev_resp_dstaddr = udev_resp_dstaddr_r;
+
+    integer i;
+
+    always @(posedge clk or negedge nreset) begin
+        if (!nreset) begin
+            active <= 1'b0;
+        end else begin
+            active <= 1'b1;
+        end
+    end
+
+    always @(posedge clk or negedge nreset) begin
+        if (!nreset) begin
+            gpio_out_r <= INITVAL;
+            read_bytes_remaining <= 'd0;
+            resp_in_progress <= 1'b0;
+            read_dstaddr <= 'd0;
+            udev_resp_valid_r <= 1'b0;
+        end else if (udev_req_valid && udev_req_ready) begin
+            if (req_cmd_posted || req_cmd_write) begin
+                for (i=0; i<flit_bytes; i=i+1) begin
+                    gpio_out_r[(i[$clog2(OWIDTH)-1:0]+udev_req_dstaddr[$clog2(OWIDTH)-1:0])*8 +: 8]
+                        <= udev_req_data[i*8 +: 8];
+                end
+                if (req_cmd_write) begin
+                    resp_opcode <= UMI_RESP_WRITE;
+                    udev_resp_valid_r <= 1'b1;
+                end
+            end else if (req_cmd_read) begin
+                for (i=0; i<flit_bytes; i=i+1) begin
+                    udev_resp_data_r[i*8 +: 8] <=
+                      gpio_in[(i[$clog2(IWIDTH)-1:0]+udev_req_dstaddr[$clog2(IWIDTH)-1:0])*8 +: 8];
+                end
+                resp_opcode <= UMI_RESP_READ;
+                udev_resp_valid_r <= 1'b1;
+                if (nbytes > (DW/8)) begin
+                    resp_in_progress <= 1'b1;
+                    read_bytes_remaining <= nbytes - flit_bytes;
+                    read_dstaddr <= udev_req_dstaddr + {{(AW-32){1'b0}}, flit_bytes};
+                end
+            end
+
+            // pass through data
+            resp_size <= req_size;
+            resp_len <= resp_len_req_next;
+            resp_atype <= req_atype;
+            resp_prot <= req_prot;
+            resp_qos <= req_qos;
+            resp_eom <= (nbytes <= (DW/8)) ? 1'b1 : 1'b0;
+            resp_eof <= req_eof;
+            resp_user <= req_user;
+            resp_err <= req_err;
+            resp_ex <= req_ex;
+            resp_hostid <= req_hostid;
+            resp_user_extended <= req_user_extended;
+            udev_resp_dstaddr_r <= udev_req_srcaddr;
+        end else if (udev_resp_valid && udev_resp_ready) begin
+            if (resp_in_progress) begin
+                if (read_bytes_remaining == 'd0) begin
+                    udev_resp_valid_r <= 1'b0;
+                    resp_in_progress <= 1'b0;
+                end else begin
+                    read_bytes_remaining <= read_bytes_remaining - flit_bytes;
+                    resp_len <= resp_len_next;
+                    udev_resp_dstaddr_r <= udev_resp_dstaddr + {{(AW-32){1'b0}}, flit_bytes};
+                    read_dstaddr <= read_dstaddr + {{(AW-32){1'b0}}, flit_bytes};
+                    resp_eom <= (read_bytes_remaining <= (DW/8)) ? 1'b1 : 1'b0;
+                    for (i=0; i<flit_bytes; i=i+1) begin
+                        udev_resp_data_r[i*8 +: 8] <=
+                          gpio_in[(i[$clog2(IWIDTH)-1:0]+read_dstaddr[$clog2(IWIDTH)-1:0])*8 +: 8];
+                    end
+                end
+            end else begin
+                udev_resp_valid_r <= 1'b0;
+            end
+        end
+    end
+
+endmodule

switchboard/verilog/fpga/axi_reader.sv

@@ -0,0 +1,82 @@
+// Copyright (c) 2024 Zero ASIC Corporation
+// This code is licensed under Apache License 2.0 (see LICENSE for details)
+
+`default_nettype none
+
+module axi_reader #(
+    parameter ID_WIDTH = 16
+) (
+    input wire clk,
+
+    input wire rvalid,
+    input wire [63:0] raddr,
+    output wire [511:0] rdata,
+    output wire rready,
+
+    output wire [ID_WIDTH-1:0] m_axi_arid,
+    output wire [63:0] m_axi_araddr,
+    output wire [7:0] m_axi_arlen,
+    output wire [2:0] m_axi_arsize,
+    output wire m_axi_arvalid,
+    input wire m_axi_arready,
+
+    input wire [ID_WIDTH-1:0] m_axi_rid,
+    input wire [511:0] m_axi_rdata,
+    input wire [1:0] m_axi_rresp,
+    input wire m_axi_rlast,
+    input wire m_axi_rvalid,
+    output wire m_axi_rready
+);
+
+    localparam [1:0] STATE_IDLE = 2'd0;
+    localparam [1:0] STATE_READ = 2'd1;
+    localparam [1:0] STATE_WAIT_RESP = 2'd2;
+
+    reg [1:0] state = STATE_IDLE;
+    reg [1:0] state_next;
+
+    always @(*) begin
+        state_next = state;
+        case (state)
+            STATE_IDLE: begin
+                if (rvalid) begin
+                    state_next = STATE_READ;
+                end
+            end
+
+            STATE_READ: begin
+                if (m_axi_arready) begin
+                    state_next = STATE_WAIT_RESP;
+                end
+            end
+
+            STATE_WAIT_RESP: begin
+                if (m_axi_rvalid) begin
+                    state_next = STATE_IDLE;
+                end
+            end
+
+            // Shouldn't reach here
+            default: state_next = 2'bXX;
+        endcase
+    end
+
+    always @(posedge clk) begin
+        state <= state_next;
+    end
+
+    // Pulse rready after we get response
+    assign rready = (state == STATE_WAIT_RESP) && (state_next == STATE_IDLE);
+    assign rdata = m_axi_rdata;
+
+    assign m_axi_arid = {ID_WIDTH{1'b0}};
+    assign m_axi_araddr = raddr;
+    assign m_axi_arlen = 8'b0;
+    assign m_axi_arsize = 3'd6;
+    assign m_axi_arvalid = (state == STATE_READ);
+
+    assign m_axi_rready = (state == STATE_WAIT_RESP);
+
+endmodule
+
+`default_nettype wire

switchboard/verilog/fpga/axi_writer.sv

@@ -0,0 +1,111 @@
+// Copyright (c) 2024 Zero ASIC Corporation
+// This code is licensed under Apache License 2.0 (see LICENSE for details)
+
+`default_nettype none
+
+module axi_writer #(
+    parameter ID_WIDTH = 16
+) (
+    input wire clk,
+
+    input wire wvalid,
+    input wire [63:0] waddr,
+    input wire [63:0] wstrb,
+    input wire [511:0] wdata,
+    output wire wready,
+
+    output wire [ID_WIDTH-1:0] m_axi_awid,
+    output wire [63:0] m_axi_awaddr,
+    output wire [7:0] m_axi_awlen,
+    output wire [2:0] m_axi_awsize,
+    output wire m_axi_awvalid,
+    input wire m_axi_awready,
+
+    output wire [511:0] m_axi_wdata,
+    output wire [63:0] m_axi_wstrb,
+    output wire m_axi_wlast,
+    output wire m_axi_wvalid,
+    input wire m_axi_wready,
+
+    input wire [ID_WIDTH-1:0] m_axi_bid,
+    input wire [1:0] m_axi_bresp,
+    input wire m_axi_bvalid,
+    output wire m_axi_bready
+);
+
+    localparam [1:0] STATE_IDLE = 2'd0;
+    localparam [1:0] STATE_WR_ADDR_DATA = 2'd1;
+    localparam [1:0] STATE_WAIT_RESP = 2'd2;
+
+    reg [1:0] state = STATE_IDLE;
+    reg [1:0] state_next;
+
+    reg awready_seen = 1'b0;
+    reg wready_seen = 1'b0;
+
+    always @(*) begin
+        state_next = state;
+        case (state)
+            STATE_IDLE: begin
+                if (wvalid) begin
+                    state_next = STATE_WR_ADDR_DATA;
+                end
+            end
+
+            // m_axi_awready and m_axi_wready may wait for both m_axi_awvalid
+            // and m_axi_wvalid to assert before asserting, so we raise both
+            // valid signals and wait for both ready signals.
+            STATE_WR_ADDR_DATA: begin
+                if ((m_axi_awready || awready_seen) && (m_axi_wready || wready_seen)) begin
+                    state_next = STATE_WAIT_RESP;
+                end
+            end
+
+            STATE_WAIT_RESP: begin
+                if (m_axi_bvalid) begin
+                    state_next = STATE_IDLE;
+                end
+            end
+
+            default: begin
+                // would only get here if state contains "X"
+                // or "Z" bits.  this might be a bit more
+                // conservative than necessary...
+                state_next = 2'bxx;
+            end
+        endcase
+    end
+
+    always @(posedge clk) begin
+        state <= state_next;
+    end
+
+    always @(posedge clk) begin
+        if (state == STATE_IDLE) begin
+            awready_seen <= 1'b0;
+            wready_seen <= 1'b0;
+        end else begin
+            awready_seen <= m_axi_awready || awready_seen;
+            wready_seen <= m_axi_wready || wready_seen;
+        end
+    end
+
+    // Pulse wready after we get response
+    assign wready = (state == STATE_WAIT_RESP) && (state_next == STATE_IDLE);
+
+    assign m_axi_awid = {ID_WIDTH{1'b0}};
+    assign m_axi_awaddr = waddr;
+    assign m_axi_awlen = 8'b0;
+    assign m_axi_awsize = 3'd6;
+    assign m_axi_awvalid = (state == STATE_WR_ADDR_DATA) && (!awready_seen);
+
+    assign m_axi_wdata = wdata;
+    assign m_axi_wstrb = wstrb;
+    assign m_axi_wlast = 1'b1;
+    assign m_axi_wvalid = (state == STATE_WR_ADDR_DATA) && (!wready_seen);
+
+    assign m_axi_bready = (state == STATE_WAIT_RESP);
+
+endmodule
+
+`default_nettype wire