switchboard-hw 0.3.0__cp314-cp314-macosx_10_15_x86_64.whl

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Files changed (99) hide show
  1. _switchboard.cpython-314-darwin.so +0 -0
  2. switchboard/__init__.py +24 -0
  3. switchboard/ams.py +668 -0
  4. switchboard/apb.py +278 -0
  5. switchboard/autowrap.py +1000 -0
  6. switchboard/axi.py +571 -0
  7. switchboard/axil.py +348 -0
  8. switchboard/bitvector.py +112 -0
  9. switchboard/cmdline.py +142 -0
  10. switchboard/cpp/Makefile +13 -0
  11. switchboard/cpp/bitutil.h +39 -0
  12. switchboard/cpp/pagemap.h +91 -0
  13. switchboard/cpp/pciedev.h +86 -0
  14. switchboard/cpp/router.cc +89 -0
  15. switchboard/cpp/spsc_queue.h +267 -0
  16. switchboard/cpp/switchboard.hpp +257 -0
  17. switchboard/cpp/switchboard_pcie.hpp +234 -0
  18. switchboard/cpp/switchboard_tlm.hpp +98 -0
  19. switchboard/cpp/umilib.h +144 -0
  20. switchboard/cpp/umilib.hpp +113 -0
  21. switchboard/cpp/umisb.hpp +364 -0
  22. switchboard/cpp/xyce.hpp +90 -0
  23. switchboard/deps/__init__.py +0 -0
  24. switchboard/deps/verilog_axi.py +23 -0
  25. switchboard/dpi/__init__.py +0 -0
  26. switchboard/dpi/switchboard_dpi.cc +119 -0
  27. switchboard/dpi/switchboard_dpi.py +13 -0
  28. switchboard/dpi/xyce_dpi.cc +43 -0
  29. switchboard/gpio.py +108 -0
  30. switchboard/icarus.py +85 -0
  31. switchboard/loopback.py +157 -0
  32. switchboard/network.py +714 -0
  33. switchboard/pytest_plugin.py +11 -0
  34. switchboard/sbdesign.py +55 -0
  35. switchboard/sbdut.py +744 -0
  36. switchboard/sbtcp.py +345 -0
  37. switchboard/sc/__init__.py +0 -0
  38. switchboard/sc/morty/__init__.py +0 -0
  39. switchboard/sc/morty/uniquify.py +67 -0
  40. switchboard/sc/sed/__init__.py +0 -0
  41. switchboard/sc/sed/sed_remove.py +47 -0
  42. switchboard/sc/standalone_netlist_flow.py +25 -0
  43. switchboard/switchboard.py +53 -0
  44. switchboard/test_util.py +46 -0
  45. switchboard/uart_xactor.py +66 -0
  46. switchboard/umi.py +793 -0
  47. switchboard/util.py +131 -0
  48. switchboard/verilator/__init__.py +0 -0
  49. switchboard/verilator/config.vlt +13 -0
  50. switchboard/verilator/testbench.cc +143 -0
  51. switchboard/verilator/verilator.py +13 -0
  52. switchboard/verilator_run.py +31 -0
  53. switchboard/verilog/__init__.py +0 -0
  54. switchboard/verilog/common/__init__.py +0 -0
  55. switchboard/verilog/common/common.py +26 -0
  56. switchboard/verilog/common/switchboard.vh +429 -0
  57. switchboard/verilog/common/uart_xactor.sv +247 -0
  58. switchboard/verilog/common/umi_gpio.v +236 -0
  59. switchboard/verilog/fpga/__init__.py +0 -0
  60. switchboard/verilog/fpga/axi_reader.sv +82 -0
  61. switchboard/verilog/fpga/axi_writer.sv +111 -0
  62. switchboard/verilog/fpga/config_registers.sv +249 -0
  63. switchboard/verilog/fpga/fpga.py +21 -0
  64. switchboard/verilog/fpga/include/sb_queue_regmap.vh +21 -0
  65. switchboard/verilog/fpga/include/spsc_queue.vh +7 -0
  66. switchboard/verilog/fpga/memory_fault.sv +40 -0
  67. switchboard/verilog/fpga/sb_fpga_queues.sv +416 -0
  68. switchboard/verilog/fpga/sb_rx_fpga.sv +303 -0
  69. switchboard/verilog/fpga/sb_tx_fpga.sv +294 -0
  70. switchboard/verilog/fpga/umi_fpga_queues.sv +146 -0
  71. switchboard/verilog/sim/__init__.py +0 -0
  72. switchboard/verilog/sim/auto_stop_sim.sv +25 -0
  73. switchboard/verilog/sim/perf_meas_sim.sv +97 -0
  74. switchboard/verilog/sim/queue_to_sb_sim.sv +176 -0
  75. switchboard/verilog/sim/queue_to_umi_sim.sv +66 -0
  76. switchboard/verilog/sim/sb_apb_m.sv +146 -0
  77. switchboard/verilog/sim/sb_axi_m.sv +199 -0
  78. switchboard/verilog/sim/sb_axil_m.sv +180 -0
  79. switchboard/verilog/sim/sb_axil_s.sv +180 -0
  80. switchboard/verilog/sim/sb_clk_gen.sv +89 -0
  81. switchboard/verilog/sim/sb_jtag_rbb_sim.sv +148 -0
  82. switchboard/verilog/sim/sb_rx_sim.sv +55 -0
  83. switchboard/verilog/sim/sb_to_queue_sim.sv +196 -0
  84. switchboard/verilog/sim/sb_tx_sim.sv +55 -0
  85. switchboard/verilog/sim/switchboard_sim.py +49 -0
  86. switchboard/verilog/sim/umi_rx_sim.sv +61 -0
  87. switchboard/verilog/sim/umi_to_queue_sim.sv +66 -0
  88. switchboard/verilog/sim/umi_tx_sim.sv +61 -0
  89. switchboard/verilog/sim/xyce_intf.sv +67 -0
  90. switchboard/vpi/switchboard_vpi.cc +431 -0
  91. switchboard/vpi/xyce_vpi.cc +200 -0
  92. switchboard/warn.py +14 -0
  93. switchboard/xyce.py +27 -0
  94. switchboard_hw-0.3.0.dist-info/METADATA +303 -0
  95. switchboard_hw-0.3.0.dist-info/RECORD +99 -0
  96. switchboard_hw-0.3.0.dist-info/WHEEL +6 -0
  97. switchboard_hw-0.3.0.dist-info/entry_points.txt +6 -0
  98. switchboard_hw-0.3.0.dist-info/licenses/LICENSE +190 -0
  99. switchboard_hw-0.3.0.dist-info/top_level.txt +2 -0
switchboard/verilog/common/switchboard.vh ADDED
@@ -0,0 +1,429 @@
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+ // Swithboard utility macros.
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+
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+ // Copyright (c) 2024 Zero ASIC Corporation
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+ // This code is licensed under Apache License 2.0 (see LICENSE for details)
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+
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+ `ifndef SWITCHBOARD_VH_
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+ `define SWITCHBOARD_VH_
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+
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+ // ref: https://stackoverflow.com/a/15376637
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+ `define STRINGIFY(x) `"x`"
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+
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+ `define SB_UMI_WIRES(signal, dw, cw, aw) \
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+ wire signal``_valid; \
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+ wire [((cw)-1): 0] signal``_cmd; \
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+ wire [((aw)-1): 0] signal``_dstaddr; \
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+ wire [((aw)-1): 0] signal``_srcaddr; \
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+ wire [((dw)-1): 0] signal``_data; \
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+ wire signal``_ready
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+
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+ // alias for SB_UMI_WIRES, keep for backwards compatibility
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+ `define UMI_PORT_WIRES_WIDTHS(prefix, dw, cw, aw) \
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+ `SB_UMI_WIRES(prefix, dw, cw, aw)
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+
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+ `define QUEUE_TO_UMI_SIM(signal, dw, cw, aw, file, vldmode=1, clk_signal=clk, reset_sig=1'b0) \
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+ queue_to_umi_sim #( \
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+ .VALID_MODE_DEFAULT(vldmode), \
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+ .DW(dw), \
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+ .CW(cw), \
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+ .AW(aw), \
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+ .FILE(file) \
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+ ) signal``_sb_inst ( \
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+ .clk(clk_signal), \
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+ .reset(reset_sig), \
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+ .data(signal``_data), \
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+ .srcaddr(signal``_srcaddr), \
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+ .dstaddr(signal``_dstaddr), \
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+ .cmd(signal``_cmd), \
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+ .ready(signal``_ready), \
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+ .valid(signal``_valid) \
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+ )
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+
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+ `define UMI_TO_QUEUE_SIM(signal, dw, cw, aw, file, rdymode=1, clk_signal=clk, reset_sig=1'b0) \
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+ umi_to_queue_sim #( \
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+ .READY_MODE_DEFAULT(rdymode), \
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+ .DW(dw), \
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+ .CW(cw), \
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+ .AW(aw), \
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+ .FILE(file) \
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+ ) signal``_sb_inst ( \
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+ .clk(clk_signal), \
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+ .reset(reset_sig), \
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+ .data(signal``_data), \
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+ .srcaddr(signal``_srcaddr), \
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+ .dstaddr(signal``_dstaddr), \
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+ .cmd(signal``_cmd), \
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+ .ready(signal``_ready), \
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+ .valid(signal``_valid) \
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+ )
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+
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+ `define SB_UMI_CONNECT(a, b) \
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+ .a``_valid(b``_valid), \
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+ .a``_cmd(b``_cmd), \
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+ .a``_dstaddr(b``_dstaddr), \
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+ .a``_srcaddr(b``_srcaddr), \
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+ .a``_data(b``_data), \
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+ .a``_ready(b``_ready)
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+
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+ `define SB_TIEOFF_UMI_INPUT(a) \
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+ .a``_valid(1'b0), \
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+ .a``_cmd(), \
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+ .a``_dstaddr(), \
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+ .a``_srcaddr(), \
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+ .a``_data(), \
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+ .a``_ready()
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+
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+ `define SB_TIEOFF_UMI_OUTPUT(a) \
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+ .a``_valid(), \
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+ .a``_cmd(), \
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+ .a``_dstaddr(), \
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+ .a``_srcaddr(), \
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+ .a``_data(), \
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+ .a``_ready(1'b0)
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+
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+ `define SWITCHBOARD_SIM_PORT(prefix, dw, cw=32, aw=64) \
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+ `SB_UMI_WIRES(prefix``_req, dw, cw, aw); \
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+ `SB_UMI_WIRES(prefix``_resp, dw, cw, aw); \
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+ `QUEUE_TO_UMI_SIM(prefix``_req, dw, cw, aw, `"prefix``_req.q`"); \
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+ `UMI_TO_QUEUE_SIM(prefix``_resp, dw, cw, aw, `"prefix``_resp.q`")
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+
90
+ `define SB_UMI_PORT(signal, dw, cw=32, aw=64, i, o) \
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+ i signal``_valid, \
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+ i [((cw)-1): 0] signal``_cmd, \
93
+ i [((aw)-1): 0] signal``_dstaddr, \
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+ i [((aw)-1): 0] signal``_srcaddr, \
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+ i [((dw)-1): 0] signal``_data, \
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+ o signal``_ready
97
+
98
+ `define SB_UMI_INPUT(signal, dw, cw=32, aw=64) \
99
+ `SB_UMI_PORT(signal, dw, cw, aw, input, output)
100
+
101
+ `define SB_UMI_OUTPUT(signal, dw, cw=32, aw=64) \
102
+ `SB_UMI_PORT(signal, dw, cw, aw, output, input)
103
+
104
+ `define SB_WIRES(signal, dw) \
105
+ wire [((dw)-1):0] signal``_data; \
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+ wire [31:0] signal``_dest; \
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+ wire signal``_last; \
108
+ wire signal``_valid; \
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+ wire signal``_ready
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+
111
+ `define SB_CONNECT(a, b) \
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+ .a``_data(b``_data), \
113
+ .a``_dest(b``_dest), \
114
+ .a``_last(b``_last), \
115
+ .a``_valid(b``_valid), \
116
+ .a``_ready(b``_ready)
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+
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+ `define SB_PORT(signal, dw, i, o) \
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+ i wire [((dw)-1):0] signal``_data, \
120
+ i wire [31:0] signal``_dest, \
121
+ i wire signal``_last, \
122
+ i wire signal``_valid, \
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+ o wire signal``_ready
124
+
125
+ `define SB_INPUT(signal, dw) \
126
+ `SB_PORT(signal, dw, input, output)
127
+
128
+ `define SB_OUTPUT(signal, dw) \
129
+ `SB_PORT(signal, dw, output, input)
130
+
131
+ `define SB_TO_QUEUE_SIM(signal, dw, file, rdymode=1, clk_signal=clk) \
132
+ sb_to_queue_sim #( \
133
+ .READY_MODE_DEFAULT(rdymode), \
134
+ .DW(dw), \
135
+ .FILE(file) \
136
+ ) signal``_sb_inst ( \
137
+ .clk(clk_signal), \
138
+ .data(signal``_data), \
139
+ .dest(signal``_dest), \
140
+ .last(signal``_last), \
141
+ .ready(signal``_ready), \
142
+ .valid(signal``_valid) \
143
+ )
144
+
145
+ `define QUEUE_TO_SB_SIM(signal, dw, file, vldmode=1, clk_signal=clk) \
146
+ queue_to_sb_sim #( \
147
+ .VALID_MODE_DEFAULT(vldmode), \
148
+ .DW(dw), \
149
+ .FILE(file) \
150
+ ) signal``_sb_inst ( \
151
+ .clk(clk_signal), \
152
+ .data(signal``_data), \
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+ .dest(signal``_dest), \
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+ .last(signal``_last), \
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+ .ready(signal``_ready), \
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+ .valid(signal``_valid) \
157
+ )
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+
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+ `define SB_APB_WIRES(signal, dw, aw) \
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+ wire signal``_psel; \
161
+ wire signal``_penable; \
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+ wire signal``_pwrite; \
163
+ wire [2:0] signal``_pprot; \
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+ wire [((aw)-1):0] signal``_paddr; \
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+ wire [((dw)/8)-1:0] signal``_pstrb; \
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+ wire [((dw)-1):0] signal``_pwdata; \
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+ wire [((dw)-1):0] signal``_prdata; \
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+ wire signal``_pready; \
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+ wire signal``_pslverr
170
+
171
+ `define SB_APB_M(signal, dw, aw, file, vldmode=1, clk_signal=clk, rst_signal=1'b0) \
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+ sb_apb_m #( \
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+ .DATA_WIDTH(dw), \
174
+ .ADDR_WIDTH(aw), \
175
+ .VALID_MODE_DEFAULT(vldmode), \
176
+ .FILE(file) \
177
+ ) signal``_sb_inst ( \
178
+ .clk(clk_signal), \
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+ .reset(rst_signal), \
180
+ .m_apb_psel(signal``_psel), \
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+ .m_apb_penable(signal``_penable), \
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+ .m_apb_pwrite(signal``_pwrite), \
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+ .m_apb_pprot(signal``_pprot), \
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+ .m_apb_paddr(signal``_paddr), \
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+ .m_apb_pstrb(signal``_pstrb), \
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+ .m_apb_pwdata(signal``_pwdata), \
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+ .m_apb_prdata(signal``_prdata), \
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+ .m_apb_pready(signal``_pready), \
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+ .m_apb_pslverr(signal``_pslverr) \
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+ )
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+
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+ `define SB_AXIL_WIRES(signal, dw, aw) \
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+ wire [((aw)-1):0] signal``_awaddr; \
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+ wire [2:0] signal``_awprot; \
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+ wire signal``_awvalid; \
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+ wire signal``_awready; \
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+ wire [((dw)-1):0] signal``_wdata; \
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+ wire [(((dw)/8)-1):0] signal``_wstrb; \
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+ wire signal``_wvalid; \
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+ wire signal``_wready; \
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+ wire [1:0] signal``_bresp; \
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+ wire signal``_bvalid; \
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+ wire signal``_bready; \
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+ wire [((aw)-1):0] signal``_araddr; \
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+ wire [2:0] signal``_arprot; \
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+ wire signal``_arvalid; \
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+ wire signal``_arready; \
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+ wire [((dw))-1:0] signal``_rdata; \
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+ wire [1:0] signal``_rresp; \
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+ wire signal``_rvalid; \
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+ wire signal``_rready
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+
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+ `define SB_AXIL_CONNECT(a, b) \
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+ .a``_awaddr(b``_awaddr), \
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+ .a``_awprot(b``_awprot), \
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+ .a``_awvalid(b``_awvalid), \
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+ .a``_awready(b``_awready), \
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+ .a``_wdata(b``_wdata), \
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+ .a``_wstrb(b``_wstrb), \
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+ .a``_wvalid(b``_wvalid), \
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+ .a``_wready(b``_wready), \
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+ .a``_bresp(b``_bresp), \
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+ .a``_bvalid(b``_bvalid), \
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+ .a``_bready(b``_bready), \
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+ .a``_araddr(b``_araddr), \
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+ .a``_arprot(b``_arprot), \
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+ .a``_arvalid(b``_arvalid), \
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+ .a``_arready(b``_arready), \
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+ .a``_rdata(b``_rdata), \
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+ .a``_rresp(b``_rresp), \
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+ .a``_rvalid(b``_rvalid), \
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+ .a``_rready(b``_rready)
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+
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+ `define SB_AXIL(dir, signal, dw, aw, file, vldmode=1, rdymode=1, clk_signal=clk, rst_signal=1'b0) \
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+ sb_axil_``dir #( \
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+ .DATA_WIDTH(dw), \
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+ .ADDR_WIDTH(aw), \
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+ .VALID_MODE_DEFAULT(vldmode), \
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+ .READY_MODE_DEFAULT(rdymode), \
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+ .FILE(file) \
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+ ) signal``_sb_inst ( \
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+ .clk(clk_signal), \
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+ .reset(rst_signal), \
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+ .dir``_axil_awaddr(signal``_awaddr), \
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+ .dir``_axil_awprot(signal``_awprot), \
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+ .dir``_axil_awvalid(signal``_awvalid), \
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+ .dir``_axil_awready(signal``_awready), \
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+ .dir``_axil_wdata(signal``_wdata), \
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+ .dir``_axil_wstrb(signal``_wstrb), \
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+ .dir``_axil_wvalid(signal``_wvalid), \
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+ .dir``_axil_wready(signal``_wready), \
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+ .dir``_axil_bresp(signal``_bresp), \
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+ .dir``_axil_bvalid(signal``_bvalid), \
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+ .dir``_axil_bready(signal``_bready), \
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+ .dir``_axil_araddr(signal``_araddr), \
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+ .dir``_axil_arprot(signal``_arprot), \
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+ .dir``_axil_arvalid(signal``_arvalid), \
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+ .dir``_axil_arready(signal``_arready), \
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+ .dir``_axil_rdata(signal``_rdata), \
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+ .dir``_axil_rresp(signal``_rresp), \
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+ .dir``_axil_rvalid(signal``_rvalid), \
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+ .dir``_axil_rready(signal``_rready) \
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+ )
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+
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+ `define SB_AXIL_M(signal, dw, aw, file, vldmode=1, rdymode=1, clk_signal=clk, rst_signal=1'b0) \
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+ `SB_AXIL(m, signal, dw, aw, file, vldmode, rdymode, clk_signal, rst_signal)
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+
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+ `define SB_AXIL_S(signal, dw, aw, file, vldmode=1, rdymode=1, clk_signal=clk, rst_signal=1'b0) \
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+ `SB_AXIL(s, signal, dw, aw, file, vldmode, rdymode, clk_signal, rst_signal)
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+
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+ `define SB_AXI_WIRES(signal, dw, aw, idw) \
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+ wire [(idw)-1:0] signal``_awid; \
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+ wire [(aw)-1:0] signal``_awaddr; \
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+ wire [7:0] signal``_awlen; \
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+ wire [2:0] signal``_awsize; \
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+ wire [1:0] signal``_awburst; \
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+ wire signal``_awlock; \
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+ wire [3:0] signal``_awcache; \
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+ wire [2:0] signal``_awprot; \
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+ wire signal``_awvalid; \
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+ wire signal``_awready; \
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+ wire [(dw)-1:0] signal``_wdata; \
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+ wire [((dw)/8)-1:0] signal``_wstrb; \
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+ wire signal``_wlast; \
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+ wire signal``_wvalid; \
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+ wire signal``_wready; \
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+ wire [(idw)-1:0] signal``_bid; \
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+ wire [1:0] signal``_bresp; \
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+ wire signal``_bvalid; \
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+ wire signal``_bready; \
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+ wire [(idw)-1:0] signal``_arid; \
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+ wire [(aw)-1:0] signal``_araddr; \
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+ wire [7:0] signal``_arlen; \
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+ wire [2:0] signal``_arsize; \
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+ wire [1:0] signal``_arburst; \
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+ wire signal``_arlock; \
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+ wire [3:0] signal``_arcache; \
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+ wire [2:0] signal``_arprot; \
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+ wire signal``_arvalid; \
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+ wire signal``_arready; \
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+ wire [(idw)-1:0] signal``_rid; \
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+ wire [(dw)-1:0] signal``_rdata; \
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+ wire [1:0] signal``_rresp; \
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+ wire signal``_rlast; \
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+ wire signal``_rvalid; \
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+ wire signal``_rready;
307
+
308
+ `define SB_AXI_CONNECT(a, b) \
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+ .a``_awid(b``_awid), \
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+ .a``_awaddr(b``_awaddr), \
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+ .a``_awlen(b``_awlen), \
312
+ .a``_awsize(b``_awsize), \
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+ .a``_awburst(b``_awburst), \
314
+ .a``_awlock(b``_awlock), \
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+ .a``_awcache(b``_awcache), \
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+ .a``_awprot(b``_awprot), \
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+ .a``_awvalid(b``_awvalid), \
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+ .a``_awready(b``_awready), \
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+ .a``_wdata(b``_wdata), \
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+ .a``_wstrb(b``_wstrb), \
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+ .a``_wlast(b``_wlast), \
322
+ .a``_wvalid(b``_wvalid), \
323
+ .a``_wready(b``_wready), \
324
+ .a``_bid(b``_bid), \
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+ .a``_bresp(b``_bresp), \
326
+ .a``_bvalid(b``_bvalid), \
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+ .a``_bready(b``_bready), \
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+ .a``_arid(b``_arid), \
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+ .a``_araddr(b``_araddr), \
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+ .a``_arlen(b``_arlen), \
331
+ .a``_arsize(b``_arsize), \
332
+ .a``_arburst(b``_arburst), \
333
+ .a``_arlock(b``_arlock), \
334
+ .a``_arcache(b``_arcache), \
335
+ .a``_arprot(b``_arprot), \
336
+ .a``_arvalid(b``_arvalid), \
337
+ .a``_arready(b``_arready), \
338
+ .a``_rid(b``_rid), \
339
+ .a``_rdata(b``_rdata), \
340
+ .a``_rresp(b``_rresp), \
341
+ .a``_rlast(b``_rlast), \
342
+ .a``_rvalid(b``_rvalid), \
343
+ .a``_rready(b``_rready)
344
+
345
+ `define SB_AXI(dir, signal, dw, aw, idw, file, vldmode=1, rdymode=1, clk_signal=clk) \
346
+ sb_axi_``dir #( \
347
+ .DATA_WIDTH(dw), \
348
+ .ADDR_WIDTH(aw), \
349
+ .ID_WIDTH(idw), \
350
+ .VALID_MODE_DEFAULT(vldmode), \
351
+ .READY_MODE_DEFAULT(rdymode), \
352
+ .FILE(file) \
353
+ ) signal``_sb_inst ( \
354
+ .clk(clk_signal), \
355
+ .dir``_axi_awid(signal``_awid), \
356
+ .dir``_axi_awaddr(signal``_awaddr), \
357
+ .dir``_axi_awlen(signal``_awlen), \
358
+ .dir``_axi_awsize(signal``_awsize), \
359
+ .dir``_axi_awburst(signal``_awburst), \
360
+ .dir``_axi_awlock(signal``_awlock), \
361
+ .dir``_axi_awcache(signal``_awcache), \
362
+ .dir``_axi_awprot(signal``_awprot), \
363
+ .dir``_axi_awvalid(signal``_awvalid), \
364
+ .dir``_axi_awready(signal``_awready), \
365
+ .dir``_axi_wdata(signal``_wdata), \
366
+ .dir``_axi_wstrb(signal``_wstrb), \
367
+ .dir``_axi_wlast(signal``_wlast), \
368
+ .dir``_axi_wvalid(signal``_wvalid), \
369
+ .dir``_axi_wready(signal``_wready), \
370
+ .dir``_axi_bid(signal``_bid), \
371
+ .dir``_axi_bresp(signal``_bresp), \
372
+ .dir``_axi_bvalid(signal``_bvalid), \
373
+ .dir``_axi_bready(signal``_bready), \
374
+ .dir``_axi_arid(signal``_arid), \
375
+ .dir``_axi_araddr(signal``_araddr), \
376
+ .dir``_axi_arlen(signal``_arlen), \
377
+ .dir``_axi_arsize(signal``_arsize), \
378
+ .dir``_axi_arburst(signal``_arburst), \
379
+ .dir``_axi_arlock(signal``_arlock), \
380
+ .dir``_axi_arcache(signal``_arcache), \
381
+ .dir``_axi_arprot(signal``_arprot), \
382
+ .dir``_axi_arvalid(signal``_arvalid), \
383
+ .dir``_axi_arready(signal``_arready), \
384
+ .dir``_axi_rid(signal``_rid), \
385
+ .dir``_axi_rdata(signal``_rdata), \
386
+ .dir``_axi_rresp(signal``_rresp), \
387
+ .dir``_axi_rlast(signal``_rlast), \
388
+ .dir``_axi_rvalid(signal``_rvalid), \
389
+ .dir``_axi_rready(signal``_rready) \
390
+ )
391
+
392
+ `define SB_AXI_M(signal, dw, aw, idw, file, vldmode=1, rdymode=1, clk_signal=clk) \
393
+ `SB_AXI(m, signal, dw, aw, idw, file, vldmode, rdymode, clk_signal)
394
+
395
+ `define SB_AXI_S(signal, dw, aw, idw, file, vldmode=1, rdymode=1, clk_signal=clk) \
396
+ `SB_AXI(s, signal, dw, aw, idw, file, vldmode, rdymode, clk_signal)
397
+
398
+ `define SB_CREATE_CLOCK(clk_signal, period=10e-9, duty_cycle=0.5, max_rate=-1, start_delay=-1) \
399
+ wire clk_signal; \
400
+ \
401
+ sb_clk_gen #( \
402
+ .DEFAULT_PERIOD(period), \
403
+ .DEFAULT_DUTY_CYCLE(duty_cycle), \
404
+ .DEFAULT_MAX_RATE(max_rate), \
405
+ .DEFAULT_START_DELAY(start_delay) \
406
+ ) clk_signal``_sb_inst ( \
407
+ .clk(clk_signal) \
408
+ );
409
+
410
+ `define SB_SETUP_PROBES(toplevel=testbench) \
411
+ `ifdef SB_TRACE \
412
+ string dumpfile_sb_value; \
413
+ initial begin \
414
+ if ($test$plusargs("trace")) begin \
415
+ if ($value$plusargs("dumpfile=%s", dumpfile_sb_value)) begin \
416
+ $dumpfile(dumpfile_sb_value); \
417
+ end else begin \
418
+ `ifdef SB_TRACE_FST \
419
+ $dumpfile("testbench.fst"); \
420
+ `else \
421
+ $dumpfile("testbench.vcd"); \
422
+ `endif \
423
+ end \
424
+ $dumpvars(0, ``toplevel); \
425
+ end \
426
+ end \
427
+ `endif
428
+
429
+ `endif // SWITCHBOARD_VH_