switchboard-hw 0.3.0__cp314-cp314-macosx_10_15_x86_64.whl

switchboard/verilog/fpga/sb_tx_fpga.sv

@@ -0,0 +1,294 @@
+// Copyright (c) 2024 Zero ASIC Corporation
+// This code is licensed under Apache License 2.0 (see LICENSE for details)
+
+`default_nettype none
+
+module sb_tx_fpga #(
+    parameter ID_WIDTH = 16,
+    // must be <= 448 (512-64)
+    parameter DW = 416
+) (
+    input wire clk,
+    input wire en,
+    input wire reset,
+
+    input wire [DW-1:0] data,
+    input wire [31:0] dest,
+    input wire last,
+    output wire ready,
+    input wire valid,
+
+    input wire [63:0] cfg_base_addr,
+    input wire [31:0] cfg_capacity,
+
+    output wire status_idle,
+
+    output wire [ID_WIDTH-1:0] m_axi_awid,
+    output wire [63:0] m_axi_awaddr,
+    output wire [7:0] m_axi_awlen,
+    output wire [2:0] m_axi_awsize,
+    output wire m_axi_awvalid,
+    input wire m_axi_awready,
+
+    output wire [511:0] m_axi_wdata,
+    output wire [63:0] m_axi_wstrb,
+    output wire m_axi_wlast,
+    output wire m_axi_wvalid,
+    input wire m_axi_wready,
+
+    input wire [ID_WIDTH-1:0] m_axi_bid,
+    input wire [1:0] m_axi_bresp,
+    input wire m_axi_bvalid,
+    output wire m_axi_bready,
+
+    output wire [ID_WIDTH-1:0] m_axi_arid,
+    output wire [63:0] m_axi_araddr,
+    output wire [7:0] m_axi_arlen,
+    output wire [2:0] m_axi_arsize,
+    output wire m_axi_arvalid,
+    input wire m_axi_arready,
+
+    input wire [ID_WIDTH-1:0] m_axi_rid,
+    input wire [511:0] m_axi_rdata,
+    input wire [1:0] m_axi_rresp,
+    input wire m_axi_rlast,
+    input wire m_axi_rvalid,
+    output wire m_axi_rready
+);
+
+    `include "spsc_queue.vh"
+
+    /*
+     * Main state machine
+     */
+
+    localparam [2:0] STATE_IDLE = 3'd0;
+    localparam [2:0] STATE_RD_TAIL = 3'd1;
+    localparam [2:0] STATE_WR_PACKET = 3'd2;
+    localparam [2:0] STATE_WR_HEAD = 3'd3;
+    localparam [2:0] STATE_FAULT = 3'd4;
+
+    wire wvalid;
+    reg [63:0] waddr;
+    reg [63:0] wstrb;
+    reg [511:0] wdata;
+    wire wready;
+
+    wire rvalid;
+    reg [63:0] raddr;
+    wire rready;
+    wire [511:0] rdata;
+
+    wire full;
+    wire fault;
+
+    reg [511:0] packet_to_write;
+
+    reg [2:0] state = STATE_IDLE;
+    reg [2:0] state_next;
+
+    always @(*) begin
+        state_next = state;
+        case (state)
+            STATE_IDLE: begin
+                if (valid && en) begin
+                    if (!full) begin
+                        state_next = STATE_WR_PACKET;
+                    end else begin
+                        state_next = STATE_RD_TAIL;
+                    end
+                end
+            end
+
+            STATE_RD_TAIL: begin
+                if (rready && !en) begin
+                    state_next = STATE_IDLE;
+                end else if (!full) begin
+                    state_next = STATE_WR_PACKET;
+                end
+            end
+
+            STATE_WR_PACKET: begin
+                // This state doesn't force a transition to IDLE on !en, since
+                // we always need to write the head after writing the packet.
+                if (wready) begin
+                    state_next = STATE_WR_HEAD;
+                end
+            end
+
+            STATE_WR_HEAD: begin
+                if (wready) begin
+                    state_next = STATE_IDLE;
+                end
+            end
+
+            STATE_FAULT: begin
+                state_next = STATE_FAULT;
+            end
+
+            // Shouldn't reach here
+            default: state_next = 3'bXXX;
+        endcase
+    end
+
+    always @(posedge clk) begin
+        if (reset) begin
+            state <= STATE_IDLE;
+        end else if (fault) begin
+            state <= STATE_FAULT;
+        end else begin
+            state <= state_next;
+        end
+    end
+
+    /*
+     * Queue state logic
+     */
+
+    reg [31:0] head = 32'd0;
+    reg [31:0] tail = 32'd0;
+    wire [31:0] head_next;
+    wire [31:0] tail_next;
+    wire [31:0] head_incr;
+
+    assign head_incr = (head + 32'd1 == cfg_capacity) ? 32'd0 : (head + 32'd1);
+    assign head_next = (state == STATE_WR_PACKET && wready) ? head_incr : head;
+
+    assign tail_next = (state == STATE_RD_TAIL && rready) ? rdata[31:0] : tail;
+
+    always @(posedge clk) begin
+        if (reset) begin
+            head <= 32'd0;
+            tail <= 32'd0;
+        end else begin
+            head <= head_next;
+            tail <= tail_next;
+        end
+    end
+
+    // Use *_next signals here to speed up state machine transitions.
+    assign full = (head_incr == tail_next);
+
+    // Addresses within queue
+    wire [63:0] head_addr;
+    wire [63:0] tail_addr;
+    assign head_addr = cfg_base_addr + HEAD_OFFSET;
+    assign tail_addr = cfg_base_addr + TAIL_OFFSET;
+
+    wire wvalid_checked;
+    wire [63:0] fault_addr;
+    memory_fault write_checker(
+        .clk(clk),
+        .reset(reset),
+
+        .access_valid_in(wvalid),
+        .access_addr(waddr),
+        .access_valid_out(wvalid_checked),
+
+        .base_legal_addr(cfg_base_addr),
+        .legal_length(cfg_capacity * PACKET_SIZE + PACKET_OFFSET),
+
+        .fault(fault),
+        .fault_addr(fault_addr)
+    );
+
+    /*
+     * Simple W/R interface to AXI bus
+     */
+
+    axi_writer #(
+        .ID_WIDTH(ID_WIDTH)
+    ) writer (
+        .wvalid(wvalid_checked),
+        .*
+    );
+
+    axi_reader #(
+        .ID_WIDTH(ID_WIDTH)
+    ) reader (
+        .*
+    );
+
+    assign wvalid = (state == STATE_WR_HEAD) || (state == STATE_WR_PACKET);
+    always @(*) begin
+        waddr = 64'd0;
+        wstrb = 64'd0;
+        wdata = 512'd0;
+        if (state == STATE_WR_HEAD) begin
+            waddr = head_addr;
+            wstrb = 64'hff;
+            wdata = {480'd0, head};
+        end else if (state == STATE_WR_PACKET) begin
+            waddr = cfg_base_addr + PACKET_OFFSET + (head * PACKET_SIZE);
+            wstrb = {{((512-64-DW)/8){1'b0}}, {((DW+64)/8){1'b1}}};
+            wdata = packet_to_write;
+        end
+    end
+    assign rvalid = (state == STATE_RD_TAIL);
+    always @(*) begin
+        raddr = 64'd0;
+        if (state == STATE_RD_TAIL) begin
+            raddr = tail_addr;
+        end
+    end
+
+    /*
+     * SB handshaking
+     */
+
+    always @(posedge clk) begin
+        if (reset) begin
+            packet_to_write <= 512'd0;
+        end else if (valid && ready) begin
+            packet_to_write <= {{(512-64-DW){1'b0}}, data, 31'd0, last, dest};
+        end
+    end
+    assign ready = (state == STATE_IDLE) && en;
+
+    assign status_idle = state == STATE_IDLE;
+
+`ifdef DEBUG
+   ila_0 ILA_RD (
+                   .clk    (clk),
+                   .probe0 (m_axi_arvalid),
+                   .probe1 (m_axi_araddr),
+                   .probe2 (m_axi_arready),
+                   .probe3 (m_axi_rvalid),
+                   .probe4 (m_axi_rdata[63:0]),
+                   .probe5 (m_axi_rready)
+                   );
+
+   ila_0 ILA_WR (
+                   .clk    (clk),
+                   .probe0 (m_axi_awvalid),
+                   .probe1 (m_axi_awaddr),
+                   .probe2 (m_axi_awready),
+                   .probe3 (m_axi_wvalid),
+                   .probe4 (m_axi_wdata[63:0]),
+                   .probe5 (m_axi_wready)
+                   );
+
+   ila_0 ILA_STATE (
+                   .clk    (clk),
+                   .probe0 (en),
+                   .probe1 ({head, tail}),
+                   .probe2 (valid),
+                   .probe3 (ready),
+                   .probe4 ({state, head_incr}),
+                   .probe5 (full)
+                   );
+
+   ila_0 ILA_FAULT (
+                   .clk    (clk),
+                   .probe0 (fault),
+                   .probe1 (fault_addr),
+                   .probe2 (),
+                   .probe3 (),
+                   .probe4 (),
+                   .probe5 ()
+                   );
+`endif
+
+endmodule
+
+`default_nettype wire

switchboard/verilog/fpga/umi_fpga_queues.sv

@@ -0,0 +1,146 @@
+// Copyright (c) 2024 Zero ASIC Corporation
+// This code is licensed under Apache License 2.0 (see LICENSE for details)
+
+`default_nettype none
+
+module umi_fpga_queues #(
+    parameter NUM_RX_QUEUES = 1,
+    parameter NUM_TX_QUEUES = 1,
+    parameter NUM_USER_REGS = 1,
+
+    parameter integer DW=256,
+    parameter integer AW=64,
+    parameter integer CW=32
+) (
+    input wire clk,
+    input wire nreset,
+
+    // UMI interfaces
+    output wire [NUM_RX_QUEUES*DW-1:0] rx_data,
+    output wire [NUM_RX_QUEUES*AW-1:0] rx_srcaddr,
+    output wire [NUM_RX_QUEUES*AW-1:0] rx_dstaddr,
+    output wire [NUM_RX_QUEUES*CW-1:0] rx_cmd,
+    input wire [NUM_RX_QUEUES-1:0] rx_ready,
+    output wire [NUM_RX_QUEUES-1:0] rx_valid,
+
+    input wire [NUM_TX_QUEUES*DW-1:0] tx_data,
+    input wire [NUM_TX_QUEUES*AW-1:0] tx_srcaddr,
+    input wire [NUM_TX_QUEUES*AW-1:0] tx_dstaddr,
+    input wire [NUM_TX_QUEUES*CW-1:0] tx_cmd,
+    output wire [NUM_TX_QUEUES-1:0] tx_ready,
+    input wire [NUM_TX_QUEUES-1:0] tx_valid,
+
+    output wire [(NUM_USER_REGS > 0 ? NUM_USER_REGS : 1)*32-1:0] cfg_user,
+
+    // AXI manager interface for memory access
+    output wire [15:0] m_axi_awid,
+    output wire [63:0] m_axi_awaddr,
+    output wire [7:0] m_axi_awlen,
+    output wire [2:0] m_axi_awsize,
+    output wire [18:0] m_axi_awuser,
+    output wire m_axi_awvalid,
+    input wire m_axi_awready,
+
+    output wire [511:0] m_axi_wdata,
+    output wire [63:0] m_axi_wstrb,
+    output wire m_axi_wlast,
+    output wire m_axi_wvalid,
+    input wire m_axi_wready,
+
+    input wire [15:0] m_axi_bid,
+    input wire [1:0] m_axi_bresp,
+    input wire m_axi_bvalid,
+    output wire m_axi_bready,
+
+    output wire [15:0] m_axi_arid,
+    output wire [63:0] m_axi_araddr,
+    output wire [7:0] m_axi_arlen,
+    output wire [2:0] m_axi_arsize,
+    output wire [18:0] m_axi_aruser,
+    output wire m_axi_arvalid,
+    input wire m_axi_arready,
+
+    input wire [15:0] m_axi_rid,
+    input wire [511:0] m_axi_rdata,
+    input wire [1:0] m_axi_rresp,
+    input wire m_axi_rlast,
+    input wire m_axi_rvalid,
+    output wire m_axi_rready,
+
+    // AXIL subordinate interface for config registers
+    input wire s_axil_awvalid,
+    input wire [31:0] s_axil_awaddr,
+    output wire s_axil_awready,
+
+    input wire s_axil_wvalid,
+    input wire [31:0] s_axil_wdata,
+    input wire [3:0] s_axil_wstrb,
+    output wire s_axil_wready,
+
+    output wire s_axil_bvalid,
+    output wire [1:0] s_axil_bresp,
+    input wire s_axil_bready,
+
+    input wire s_axil_arvalid,
+    input wire [31:0] s_axil_araddr,
+    output wire s_axil_arready,
+
+    output wire s_axil_rvalid,
+    output wire [31:0] s_axil_rdata,
+    output wire [1:0] s_axil_rresp,
+    input wire s_axil_rready
+);
+
+    localparam SB_DW = DW + AW + AW + CW;
+
+    // Pack/unpack UMI signals to/from Switchboard packets
+
+    genvar i;
+    wire [NUM_RX_QUEUES*SB_DW-1:0] sb_rx_data;
+    for (i = 0; i < NUM_RX_QUEUES; i = i + 1) begin
+        assign rx_cmd[i*CW+:CW] = sb_rx_data[i*SB_DW + CW-1:i*SB_DW];
+        assign rx_dstaddr[i*AW+:AW] = sb_rx_data[i*SB_DW + AW+CW-1:i*SB_DW + CW];
+        assign rx_srcaddr[i*AW+:AW] = sb_rx_data[i*SB_DW + AW+AW+CW-1:i*SB_DW + AW+CW];
+        assign rx_data[i*DW+:DW] = sb_rx_data[i*SB_DW + DW+AW+AW+CW-1:i*SB_DW + AW+AW+CW];
+    end
+
+    wire [NUM_TX_QUEUES*SB_DW-1:0] sb_tx_data;
+    wire [NUM_TX_QUEUES*32-1:0] sb_tx_dest;
+    wire [NUM_TX_QUEUES-1:0] sb_tx_last;
+    for (i = 0; i < NUM_TX_QUEUES; i = i + 1) begin
+        assign sb_tx_data[i*SB_DW+:SB_DW] = {
+            tx_data[i*DW+:DW], tx_srcaddr[i*AW+:AW], tx_dstaddr[i*AW+:AW], tx_cmd[i*CW+:CW]
+        };
+        assign sb_tx_dest[i*32+:32] = {16'h0000, tx_dstaddr[i*AW+55:i*AW+40]};
+        assign sb_tx_last[i] = tx_cmd[(i*CW)+22];
+    end
+
+    sb_fpga_queues #(
+        .NUM_RX_QUEUES(NUM_RX_QUEUES),
+        .NUM_TX_QUEUES(NUM_TX_QUEUES),
+        .NUM_USER_REGS(NUM_USER_REGS),
+
+        .DW(SB_DW)
+    ) sb_fpga_queues_i (
+        .clk(clk),
+        .nreset(nreset),
+
+        .rx_data(sb_rx_data),
+        .rx_dest(),
+        .rx_last(),
+        .rx_ready(rx_ready),
+        .rx_valid(rx_valid),
+
+        .tx_data(sb_tx_data),
+        .tx_dest(sb_tx_dest),
+        .tx_last(sb_tx_last),
+        .tx_ready(tx_ready),
+        .tx_valid(tx_valid),
+
+        // Pass thru AXI ports implicitly
+        .*
+    );
+
+endmodule
+
+`default_nettype wire

switchboard/verilog/sim/auto_stop_sim.sv

@@ -0,0 +1,25 @@
+// Copyright (c) 2024 Zero ASIC Corporation
+// This code is licensed under Apache License 2.0 (see LICENSE for details)
+
+`default_nettype none
+
+module auto_stop_sim #(
+    parameter CYCLES=50000000
+) (
+    input clk
+);
+
+    integer i=0;
+
+    always @(posedge clk) begin
+        if (i >= CYCLES) begin
+            $display("STOPPING SIMULATION");
+            $finish;
+        end else begin
+            i <= i + 1;
+        end
+    end
+
+endmodule
+
+`default_nettype wire

switchboard/verilog/sim/perf_meas_sim.sv

@@ -0,0 +1,97 @@
+// Copyright (c) 2024 Zero ASIC Corporation
+// This code is licensed under Apache License 2.0 (see LICENSE for details)
+
+`default_nettype none
+
+module perf_meas_sim #(
+    // verilog_lint: waive-start parameter-name-style
+    parameter integer default_cycles_per_meas=0,
+    parameter real max_report_time=3.0,
+    parameter real min_report_time=0.3,
+    parameter integer search_factor=2
+    // verilog_lint: waive-stop parameter-name-style
+) (
+    input clk
+);
+    `ifdef __ICARUS__
+        `define SB_EXT_FUNC(x) $``x``
+        `define SB_START_FUNC task
+        `define SB_END_FUNC endtask
+    `else
+        `define SB_EXT_FUNC(x) x
+        `define SB_START_FUNC function automatic void
+        `define SB_END_FUNC endfunction
+
+        import "DPI-C" function void pi_time_taken(output real t);
+    `endif
+
+    // internal signals
+    real t;
+    real sim_rate;
+    integer cycles_per_meas=default_cycles_per_meas;
+    integer total_clock_cycles=0;
+    string sim_name;
+
+    `SB_START_FUNC init(input integer n, input string name="");
+        cycles_per_meas = n;
+        sim_name = name;
+        /* verilator lint_off IGNOREDRETURN */
+        `SB_EXT_FUNC(pi_time_taken)(t);
+        /* verilator lint_on IGNOREDRETURN */
+    `SB_END_FUNC
+
+    initial begin
+        /* verilator lint_off IGNOREDRETURN */
+        `SB_EXT_FUNC(pi_time_taken)(t);  // discard first result since it is invalid
+        /* verilator lint_on IGNOREDRETURN */
+    end
+
+    always @(posedge clk) begin
+        if (cycles_per_meas == 0) begin
+            // do nothing...
+        end else if (total_clock_cycles >= cycles_per_meas) begin
+            /* verilator lint_off IGNOREDRETURN */
+            `SB_EXT_FUNC(pi_time_taken)(t);
+            /* verilator lint_on IGNOREDRETURN */
+            if (sim_name != "") begin
+                $write("%s: ", sim_name);
+            end
+            sim_rate = (1.0*total_clock_cycles)/t;
+            if (sim_rate < 1.0e3) begin
+                $display("Simulation rate: %0.3f Hz", sim_rate);
+            end else if (sim_rate < 1.0e6) begin
+                $display("Simulation rate: %0.3f kHz", 1e-3*sim_rate);
+            end else begin
+                $display("Simulation rate: %0.3f MHz", 1e-6*sim_rate);
+            end
+            total_clock_cycles <= 0;
+
+            // update number of cycles in between updates appropriately
+            if (t < min_report_time) begin
+                // reporting in too frequent, increase cycles_per_meas
+                // to report less frequently
+                cycles_per_meas = cycles_per_meas * search_factor;
+            end else if (t > max_report_time) begin
+                // reporting in too infrequent, decrease cycles_per_meas
+                // to report more frequently
+                cycles_per_meas = cycles_per_meas / search_factor;
+                if (cycles_per_meas == 0) begin
+                    // but don't let cycles_per_meas drop to zero,
+                    // since that disables performance measurement
+                    cycles_per_meas = 1;
+                end
+            end
+        end else begin
+            total_clock_cycles <= total_clock_cycles + 1;
+        end
+    end
+
+    // clean up macros
+
+    `undef SB_EXT_FUNC
+    `undef SB_START_FUNC
+    `undef SB_END_FUNC
+
+endmodule
+
+`default_nettype wire