siliconcompiler 0.28.8__py3-none-any.whl → 0.29.0__py3-none-any.whl

siliconcompiler/tools/openroad/scripts/apr/sc_init_floorplan.tcl

@@ -0,0 +1,333 @@
+###############################
+# Reading SC Schema
+###############################
+
+source ./sc_manifest.tcl > /dev/null
+
+###############################
+# Task Preamble
+###############################
+
+set sc_refdir [sc_cfg_tool_task_get refdir]
+source -echo "$sc_refdir/apr/preamble.tcl"
+
+###############################
+# FLOORPLANNING
+###############################
+
+###############################
+# Setup Global Connections
+###############################
+
+if { [sc_cfg_tool_task_exists {file} global_connect] } {
+    foreach global_connect [sc_cfg_tool_task_get {file} global_connect] {
+        puts "Sourcing global connect configuration: ${global_connect}"
+        source $global_connect
+    }
+}
+
+###############################
+# Initialize floorplan
+###############################
+
+if { [sc_cfg_exists input asic floorplan] } {
+    set def [lindex [sc_cfg_get input asic floorplan] 0]
+    puts "Reading floorplan DEF: ${def}"
+    read_def -floorplan_initialize $def
+} else {
+    set sc_libtype [sc_cfg_get library $sc_mainlib asic libarch]
+    set sc_site [lindex [sc_cfg_get library $sc_mainlib asic site $sc_libtype] 0]
+
+    #NOTE: assuming a two tuple value as lower left, upper right
+    set sc_diearea [sc_cfg_get constraint outline]
+    set sc_corearea [sc_cfg_get constraint corearea]
+    if {
+        $sc_diearea != "" &&
+        $sc_corearea != ""
+    } {
+        # Use die and core sizes
+        set sc_diesize "[lindex $sc_diearea 0] [lindex $sc_diearea 1]"
+        set sc_coresize "[lindex $sc_corearea 0] [lindex $sc_corearea 1]"
+
+        initialize_floorplan -die_area $sc_diesize \
+            -core_area $sc_coresize \
+            -site $sc_site
+    } else {
+        # Use density
+        initialize_floorplan -aspect_ratio [sc_cfg_get constraint aspectratio] \
+            -utilization [sc_cfg_get constraint density] \
+            -core_space [sc_cfg_get constraint coremargin] \
+            -site $sc_site
+    }
+}
+
+puts "Floorplan information:"
+puts "Die area: [ord::get_die_area]"
+puts "Core area: [ord::get_core_area]"
+
+###############################
+# Track Creation
+###############################
+
+# source tracks from file if found, else else use schema entries
+if { [sc_cfg_exists library $sc_mainlib option file openroad_tracks] } {
+    set tracks_file [lindex [sc_cfg_get library $sc_mainlib option file openroad_tracks] 0]
+    puts "Sourcing tracks configuration: ${tracks_file}"
+    source $tracks_file
+} else {
+    make_tracks
+}
+
+set do_automatic_pins 1
+if {
+    [sc_cfg_tool_task_exists file padring] &&
+    [llength [sc_cfg_tool_task_get file padring]] > 0
+} {
+    set do_automatic_pins 0
+
+    ###############################
+    # Generate pad ring
+    ###############################
+    foreach padring_file [sc_cfg_tool_task_get {file} padring] {
+        puts "Sourcing padring configuration: ${padring_file}"
+        source $padring_file
+    }
+
+    if { [sc_design_has_unplaced_pads] } {
+        foreach inst [[ord::get_db_block] getInsts] {
+            if { [$inst isPad] && ![$inst isFixed] } {
+                utl::warn FLW 1 "[$inst getName] has not been placed"
+            }
+        }
+        utl::error FLW 1 "Design contains unplaced IOs"
+    }
+}
+
+###############################
+# Pin placement
+###############################
+set sc_hpinmetal [sc_cfg_get pdk $sc_pdk {var} $sc_tool pin_layer_horizontal $sc_stackup]
+set sc_hpinmetal [sc_get_layer_name $sc_hpinmetal]
+set sc_vpinmetal [sc_cfg_get pdk $sc_pdk {var} $sc_tool pin_layer_vertical $sc_stackup]
+set sc_vpinmetal [sc_get_layer_name $sc_vpinmetal]
+
+if { [sc_cfg_exists constraint pin] } {
+    source "[sc_cfg_tool_task_get file sc_pin_constraint]"
+
+    proc sc_pin_print { arg } { utl::warn FLW 1 $arg }
+    proc sc_pin_layer_select { pin } {
+        global sc_hpinmetal
+        global sc_vpinmetal
+
+        set layer [sc_cfg_get constraint pin $pin layer]
+        if { [llength $layer] != 0 } {
+            return [sc_get_layer_name [lindex $layer 0]]
+        }
+        set side [sc_cfg_get constraint pin $pin side]
+        if { [llength $side] != 0 } {
+            switch -regexp $side {
+                "1|3" {
+                    return [lindex $sc_hpinmetal 0]
+                }
+                "2|4" {
+                    return [lindex $sc_vpinmetal 0]
+                }
+                default {
+                    utl::error FLW 1 "Side number ($side) on $pin is not supported."
+                }
+            }
+        }
+
+        utl::error FLW 1 "$pin needs to either specify side or layer parameter."
+    }
+    sc_collect_pin_constraints \
+        pin_placement \
+        pin_order \
+        sc_pin_layer_select \
+        sc_pin_print
+
+    foreach pin $pin_placement {
+        set layer [sc_pin_layer_select $pin]
+        set place [sc_cfg_get constraint pin $pin placement]
+
+        set x_loc [lindex $place 0]
+        set y_loc [lindex $place 1]
+
+        place_pin -pin_name $pin \
+            -layer $layer \
+            -location "$x_loc $y_loc" \
+            -force_to_die_boundary
+    }
+
+    dict for {side layer_pins} $pin_order {
+        set edge_length 0
+        switch -regexp $side {
+            "1|3" {
+                set edge_length \
+                    [expr { [lindex [ord::get_die_area] 3] - [lindex [ord::get_die_area] 1] }]
+            }
+            "2|4" {
+                set edge_length \
+                    [expr { [lindex [ord::get_die_area] 2] - [lindex [ord::get_die_area] 0] }]
+            }
+            default {
+                utl::error FLW 1 "Side number ($side) is not supported."
+            }
+        }
+
+        dict for {layer ordered_pins} $layer_pins {
+            set spacing [expr { $edge_length / ([llength $ordered_pins] + 1) }]
+
+            for { set i 0 } { $i < [llength $ordered_pins] } { incr i } {
+                set name [lindex $ordered_pins $i]
+                switch -regexp $side {
+                    "1" {
+                        set x_loc [lindex [ord::get_die_area] 1]
+                        set y_loc [expr { ($i + 1) * $spacing }]
+                    }
+                    "2" {
+                        set x_loc [expr { ($i + 1) * $spacing }]
+                        set y_loc [lindex [ord::get_die_area] 3]
+                    }
+                    "3" {
+                        set x_loc [lindex [ord::get_die_area] 2]
+                        set y_loc [expr { ($i + 1) * $spacing }]
+                    }
+                    "4" {
+                        set x_loc [expr { ($i + 1) * $spacing }]
+                        set y_loc [lindex [ord::get_die_area] 1]
+                    }
+                }
+
+                place_pin -pin_name $name \
+                    -layer $layer \
+                    -location "$x_loc $y_loc" \
+                    -force_to_die_boundary
+            }
+        }
+    }
+}
+
+###############################
+# Macro placement
+###############################
+
+# If manual macro placement is provided use that first
+if { [sc_cfg_exists constraint component] } {
+    set sc_snap_strategy [sc_cfg_tool_task_get {var} ifp_snap_strategy]
+
+    if { $sc_snap_strategy == "manufacturing_grid" } {
+        if { [[ord::get_db_tech] hasManufacturingGrid] } {
+            set x_grid [[ord::get_db_tech] getManufacturingGrid]
+            set y_grid $x_grid
+        } else {
+            utl::warn FLW 1 \
+                "Manufacturing grid is not defined, defaulting to 'none' snapping strategy"
+            set x_grid 1
+            set y_grid 1
+        }
+    } elseif { $sc_snap_strategy == "site" } {
+        set x_grid 0
+        set y_grid 0
+        foreach row [[ord::get_db_block] getRows] {
+            set site [$row getSite]
+            if { [$site getClass] == "PAD" } {
+                continue
+            }
+
+            set site_height [$site getHeight]
+            set site_width [$site getWidth]
+            if { $y_grid == 0 } {
+                set y_grid $site_height
+            } elseif { $y_grid > $site_height } {
+                set y_grid $site_height
+            }
+            if { $x_grid == 0 } {
+                set x_grid $site_width
+            } elseif { $x_grid > $site_width } {
+                set x_grid $site_width
+            }
+        }
+    } else {
+        set x_grid 1
+        set y_grid 1
+    }
+
+    if { $x_grid == 0 || $y_grid == 0 } {
+        utl::warn FLW 1 "Unable to determine snapping grid."
+        set x_grid 1
+        set y_grid 1
+    }
+
+    set x_grid [ord::dbu_to_microns $x_grid]
+    set y_grid [ord::dbu_to_microns $y_grid]
+
+    dict for {name params} [sc_cfg_get constraint component] {
+        set location [dict get $params placement]
+        set rotation [sc_convert_rotation [dict get $params rotation]]
+
+        if { [dict exists $params partname] } {
+            set cell [dict get $params partname]
+        } else {
+            set cell ""
+        }
+        if { [llength [dict get $params halo]] != 0 } {
+            utl::warn FLW 1 "Halo is not supported in OpenROAD"
+        }
+
+        set inst [[ord::get_db_block] findInst $name]
+        if { $inst == "NULL" } {
+            utl::warn FLW 1 "Could not find instance: $name"
+
+            if { $cell == "" } {
+                utl::error FLW 1 \
+                    "Unable to create instance for $name as the cell has not been specified"
+            }
+        } else {
+            set cell ""
+        }
+
+        set x_loc [expr { round([lindex $location 0] / $x_grid) * $x_grid }]
+        set y_loc [expr { round([lindex $location 1] / $y_grid) * $y_grid }]
+
+        set place_inst_args []
+        if { $cell != "" } {
+            lappend place_inst_args -cell $cell
+        }
+
+        place_inst \
+            -name $name \
+            -location "$x_loc $y_loc" \
+            -orient $rotation \
+            -status FIRM \
+            {*}$place_inst_args
+    }
+
+    sc_print_macro_information
+}
+
+if { $do_automatic_pins } {
+    ###############################
+    # Automatic Random Pin Placement
+    ###############################
+
+    sc_pin_placement -random
+}
+
+###############################
+# Remove buffers inserted by synthesis
+###############################
+
+if { [lindex [sc_cfg_tool_task_get var remove_synth_buffers] 0] == "true" } {
+    remove_buffers
+}
+
+if { [lindex [sc_cfg_tool_task_get var remove_dead_logic] 0] == "true" } {
+    eliminate_dead_logic
+}
+
+###############################
+# Task Postamble
+###############################
+
+source -echo "$sc_refdir/apr/postamble.tcl"

siliconcompiler/tools/openroad/scripts/apr/sc_macro_placement.tcl

@@ -0,0 +1,123 @@
+###############################
+# Reading SC Schema
+###############################
+
+source ./sc_manifest.tcl > /dev/null
+
+###############################
+# Task Preamble
+###############################
+
+set sc_refdir [sc_cfg_tool_task_get refdir]
+source -echo "$sc_refdir/apr/preamble.tcl"
+
+# Need to check if we have any macros before performing macro placement,
+# since we get an error otherwise.
+if { [sc_design_has_unplaced_macros] } {
+    if { [lindex [sc_cfg_tool_task_get var rtlmp_enable] 0] == "true" } {
+        ###############################
+        # Macro placement
+        ###############################
+
+        lassign [sc_cfg_tool_task_get var macro_place_halo] halo_x halo_y
+
+        set rtlmp_args []
+        set rtlmp_max_levels [lindex [sc_cfg_tool_task_get var rtlmp_max_levels] 0]
+        if { $rtlmp_max_levels != "" } {
+            lappend rtlmp_args -max_num_level $rtlmp_max_levels
+        }
+        set rtlmp_min_instances [lindex [sc_cfg_tool_task_get var rtlmp_min_instances] 0]
+        if { $rtlmp_min_instances != "" } {
+            lappend rtlmp_args -min_num_inst $rtlmp_min_instances
+        }
+        set rtlmp_max_instances [lindex [sc_cfg_tool_task_get var rtlmp_max_instances] 0]
+        if { $rtlmp_max_instances != "" } {
+            lappend rtlmp_args -max_num_inst $rtlmp_max_instances
+        }
+        set rtlmp_min_macros [lindex [sc_cfg_tool_task_get var rtlmp_min_macros] 0]
+        if { $rtlmp_min_macros != "" } {
+            lappend rtlmp_args -min_num_macro $rtlmp_min_macros
+        }
+        set rtlmp_max_macros [lindex [sc_cfg_tool_task_get var rtlmp_max_macros] 0]
+        if { $rtlmp_max_macros != "" } {
+            lappend rtlmp_args -max_num_macro $rtlmp_max_macros
+        }
+        set rtlmp_min_aspect_ratio [lindex [sc_cfg_tool_task_get var rtlmp_min_aspect_ratio] 0]
+        if { $rtlmp_min_aspect_ratio != "" } {
+            lappend rtlmp_args -min_ar $rtlmp_min_aspect_ratio
+        }
+        set rtlmp_fence [sc_cfg_tool_task_get var rtlmp_fence]
+        if { $rtlmp_fence != "" } {
+            lappend rtlmp_args -fence_lx [lindex $rtlmp_fence 0]
+            lappend rtlmp_args -fence_ly [lindex $rtlmp_fence 1]
+            lappend rtlmp_args -fence_ux [lindex $rtlmp_fence 2]
+            lappend rtlmp_args -fence_uy [lindex $rtlmp_fence 3]
+        }
+        set rtlmp_bus_planning [lindex [sc_cfg_tool_task_get var rtlmp_bus_planning] 0]
+        if { $rtlmp_bus_planning == "true" } {
+            lappend rtlmp_args -bus_planning
+        }
+        set rtlmp_target_dead_space [lindex [sc_cfg_tool_task_get var rtlmp_target_dead_space] 0]
+        if { $rtlmp_target_dead_space != "" } {
+            lappend rtlmp_args -target_dead_space $rtlmp_target_dead_space
+        }
+
+        set rtlmp_area_weight [lindex [sc_cfg_tool_task_get var rtlmp_area_weight] 0]
+        if { $rtlmp_area_weight != "" } {
+            lappend rtlmp_args -area_weight $rtlmp_area_weight
+        }
+        set rtlmp_outline_weight [lindex [sc_cfg_tool_task_get var rtlmp_outline_weight] 0]
+        if { $rtlmp_outline_weight != "" } {
+            lappend rtlmp_args -outline_weight $rtlmp_outline_weight
+        }
+        set rtlmp_wirelength_weight [lindex [sc_cfg_tool_task_get var rtlmp_wirelength_weight] 0]
+        if { $rtlmp_wirelength_weight != "" } {
+            lappend rtlmp_args -wirelength_weight $rtlmp_wirelength_weight
+        }
+        set rtlmp_guidance_weight [lindex [sc_cfg_tool_task_get var rtlmp_guidance_weight] 0]
+        if { $rtlmp_guidance_weight != "" } {
+            lappend rtlmp_args -guidance_weight $rtlmp_guidance_weight
+        }
+        set rtlmp_fence_weight [lindex [sc_cfg_tool_task_get var rtlmp_fence_weight] 0]
+        if { $rtlmp_fence_weight != "" } {
+            lappend rtlmp_args -fence_weight $rtlmp_fence_weight
+        }
+        set rtlmp_notch_weight [lindex [sc_cfg_tool_task_get var rtlmp_notch_weight] 0]
+        if { $rtlmp_notch_weight != "" } {
+            lappend rtlmp_args -notch_weight $rtlmp_notch_weight
+        }
+        set rtlmp_blockage_weight [lindex [sc_cfg_tool_task_get var rtlmp_blockage_weight] 0]
+        if { $rtlmp_blockage_weight != "" } {
+            lappend rtlmp_args -blockage_weight $rtlmp_blockage_weight
+        }
+
+        rtl_macro_placer \
+            -report_directory reports/rtlmp \
+            -halo_width $halo_x \
+            -halo_height $halo_y \
+            -target_util [sc_global_placement_density] \
+            {*}$rtlmp_args
+    } else {
+        ###############################
+        # TDMS Global Placement
+        ###############################
+
+        sc_global_placement -disable_routability_driven
+
+        ###############################
+        # Macro placement
+        ###############################
+
+        macro_placement \
+            -halo [sc_cfg_tool_task_get var macro_place_halo] \
+            -channel [sc_cfg_tool_task_get var macro_place_channel]
+    }
+}
+
+sc_print_macro_information
+
+###############################
+# Task Postamble
+###############################
+
+source -echo "$sc_refdir/apr/postamble.tcl"

siliconcompiler/tools/openroad/scripts/apr/sc_metrics.tcl

@@ -0,0 +1,22 @@
+###############################
+# Reading SC Schema
+###############################
+
+source ./sc_manifest.tcl > /dev/null
+
+###############################
+# Task Preamble
+###############################
+
+set sc_refdir [sc_cfg_tool_task_get refdir]
+source -echo "$sc_refdir/apr/preamble.tcl"
+
+###############################
+# Report Metrics
+###############################
+
+###############################
+# Task Postamble
+###############################
+
+source -echo "$sc_refdir/apr/postamble.tcl"

siliconcompiler/tools/openroad/scripts/apr/sc_pin_placement.tcl

@@ -0,0 +1,41 @@
+###############################
+# Reading SC Schema
+###############################
+
+source ./sc_manifest.tcl > /dev/null
+
+###############################
+# Task Preamble
+###############################
+
+set sc_refdir [sc_cfg_tool_task_get refdir]
+source -echo "$sc_refdir/apr/preamble.tcl"
+
+if { [sc_design_has_placeable_ios] } {
+    ###############################
+    # Global Placement (without considering IO placements)
+    ###############################
+
+    if { [lindex [sc_cfg_tool_task_get {var} gpl_enable_skip_io] 0] == "true" } {
+        utl::info FLW 1 "Performing global placement without considering IO"
+        sc_global_placement -skip_io
+    }
+
+    ###############################
+    # Refine Automatic Pin Placement
+    ###############################
+
+    if { ![sc_has_unplaced_instances] } {
+        sc_pin_placement
+    } else {
+        utl::info FLW 1 "Skipping pin placements refinement due to unplaced instances"
+    }
+
+    estimate_parasitics -placement
+}
+
+###############################
+# Task Postamble
+###############################
+
+source -echo "$sc_refdir/apr/postamble.tcl"

siliconcompiler/tools/openroad/scripts/apr/sc_power_grid.tcl

@@ -0,0 +1,60 @@
+###############################
+# Reading SC Schema
+###############################
+
+source ./sc_manifest.tcl > /dev/null
+
+###############################
+# Task Preamble
+###############################
+
+set sc_refdir [sc_cfg_tool_task_get refdir]
+source -echo "$sc_refdir/apr/preamble.tcl"
+
+###############################
+# Error checking
+###############################
+
+if { [sc_design_has_unplaced_macros] } {
+    utl::error FLW 1 "Design contains unplaced macros."
+}
+
+###############################
+# Power Network
+###############################
+
+set pdn_files []
+foreach pdnconfig [sc_cfg_tool_task_get {file} pdn_config] {
+    if { [lsearch -exact $pdn_files $pdnconfig] != -1 } {
+        continue
+    }
+    puts "Sourcing PDNGEN configuration: ${pdnconfig}"
+    source $pdnconfig
+
+    lappend pdn_files $pdnconfig
+}
+pdngen -failed_via_report "reports/${sc_design}_pdngen_failed_vias.rpt"
+
+###############################
+# Check Power Network
+###############################
+
+foreach net [sc_supply_nets] {
+    if { ![[[ord::get_db_block] findNet $net] isSpecial] } {
+        utl::warn FLW 1 "$net_name is marked as a supply net, but is not marked as a special net"
+    }
+}
+
+foreach net [sc_psm_check_nets] {
+    puts "Check supply net: $net"
+    check_power_grid \
+        -floorplanning \
+        -error_file "reports/power_grid_${net}.rpt" \
+        -net $net
+}
+
+###############################
+# Task Postamble
+###############################
+
+source -echo "$sc_refdir/apr/postamble.tcl"

siliconcompiler/tools/openroad/scripts/apr/sc_repair_design.tcl

@@ -0,0 +1,68 @@
+###############################
+# Reading SC Schema
+###############################
+
+source ./sc_manifest.tcl > /dev/null
+
+###############################
+# Task Preamble
+###############################
+
+set sc_refdir [sc_cfg_tool_task_get refdir]
+source -echo "$sc_refdir/apr/preamble.tcl"
+
+###############################
+# Buffer ports
+###############################
+
+if { [lindex [sc_cfg_tool_task_get {var} rsz_buffer_inputs] 0] == "true" } {
+    buffer_ports -inputs
+}
+if { [lindex [sc_cfg_tool_task_get {var} rsz_buffer_outputs] 0] == "true" } {
+    buffer_ports -outputs
+}
+
+estimate_parasitics -placement
+
+###############################
+# Repair DRVs
+###############################
+
+set repair_design_args []
+
+set rsz_cap_margin [lindex [sc_cfg_tool_task_get {var} rsz_cap_margin] 0]
+if { $rsz_cap_margin != "false" } {
+    lappend repair_design_args "-cap_margin" $rsz_cap_margin
+}
+set rsz_slew_margin [lindex [sc_cfg_tool_task_get {var} rsz_slew_margin] 0]
+if { $rsz_slew_margin != "false" } {
+    lappend repair_design_args "-slew_margin" $rsz_slew_margin
+}
+
+repair_design \
+    -verbose \
+    {*}$repair_design_args
+
+###############################
+# Tie-off cell insertion
+###############################
+
+set tie_separation [lindex [sc_cfg_tool_task_get {var} ifp_tie_separation] 0]
+foreach tie_type "high low" {
+    if { [sc_has_tie_cell $tie_type] } {
+        repair_tie_fanout \
+            -separation $tie_separation \
+            [sc_get_tie_cell $tie_type]
+    }
+}
+
+global_connect
+
+# estimate for metrics
+estimate_parasitics -placement
+
+###############################
+# Task Postamble
+###############################
+
+source -echo "$sc_refdir/apr/postamble.tcl"