siliconcompiler 0.28.8__py3-none-any.whl → 0.29.0__py3-none-any.whl

This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
Files changed (122) hide show
  1. siliconcompiler/_metadata.py +1 -1
  2. siliconcompiler/apps/sc_remote.py +15 -14
  3. siliconcompiler/apps/sc_show.py +5 -5
  4. siliconcompiler/apps/utils/replay.py +136 -0
  5. siliconcompiler/core.py +14 -12
  6. siliconcompiler/flows/_common.py +11 -13
  7. siliconcompiler/flows/asicflow.py +83 -42
  8. siliconcompiler/remote/__init__.py +11 -0
  9. siliconcompiler/remote/client.py +753 -815
  10. siliconcompiler/report/report.py +2 -0
  11. siliconcompiler/report/summary_table.py +1 -1
  12. siliconcompiler/scheduler/__init__.py +51 -9
  13. siliconcompiler/scheduler/send_messages.py +37 -33
  14. siliconcompiler/scheduler/validation/email_credentials.json +7 -0
  15. siliconcompiler/schema/schema_cfg.py +15 -3
  16. siliconcompiler/schema/schema_obj.py +16 -0
  17. siliconcompiler/sphinx_ext/dynamicgen.py +4 -3
  18. siliconcompiler/targets/fpgaflow_demo.py +6 -7
  19. siliconcompiler/targets/gf180_demo.py +3 -3
  20. siliconcompiler/templates/replay/requirements.txt +6 -0
  21. siliconcompiler/templates/replay/run.py.j2 +22 -0
  22. siliconcompiler/templates/replay/setup.sh +17 -0
  23. siliconcompiler/tools/_common/__init__.py +17 -3
  24. siliconcompiler/tools/_common/asic.py +10 -3
  25. siliconcompiler/tools/builtin/concatenate.py +1 -1
  26. siliconcompiler/tools/openroad/__init__.py +103 -0
  27. siliconcompiler/tools/openroad/{openroad.py → _apr.py} +413 -422
  28. siliconcompiler/tools/openroad/antenna_repair.py +78 -0
  29. siliconcompiler/tools/openroad/clock_tree_synthesis.py +64 -0
  30. siliconcompiler/tools/openroad/detailed_placement.py +59 -0
  31. siliconcompiler/tools/openroad/detailed_route.py +62 -0
  32. siliconcompiler/tools/openroad/endcap_tapcell_insertion.py +52 -0
  33. siliconcompiler/tools/openroad/fillercell_insertion.py +58 -0
  34. siliconcompiler/tools/openroad/{dfm.py → fillmetal_insertion.py} +35 -19
  35. siliconcompiler/tools/openroad/global_placement.py +58 -0
  36. siliconcompiler/tools/openroad/global_route.py +63 -0
  37. siliconcompiler/tools/openroad/init_floorplan.py +103 -0
  38. siliconcompiler/tools/openroad/macro_placement.py +65 -0
  39. siliconcompiler/tools/openroad/metrics.py +23 -8
  40. siliconcompiler/tools/openroad/pin_placement.py +56 -0
  41. siliconcompiler/tools/openroad/power_grid.py +65 -0
  42. siliconcompiler/tools/openroad/rcx_bench.py +7 -4
  43. siliconcompiler/tools/openroad/rcx_extract.py +2 -1
  44. siliconcompiler/tools/openroad/rdlroute.py +4 -4
  45. siliconcompiler/tools/openroad/repair_design.py +59 -0
  46. siliconcompiler/tools/openroad/repair_timing.py +63 -0
  47. siliconcompiler/tools/openroad/screenshot.py +9 -20
  48. siliconcompiler/tools/openroad/scripts/apr/postamble.tcl +44 -0
  49. siliconcompiler/tools/openroad/scripts/apr/preamble.tcl +95 -0
  50. siliconcompiler/tools/openroad/scripts/apr/sc_antenna_repair.tcl +51 -0
  51. siliconcompiler/tools/openroad/scripts/apr/sc_clock_tree_synthesis.tcl +62 -0
  52. siliconcompiler/tools/openroad/scripts/apr/sc_detailed_placement.tcl +41 -0
  53. siliconcompiler/tools/openroad/scripts/apr/sc_detailed_route.tcl +71 -0
  54. siliconcompiler/tools/openroad/scripts/apr/sc_endcap_tapcell_insertion.tcl +55 -0
  55. siliconcompiler/tools/openroad/scripts/apr/sc_fillercell_insertion.tcl +27 -0
  56. siliconcompiler/tools/openroad/scripts/apr/sc_fillmetal_insertion.tcl +36 -0
  57. siliconcompiler/tools/openroad/scripts/apr/sc_global_placement.tcl +26 -0
  58. siliconcompiler/tools/openroad/scripts/apr/sc_global_route.tcl +61 -0
  59. siliconcompiler/tools/openroad/scripts/apr/sc_init_floorplan.tcl +333 -0
  60. siliconcompiler/tools/openroad/scripts/apr/sc_macro_placement.tcl +123 -0
  61. siliconcompiler/tools/openroad/scripts/apr/sc_metrics.tcl +22 -0
  62. siliconcompiler/tools/openroad/scripts/apr/sc_pin_placement.tcl +41 -0
  63. siliconcompiler/tools/openroad/scripts/apr/sc_power_grid.tcl +60 -0
  64. siliconcompiler/tools/openroad/scripts/apr/sc_repair_design.tcl +68 -0
  65. siliconcompiler/tools/openroad/scripts/apr/sc_repair_timing.tcl +83 -0
  66. siliconcompiler/tools/openroad/scripts/apr/sc_write_data.tcl +125 -0
  67. siliconcompiler/tools/openroad/scripts/common/debugging.tcl +28 -0
  68. siliconcompiler/tools/openroad/scripts/common/procs.tcl +675 -0
  69. siliconcompiler/tools/openroad/scripts/common/read_input_files.tcl +59 -0
  70. siliconcompiler/tools/openroad/scripts/common/read_liberty.tcl +20 -0
  71. siliconcompiler/tools/openroad/scripts/common/read_timing_constraints.tcl +16 -0
  72. siliconcompiler/tools/openroad/scripts/common/reports.tcl +180 -0
  73. siliconcompiler/tools/openroad/scripts/common/screenshot.tcl +18 -0
  74. siliconcompiler/tools/openroad/scripts/common/write_images.tcl +395 -0
  75. siliconcompiler/tools/openroad/scripts/{sc_rcx_bench.tcl → rcx/sc_rcx_bench.tcl} +5 -5
  76. siliconcompiler/tools/openroad/scripts/{sc_rcx_extract.tcl → rcx/sc_rcx_extract.tcl} +0 -0
  77. siliconcompiler/tools/openroad/scripts/sc_rcx.tcl +5 -16
  78. siliconcompiler/tools/openroad/scripts/sc_rdlroute.tcl +51 -51
  79. siliconcompiler/tools/openroad/scripts/sc_show.tcl +105 -0
  80. siliconcompiler/tools/openroad/show.py +28 -23
  81. siliconcompiler/tools/openroad/{export.py → write_data.py} +31 -26
  82. siliconcompiler/tools/opensta/__init__.py +1 -1
  83. siliconcompiler/tools/vivado/bitstream.py +8 -2
  84. siliconcompiler/tools/vivado/place.py +6 -2
  85. siliconcompiler/tools/vivado/route.py +6 -2
  86. siliconcompiler/tools/vivado/scripts/sc_bitstream.tcl +1 -1
  87. siliconcompiler/tools/vivado/scripts/sc_place.tcl +1 -1
  88. siliconcompiler/tools/vivado/scripts/sc_route.tcl +1 -1
  89. siliconcompiler/tools/vivado/scripts/sc_run.tcl +4 -2
  90. siliconcompiler/tools/vivado/syn_fpga.py +5 -1
  91. siliconcompiler/tools/vivado/vivado.py +26 -10
  92. siliconcompiler/tools/vpr/vpr.py +5 -0
  93. siliconcompiler/tools/yosys/syn_asic.py +7 -0
  94. siliconcompiler/tools/yosys/syn_asic.tcl +27 -6
  95. siliconcompiler/tools/yosys/syn_fpga.tcl +26 -18
  96. siliconcompiler/toolscripts/_tools.json +5 -5
  97. {siliconcompiler-0.28.8.dist-info → siliconcompiler-0.29.0.dist-info}/METADATA +50 -48
  98. {siliconcompiler-0.28.8.dist-info → siliconcompiler-0.29.0.dist-info}/RECORD +103 -76
  99. {siliconcompiler-0.28.8.dist-info → siliconcompiler-0.29.0.dist-info}/WHEEL +1 -1
  100. siliconcompiler/tools/openroad/cts.py +0 -45
  101. siliconcompiler/tools/openroad/floorplan.py +0 -75
  102. siliconcompiler/tools/openroad/physyn.py +0 -27
  103. siliconcompiler/tools/openroad/place.py +0 -41
  104. siliconcompiler/tools/openroad/route.py +0 -45
  105. siliconcompiler/tools/openroad/scripts/__init__.py +0 -0
  106. siliconcompiler/tools/openroad/scripts/sc_apr.tcl +0 -514
  107. siliconcompiler/tools/openroad/scripts/sc_cts.tcl +0 -68
  108. siliconcompiler/tools/openroad/scripts/sc_dfm.tcl +0 -22
  109. siliconcompiler/tools/openroad/scripts/sc_export.tcl +0 -100
  110. siliconcompiler/tools/openroad/scripts/sc_floorplan.tcl +0 -456
  111. siliconcompiler/tools/openroad/scripts/sc_metrics.tcl +0 -1
  112. siliconcompiler/tools/openroad/scripts/sc_physyn.tcl +0 -6
  113. siliconcompiler/tools/openroad/scripts/sc_place.tcl +0 -84
  114. siliconcompiler/tools/openroad/scripts/sc_procs.tcl +0 -494
  115. siliconcompiler/tools/openroad/scripts/sc_report.tcl +0 -189
  116. siliconcompiler/tools/openroad/scripts/sc_route.tcl +0 -143
  117. siliconcompiler/tools/openroad/scripts/sc_screenshot.tcl +0 -18
  118. siliconcompiler/tools/openroad/scripts/sc_write_images.tcl +0 -393
  119. /siliconcompiler/tools/openroad/scripts/{sc_write.tcl → common/write_data.tcl} +0 -0
  120. {siliconcompiler-0.28.8.dist-info → siliconcompiler-0.29.0.dist-info}/LICENSE +0 -0
  121. {siliconcompiler-0.28.8.dist-info → siliconcompiler-0.29.0.dist-info}/entry_points.txt +0 -0
  122. {siliconcompiler-0.28.8.dist-info → siliconcompiler-0.29.0.dist-info}/top_level.txt +0 -0
@@ -1,456 +0,0 @@
1
- ########################################################
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- # FLOORPLANNING
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- ########################################################
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-
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- ###########################
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- # Setup Global Connections
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- ###########################
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-
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- if { [sc_cfg_tool_task_exists {file} global_connect] } {
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- foreach global_connect [sc_cfg_tool_task_get {file} global_connect] {
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- puts "Sourcing global connect configuration: ${global_connect}"
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- source $global_connect
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- }
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- }
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-
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- ###########################
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- # Initialize floorplan
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- ###########################
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-
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- if { [sc_cfg_exists input asic floorplan] } {
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- set def [lindex [sc_cfg_get input asic floorplan] 0]
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- puts "Reading floorplan DEF: ${def}"
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- read_def -floorplan_initialize $def
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- } else {
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- #NOTE: assuming a two tuple value as lower left, upper right
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- set sc_diearea [sc_cfg_get constraint outline]
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- set sc_corearea [sc_cfg_get constraint corearea]
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- if {
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- $sc_diearea != "" &&
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- $sc_corearea != ""
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- } {
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- # Use die and core sizes
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- set sc_diesize "[lindex $sc_diearea 0] [lindex $sc_diearea 1]"
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- set sc_coresize "[lindex $sc_corearea 0] [lindex $sc_corearea 1]"
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-
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- initialize_floorplan -die_area $sc_diesize \
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- -core_area $sc_coresize \
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- -site $sc_site
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- } else {
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- # Use density
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- initialize_floorplan -aspect_ratio [sc_cfg_get constraint aspectratio] \
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- -utilization [sc_cfg_get constraint density] \
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- -core_space [sc_cfg_get constraint coremargin] \
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- -site $sc_site
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- }
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- }
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-
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- puts "Floorplan information:"
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- puts "Die area: [ord::get_die_area]"
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- puts "Core area: [ord::get_core_area]"
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-
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- ###########################
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- # Track Creation
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- ###########################
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-
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- # source tracks from file if found, else else use schema entries
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- if { [sc_cfg_exists library $sc_mainlib option file openroad_tracks] } {
58
- set tracks_file [lindex [sc_cfg_get library $sc_mainlib option file openroad_tracks] 0]
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- puts "Sourcing tracks configuration: ${tracks_file}"
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- source $tracks_file
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- } else {
62
- make_tracks
63
- }
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-
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- set do_automatic_pins 1
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- if {
67
- [sc_cfg_tool_task_exists file padring] &&
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- [llength [sc_cfg_tool_task_get file padring]] > 0
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- } {
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- set do_automatic_pins 0
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-
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- ###########################
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- # Generate pad ring
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- ###########################
75
- foreach padring_file [sc_cfg_tool_task_get {file} padring] {
76
- puts "Sourcing padring configuration: ${padring_file}"
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- source $padring_file
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- }
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-
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- if { [sc_design_has_unplaced_pads] } {
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- foreach inst [[ord::get_db_block] getInsts] {
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- if { [$inst isPad] && ![$inst isFixed] } {
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- utl::warn FLW 1 "[$inst getName] has not been placed"
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- }
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- }
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- utl::error FLW 1 "Design contains unplaced IOs"
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- }
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- }
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-
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- ###########################
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- # Pin placement
92
- ###########################
93
- if { [sc_cfg_exists constraint pin] } {
94
- source "[sc_cfg_tool_task_get file sc_pin_constraint]"
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-
96
- proc sc_pin_print { arg } { utl::warn FLW 1 $arg }
97
- proc sc_pin_layer_select { pin } {
98
- global sc_hpinmetal
99
- global sc_vpinmetal
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-
101
- set layer [sc_cfg_get constraint pin $pin layer]
102
- if { [llength $layer] != 0 } {
103
- return [sc_get_layer_name [lindex $layer 0]]
104
- }
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- set side [sc_cfg_get constraint pin $pin side]
106
- if { [llength $side] != 0 } {
107
- switch -regexp $side {
108
- "1|3" {
109
- return [lindex $sc_hpinmetal 0]
110
- }
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- "2|4" {
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- return [lindex $sc_vpinmetal 0]
113
- }
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- default {
115
- utl::error FLW 1 "Side number ($side) on $pin is not supported."
116
- }
117
- }
118
- }
119
-
120
- utl::error FLW 1 "$pin needs to either specify side or layer parameter."
121
- }
122
- sc_collect_pin_constraints \
123
- pin_placement \
124
- pin_order \
125
- sc_pin_layer_select \
126
- sc_pin_print
127
-
128
- foreach pin $pin_placement {
129
- set layer [sc_pin_layer_select $pin]
130
- set place [sc_cfg_get constraint pin $pin placement]
131
-
132
- set x_loc [lindex $place 0]
133
- set y_loc [lindex $place 1]
134
-
135
- place_pin -pin_name $pin \
136
- -layer $layer \
137
- -location "$x_loc $y_loc" \
138
- -force_to_die_boundary
139
- }
140
-
141
- dict for {side layer_pins} $pin_order {
142
- set edge_length 0
143
- switch -regexp $side {
144
- "1|3" {
145
- set edge_length [expr { [lindex [ord::get_die_area] 3] - [lindex [ord::get_die_area] 1] }]
146
- }
147
- "2|4" {
148
- set edge_length [expr { [lindex [ord::get_die_area] 2] - [lindex [ord::get_die_area] 0] }]
149
- }
150
- default {
151
- utl::error FLW 1 "Side number ($side) is not supported."
152
- }
153
- }
154
-
155
- dict for {layer ordered_pins} $layer_pins {
156
- set spacing [expr { $edge_length / ([llength $ordered_pins] + 1) }]
157
-
158
- for { set i 0 } { $i < [llength $ordered_pins] } { incr i } {
159
- set name [lindex $ordered_pins $i]
160
- switch -regexp $side {
161
- "1" {
162
- set x_loc [lindex [ord::get_die_area] 1]
163
- set y_loc [expr { ($i + 1) * $spacing }]
164
- }
165
- "2" {
166
- set x_loc [expr { ($i + 1) * $spacing }]
167
- set y_loc [lindex [ord::get_die_area] 3]
168
- }
169
- "3" {
170
- set x_loc [lindex [ord::get_die_area] 2]
171
- set y_loc [expr { ($i + 1) * $spacing }]
172
- }
173
- "4" {
174
- set x_loc [expr { ($i + 1) * $spacing }]
175
- set y_loc [lindex [ord::get_die_area] 1]
176
- }
177
- }
178
-
179
- place_pin -pin_name $name \
180
- -layer $layer \
181
- -location "$x_loc $y_loc" \
182
- -force_to_die_boundary
183
- }
184
- }
185
- }
186
- }
187
-
188
- ###########################
189
- # Macro placement
190
- ###########################
191
-
192
- # If manual macro placement is provided use that first
193
- if { [sc_cfg_exists constraint component] } {
194
- set sc_snap_strategy [sc_cfg_tool_task_get {var} ifp_snap_strategy]
195
-
196
- if { $sc_snap_strategy == "manufacturing_grid" } {
197
- if { [[ord::get_db_tech] hasManufacturingGrid] } {
198
- set x_grid [[ord::get_db_tech] getManufacturingGrid]
199
- set y_grid $x_grid
200
- } else {
201
- utl::warn FLW 1 "Manufacturing grid is not defined, defaulting to 'none' snapping strategy"
202
- set x_grid 1
203
- set y_grid 1
204
- }
205
- } elseif { $sc_snap_strategy == "site" } {
206
- set x_grid 0
207
- set y_grid 0
208
- foreach row [[ord::get_db_block] getRows] {
209
- set site [$row getSite]
210
- if { [$site getClass] == "PAD" } {
211
- continue
212
- }
213
-
214
- set site_height [$site getHeight]
215
- set site_width [$site getWidth]
216
- if { $y_grid == 0 } {
217
- set y_grid $site_height
218
- } elseif { $y_grid > $site_height } {
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- set y_grid $site_height
220
- }
221
- if { $x_grid == 0 } {
222
- set x_grid $site_width
223
- } elseif { $x_grid > $site_width } {
224
- set x_grid $site_width
225
- }
226
- }
227
- } else {
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- set x_grid 1
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- set y_grid 1
230
- }
231
-
232
- if { $x_grid == 0 || $y_grid == 0 } {
233
- utl::warn FLW 1 "Unable to determine snapping grid."
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- set x_grid 1
235
- set y_grid 1
236
- }
237
-
238
- set x_grid [ord::dbu_to_microns $x_grid]
239
- set y_grid [ord::dbu_to_microns $y_grid]
240
-
241
- dict for {name params} [sc_cfg_get constraint component] {
242
- set location [dict get $params placement]
243
- set rotation [sc_convert_rotation [dict get $params rotation]]
244
-
245
- if { [dict exists $params partname] } {
246
- set cell [dict get $params partname]
247
- } else {
248
- set cell ""
249
- }
250
- if { [llength [dict get $params halo]] != 0 } {
251
- utl::warn FLW 1 "Halo is not supported in OpenROAD"
252
- }
253
-
254
- set transform [odb::dbTransform $rotation]
255
-
256
- set inst [[ord::get_db_block] findInst $name]
257
- if { $inst == "NULL" } {
258
- utl::warn FLW 1 "Could not find instance: $name"
259
-
260
- if { $cell == "" } {
261
- utl::error FLW 1 "Unable to create instance for $name as the cell has not been specified"
262
- } else {
263
- set master [[ord::get_db] findMaster $cell]
264
- if { $master == "NULL" } {
265
- utl::error FLW 1 "Unable to create $name, $cell is not a valid type"
266
- }
267
- set inst [odb::dbInst_create [ord::get_db_block] $master $name]
268
- }
269
- }
270
- set master [$inst getMaster]
271
-
272
- set x_loc [expr { round([lindex $location 0] / $x_grid) * $x_grid }]
273
- set y_loc [expr { round([lindex $location 1] / $y_grid) * $y_grid }]
274
-
275
- $inst setOrient [$rotation getOrient]
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- $inst setLocation [ord::microns_to_dbu $x_loc] [ord::microns_to_dbu $y_loc]
277
- $inst setPlacementStatus FIRM
278
- }
279
- }
280
-
281
- if { $do_automatic_pins } {
282
- ###########################
283
- # Automatic Random Pin Placement
284
- ###########################
285
-
286
- sc_pin_placement -random
287
- }
288
-
289
- # Need to check if we have any macros before performing macro placement,
290
- # since we get an error otherwise.
291
- if { [sc_design_has_unplaced_macros] } {
292
- if { $openroad_rtlmp_enable == "true" } {
293
- lassign $openroad_mpl_macro_place_halo halo_x halo_y
294
-
295
- set rtlmp_args []
296
- if { $openroad_rtlmp_max_levels != "" } {
297
- lappend rtlmp_args -max_num_level $openroad_rtlmp_max_levels
298
- }
299
- if { $openroad_rtlmp_min_instances != "" } {
300
- lappend rtlmp_args -min_num_inst $openroad_rtlmp_min_instances
301
- }
302
- if { $openroad_rtlmp_max_instances != "" } {
303
- lappend rtlmp_args -max_num_inst $openroad_rtlmp_max_instances
304
- }
305
- if { $openroad_rtlmp_min_macros != "" } {
306
- lappend rtlmp_args -min_num_macro $openroad_rtlmp_min_macros
307
- }
308
- if { $openroad_rtlmp_max_macros != "" } {
309
- lappend rtlmp_args -max_num_macro $openroad_rtlmp_max_macros
310
- }
311
- if { $openroad_rtlmp_min_aspect_ratio != "" } {
312
- lappend rtlmp_args -min_ar $openroad_rtlmp_min_aspect_ratio
313
- }
314
- if { $openroad_rtlmp_fence != "" } {
315
- lappend rtlmp_args -fence_lx [lindex $openroad_rtlmp_fence 0]
316
- lappend rtlmp_args -fence_ly [lindex $openroad_rtlmp_fence 1]
317
- lappend rtlmp_args -fence_ux [lindex $openroad_rtlmp_fence 2]
318
- lappend rtlmp_args -fence_uy [lindex $openroad_rtlmp_fence 3]
319
- }
320
- if { $openroad_rtlmp_bus_planning == "true" } {
321
- lappend rtlmp_args -bus_planning
322
- }
323
- if { $openroad_rtlmp_target_dead_space != "" } {
324
- lappend rtlmp_args -target_dead_space $openroad_rtlmp_target_dead_space
325
- }
326
-
327
- if { $openroad_rtlmp_area_weight != "" } {
328
- lappend rtlmp_args -area_weight $openroad_rtlmp_area_weight
329
- }
330
- if { $openroad_rtlmp_outline_weight != "" } {
331
- lappend rtlmp_args -outline_weight $openroad_rtlmp_outline_weight
332
- }
333
- if { $openroad_rtlmp_wirelength_weight != "" } {
334
- lappend rtlmp_args -wirelength_weight $openroad_rtlmp_wirelength_weight
335
- }
336
- if { $openroad_rtlmp_guidance_weight != "" } {
337
- lappend rtlmp_args -guidance_weight $openroad_rtlmp_guidance_weight
338
- }
339
- if { $openroad_rtlmp_fence_weight != "" } {
340
- lappend rtlmp_args -fence_weight $openroad_rtlmp_fence_weight
341
- }
342
- if { $openroad_rtlmp_notch_weight != "" } {
343
- lappend rtlmp_args -notch_weight $openroad_rtlmp_notch_weight
344
- }
345
- if { $openroad_rtlmp_blockage_weight != "" } {
346
- lappend rtlmp_args -blockage_weight $openroad_rtlmp_blockage_weight
347
- }
348
-
349
- rtl_macro_placer -report_directory reports/rtlmp \
350
- -halo_width $halo_x \
351
- -halo_height $halo_y \
352
- -target_util [sc_global_placement_density] \
353
- {*}$rtlmp_args
354
- } else {
355
- ###########################
356
- # TDMS Global Placement
357
- ###########################
358
-
359
- sc_global_placement -disable_routability_driven
360
-
361
- ###########################
362
- # Macro placement
363
- ###########################
364
-
365
- macro_placement -halo $openroad_mpl_macro_place_halo \
366
- -channel $openroad_mpl_macro_place_channel
367
-
368
- # Note: some platforms set a "macro blockage halo" at this point, but the
369
- # technologies we support do not, so we don't include that step for now.
370
- }
371
- }
372
-
373
- sc_print_macro_information
374
-
375
- if { [sc_design_has_unplaced_macros] } {
376
- utl::error FLW 1 "Design contains unplaced macros."
377
- }
378
-
379
- ###########################
380
- # Insert tie cells
381
- ###########################
382
-
383
- foreach tie_type "high low" {
384
- if { [has_tie_cell $tie_type] } {
385
- insert_tiecells [get_tie_cell $tie_type]
386
- }
387
- }
388
- global_connect
389
-
390
- ###########################
391
- # Tap Cells
392
- ###########################
393
-
394
- if {
395
- [sc_cfg_tool_task_exists {file} ifp_tapcell] &&
396
- [llength [sc_cfg_tool_task_get {file} ifp_tapcell]] > 0
397
- } {
398
- foreach tapcell_file [sc_cfg_tool_task_get {file} ifp_tapcell] {
399
- puts "Sourcing tapcell file: ${tapcell_file}"
400
- source $tapcell_file
401
- }
402
- global_connect
403
- } else {
404
- utl::warn FLW 1 "Tapcell configuration not provided"
405
- cut_rows
406
- }
407
-
408
- ###########################
409
- # Power Network
410
- ###########################
411
-
412
- if {
413
- $openroad_pdn_enable == "true" &&
414
- [sc_cfg_tool_task_exists {file} pdn_config] &&
415
- [llength [sc_cfg_tool_task_get {file} pdn_config]] > 0
416
- } {
417
- set pdn_files []
418
- foreach pdnconfig [sc_cfg_tool_task_get {file} pdn_config] {
419
- if { [lsearch -exact $pdn_files $pdnconfig] != -1 } {
420
- continue
421
- }
422
- puts "Sourcing PDNGEN configuration: ${pdnconfig}"
423
- source $pdnconfig
424
-
425
- lappend pdn_files $pdnconfig
426
- }
427
- pdngen -failed_via_report "reports/${sc_design}_pdngen_failed_vias.rpt"
428
- } else {
429
- utl::warn FLW 1 "No power grid inserted"
430
- }
431
-
432
- ###########################
433
- # Check Power Network
434
- ###########################
435
-
436
- foreach net [sc_supply_nets] {
437
- if { ![[[ord::get_db_block] findNet $net] isSpecial] } {
438
- utl::warn FLW 1 "$net_name is marked as a supply net, but is not marked as a special net"
439
- }
440
- }
441
-
442
- foreach net [sc_psm_check_nets] {
443
- puts "Check supply net: $net"
444
- check_power_grid \
445
- -floorplanning \
446
- -error_file "reports/power_grid_${net}.rpt" \
447
- -net $net
448
- }
449
-
450
- ###########################
451
- # Remove buffers inserted by synthesis
452
- ###########################
453
-
454
- if { [lindex [sc_cfg_tool_task_get var remove_synth_buffers] 0] == "true" } {
455
- remove_buffers
456
- }
@@ -1,6 +0,0 @@
1
- # while (not good enough):
2
- # global placement
3
- # estimate parasitics
4
- # logic remapping, buffering
5
-
6
- puts "NOP"
@@ -1,84 +0,0 @@
1
- #######################
2
- # Global Placement and Refinement of Pin Placement
3
- #######################
4
-
5
- if { [sc_design_has_placeable_ios] } {
6
- #######################
7
- # Global Placement (without considering IO placements)
8
- #######################
9
-
10
- if { $openroad_gpl_enable_skip_io } {
11
- utl::info FLW 1 "Performing global placement without considering IO"
12
- sc_global_placement -skip_io
13
- }
14
-
15
- ###########################
16
- # Refine Automatic Pin Placement
17
- ###########################
18
-
19
- if { ![sc_has_unplaced_instances] } {
20
- sc_pin_placement
21
- } else {
22
- utl::info FLW 1 "Skipping pin placements refinement due to unplaced instances"
23
- }
24
- }
25
-
26
- #######################
27
- # Global Placement
28
- #######################
29
-
30
- sc_global_placement
31
-
32
- #######################
33
- # Repair Design
34
- #######################
35
-
36
- estimate_parasitics -placement
37
-
38
- if { $openroad_rsz_buffer_inputs == "true" } {
39
- buffer_ports -inputs
40
- }
41
- if { $openroad_rsz_buffer_outputs == "true" } {
42
- buffer_ports -outputs
43
- }
44
-
45
- set repair_design_args []
46
- if { $openroad_rsz_cap_margin != "false" } {
47
- lappend repair_design_args "-cap_margin" $openroad_rsz_cap_margin
48
- }
49
- if { $openroad_rsz_slew_margin != "false" } {
50
- lappend repair_design_args "-slew_margin" $openroad_rsz_slew_margin
51
- }
52
- repair_design -verbose {*}$repair_design_args
53
-
54
- #######################
55
- # TIE FANOUT
56
- #######################
57
-
58
- foreach tie_type "high low" {
59
- if { [has_tie_cell $tie_type] } {
60
- repair_tie_fanout -separation $openroad_ifp_tie_separation [get_tie_cell $tie_type]
61
- }
62
- }
63
-
64
- #######################
65
- # DETAILED PLACEMENT
66
- #######################
67
-
68
- sc_detailed_placement
69
-
70
- if { $openroad_dpo_enable == "true" } {
71
- improve_placement -max_displacement $openroad_dpo_max_displacement
72
-
73
- # Do another detailed placement in case DPO leaves violations behind
74
- sc_detailed_placement
75
- }
76
-
77
- optimize_mirroring
78
-
79
- check_placement -verbose
80
-
81
- global_connect
82
-
83
- # estimate for metrics
84
- estimate_parasitics -placement