siliconcompiler 0.28.8__py3-none-any.whl → 0.29.0__py3-none-any.whl

This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
Files changed (122) hide show
  1. siliconcompiler/_metadata.py +1 -1
  2. siliconcompiler/apps/sc_remote.py +15 -14
  3. siliconcompiler/apps/sc_show.py +5 -5
  4. siliconcompiler/apps/utils/replay.py +136 -0
  5. siliconcompiler/core.py +14 -12
  6. siliconcompiler/flows/_common.py +11 -13
  7. siliconcompiler/flows/asicflow.py +83 -42
  8. siliconcompiler/remote/__init__.py +11 -0
  9. siliconcompiler/remote/client.py +753 -815
  10. siliconcompiler/report/report.py +2 -0
  11. siliconcompiler/report/summary_table.py +1 -1
  12. siliconcompiler/scheduler/__init__.py +51 -9
  13. siliconcompiler/scheduler/send_messages.py +37 -33
  14. siliconcompiler/scheduler/validation/email_credentials.json +7 -0
  15. siliconcompiler/schema/schema_cfg.py +15 -3
  16. siliconcompiler/schema/schema_obj.py +16 -0
  17. siliconcompiler/sphinx_ext/dynamicgen.py +4 -3
  18. siliconcompiler/targets/fpgaflow_demo.py +6 -7
  19. siliconcompiler/targets/gf180_demo.py +3 -3
  20. siliconcompiler/templates/replay/requirements.txt +6 -0
  21. siliconcompiler/templates/replay/run.py.j2 +22 -0
  22. siliconcompiler/templates/replay/setup.sh +17 -0
  23. siliconcompiler/tools/_common/__init__.py +17 -3
  24. siliconcompiler/tools/_common/asic.py +10 -3
  25. siliconcompiler/tools/builtin/concatenate.py +1 -1
  26. siliconcompiler/tools/openroad/__init__.py +103 -0
  27. siliconcompiler/tools/openroad/{openroad.py → _apr.py} +413 -422
  28. siliconcompiler/tools/openroad/antenna_repair.py +78 -0
  29. siliconcompiler/tools/openroad/clock_tree_synthesis.py +64 -0
  30. siliconcompiler/tools/openroad/detailed_placement.py +59 -0
  31. siliconcompiler/tools/openroad/detailed_route.py +62 -0
  32. siliconcompiler/tools/openroad/endcap_tapcell_insertion.py +52 -0
  33. siliconcompiler/tools/openroad/fillercell_insertion.py +58 -0
  34. siliconcompiler/tools/openroad/{dfm.py → fillmetal_insertion.py} +35 -19
  35. siliconcompiler/tools/openroad/global_placement.py +58 -0
  36. siliconcompiler/tools/openroad/global_route.py +63 -0
  37. siliconcompiler/tools/openroad/init_floorplan.py +103 -0
  38. siliconcompiler/tools/openroad/macro_placement.py +65 -0
  39. siliconcompiler/tools/openroad/metrics.py +23 -8
  40. siliconcompiler/tools/openroad/pin_placement.py +56 -0
  41. siliconcompiler/tools/openroad/power_grid.py +65 -0
  42. siliconcompiler/tools/openroad/rcx_bench.py +7 -4
  43. siliconcompiler/tools/openroad/rcx_extract.py +2 -1
  44. siliconcompiler/tools/openroad/rdlroute.py +4 -4
  45. siliconcompiler/tools/openroad/repair_design.py +59 -0
  46. siliconcompiler/tools/openroad/repair_timing.py +63 -0
  47. siliconcompiler/tools/openroad/screenshot.py +9 -20
  48. siliconcompiler/tools/openroad/scripts/apr/postamble.tcl +44 -0
  49. siliconcompiler/tools/openroad/scripts/apr/preamble.tcl +95 -0
  50. siliconcompiler/tools/openroad/scripts/apr/sc_antenna_repair.tcl +51 -0
  51. siliconcompiler/tools/openroad/scripts/apr/sc_clock_tree_synthesis.tcl +62 -0
  52. siliconcompiler/tools/openroad/scripts/apr/sc_detailed_placement.tcl +41 -0
  53. siliconcompiler/tools/openroad/scripts/apr/sc_detailed_route.tcl +71 -0
  54. siliconcompiler/tools/openroad/scripts/apr/sc_endcap_tapcell_insertion.tcl +55 -0
  55. siliconcompiler/tools/openroad/scripts/apr/sc_fillercell_insertion.tcl +27 -0
  56. siliconcompiler/tools/openroad/scripts/apr/sc_fillmetal_insertion.tcl +36 -0
  57. siliconcompiler/tools/openroad/scripts/apr/sc_global_placement.tcl +26 -0
  58. siliconcompiler/tools/openroad/scripts/apr/sc_global_route.tcl +61 -0
  59. siliconcompiler/tools/openroad/scripts/apr/sc_init_floorplan.tcl +333 -0
  60. siliconcompiler/tools/openroad/scripts/apr/sc_macro_placement.tcl +123 -0
  61. siliconcompiler/tools/openroad/scripts/apr/sc_metrics.tcl +22 -0
  62. siliconcompiler/tools/openroad/scripts/apr/sc_pin_placement.tcl +41 -0
  63. siliconcompiler/tools/openroad/scripts/apr/sc_power_grid.tcl +60 -0
  64. siliconcompiler/tools/openroad/scripts/apr/sc_repair_design.tcl +68 -0
  65. siliconcompiler/tools/openroad/scripts/apr/sc_repair_timing.tcl +83 -0
  66. siliconcompiler/tools/openroad/scripts/apr/sc_write_data.tcl +125 -0
  67. siliconcompiler/tools/openroad/scripts/common/debugging.tcl +28 -0
  68. siliconcompiler/tools/openroad/scripts/common/procs.tcl +675 -0
  69. siliconcompiler/tools/openroad/scripts/common/read_input_files.tcl +59 -0
  70. siliconcompiler/tools/openroad/scripts/common/read_liberty.tcl +20 -0
  71. siliconcompiler/tools/openroad/scripts/common/read_timing_constraints.tcl +16 -0
  72. siliconcompiler/tools/openroad/scripts/common/reports.tcl +180 -0
  73. siliconcompiler/tools/openroad/scripts/common/screenshot.tcl +18 -0
  74. siliconcompiler/tools/openroad/scripts/common/write_images.tcl +395 -0
  75. siliconcompiler/tools/openroad/scripts/{sc_rcx_bench.tcl → rcx/sc_rcx_bench.tcl} +5 -5
  76. siliconcompiler/tools/openroad/scripts/{sc_rcx_extract.tcl → rcx/sc_rcx_extract.tcl} +0 -0
  77. siliconcompiler/tools/openroad/scripts/sc_rcx.tcl +5 -16
  78. siliconcompiler/tools/openroad/scripts/sc_rdlroute.tcl +51 -51
  79. siliconcompiler/tools/openroad/scripts/sc_show.tcl +105 -0
  80. siliconcompiler/tools/openroad/show.py +28 -23
  81. siliconcompiler/tools/openroad/{export.py → write_data.py} +31 -26
  82. siliconcompiler/tools/opensta/__init__.py +1 -1
  83. siliconcompiler/tools/vivado/bitstream.py +8 -2
  84. siliconcompiler/tools/vivado/place.py +6 -2
  85. siliconcompiler/tools/vivado/route.py +6 -2
  86. siliconcompiler/tools/vivado/scripts/sc_bitstream.tcl +1 -1
  87. siliconcompiler/tools/vivado/scripts/sc_place.tcl +1 -1
  88. siliconcompiler/tools/vivado/scripts/sc_route.tcl +1 -1
  89. siliconcompiler/tools/vivado/scripts/sc_run.tcl +4 -2
  90. siliconcompiler/tools/vivado/syn_fpga.py +5 -1
  91. siliconcompiler/tools/vivado/vivado.py +26 -10
  92. siliconcompiler/tools/vpr/vpr.py +5 -0
  93. siliconcompiler/tools/yosys/syn_asic.py +7 -0
  94. siliconcompiler/tools/yosys/syn_asic.tcl +27 -6
  95. siliconcompiler/tools/yosys/syn_fpga.tcl +26 -18
  96. siliconcompiler/toolscripts/_tools.json +5 -5
  97. {siliconcompiler-0.28.8.dist-info → siliconcompiler-0.29.0.dist-info}/METADATA +50 -48
  98. {siliconcompiler-0.28.8.dist-info → siliconcompiler-0.29.0.dist-info}/RECORD +103 -76
  99. {siliconcompiler-0.28.8.dist-info → siliconcompiler-0.29.0.dist-info}/WHEEL +1 -1
  100. siliconcompiler/tools/openroad/cts.py +0 -45
  101. siliconcompiler/tools/openroad/floorplan.py +0 -75
  102. siliconcompiler/tools/openroad/physyn.py +0 -27
  103. siliconcompiler/tools/openroad/place.py +0 -41
  104. siliconcompiler/tools/openroad/route.py +0 -45
  105. siliconcompiler/tools/openroad/scripts/__init__.py +0 -0
  106. siliconcompiler/tools/openroad/scripts/sc_apr.tcl +0 -514
  107. siliconcompiler/tools/openroad/scripts/sc_cts.tcl +0 -68
  108. siliconcompiler/tools/openroad/scripts/sc_dfm.tcl +0 -22
  109. siliconcompiler/tools/openroad/scripts/sc_export.tcl +0 -100
  110. siliconcompiler/tools/openroad/scripts/sc_floorplan.tcl +0 -456
  111. siliconcompiler/tools/openroad/scripts/sc_metrics.tcl +0 -1
  112. siliconcompiler/tools/openroad/scripts/sc_physyn.tcl +0 -6
  113. siliconcompiler/tools/openroad/scripts/sc_place.tcl +0 -84
  114. siliconcompiler/tools/openroad/scripts/sc_procs.tcl +0 -494
  115. siliconcompiler/tools/openroad/scripts/sc_report.tcl +0 -189
  116. siliconcompiler/tools/openroad/scripts/sc_route.tcl +0 -143
  117. siliconcompiler/tools/openroad/scripts/sc_screenshot.tcl +0 -18
  118. siliconcompiler/tools/openroad/scripts/sc_write_images.tcl +0 -393
  119. /siliconcompiler/tools/openroad/scripts/{sc_write.tcl → common/write_data.tcl} +0 -0
  120. {siliconcompiler-0.28.8.dist-info → siliconcompiler-0.29.0.dist-info}/LICENSE +0 -0
  121. {siliconcompiler-0.28.8.dist-info → siliconcompiler-0.29.0.dist-info}/entry_points.txt +0 -0
  122. {siliconcompiler-0.28.8.dist-info → siliconcompiler-0.29.0.dist-info}/top_level.txt +0 -0
@@ -1,8 +1,8 @@
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  siliconcompiler/__init__.py,sha256=Ke_Bcryj9N6MoUq_5z_IDW3qMrUzR-3-kJVsvUenYzY,511
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  siliconcompiler/__main__.py,sha256=JwWkcvaNngqgMWprEQ1cFy2Wdq9GMvk46UGTHyh_qvM,170
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  siliconcompiler/_common.py,sha256=c6r0SbI2xTpNOZayFsyCDo0riJGNJSPN-0zW8R7rDBI,1488
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- siliconcompiler/_metadata.py,sha256=CumyMn5odWcWqlPwYTx9IioZ5rx0a68RKL7IvU2SO-A,1264
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- siliconcompiler/core.py,sha256=_T1eEY7lUsrbaEBUaG1WSAzY2JFxyz5tXEKxvoCGZaI,135718
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+ siliconcompiler/_metadata.py,sha256=FWWPgsF9yds5x4TtUHjoCr0fI4uNpjHLReHLkws--Ck,1264
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+ siliconcompiler/core.py,sha256=jmrE-o9IDB8aj7i4oQxuD8ikVMybopaLhzmtZA6-MBY,135846
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  siliconcompiler/flowgraph.py,sha256=WLcbBWFj5DdYRRIxNy_Djm2v4yN9WELQM_ypNPB5QVM,21963
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@@ -14,10 +14,11 @@ siliconcompiler/apps/sc.py,sha256=7wKQ89DZLVXMNbjAgIu9F8Erb_NmrBkV4lJNjBUt8_c,32
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- siliconcompiler/apps/sc_remote.py,sha256=M7wH7lULkeDSEiVkvTY2xmuAK8lJ-3eVM6fC3bqj4s8,7331
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+ siliconcompiler/apps/sc_remote.py,sha256=jsQWEqZnoKrJI9FcA2ILZYJ8F7uvLuwYI4N23dRwVRs,7241
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- siliconcompiler/apps/sc_show.py,sha256=KZGm6nd2On3a15u-OPQnLxNetiHndJKqzWMZG2_Q_1g,4652
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+ siliconcompiler/apps/sc_show.py,sha256=H0_evnBqr02FJVlIaFIva4RrYZ6M2otlWTaTCqFQPlg,4653
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+ siliconcompiler/apps/utils/replay.py,sha256=zCoGx9WJa61Yi9yDp6qNS-YzpTvU6zQLChBoMWWXViA,4611
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@@ -28,8 +29,8 @@ siliconcompiler/data/RobotoMono/LICENSE.txt,sha256=Pd-b5cKP4n2tFDpdx27qJSIq0d1ok
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- siliconcompiler/flows/asicflow.py,sha256=AbnwSersQ4EsBaAvnH3sz44Tj62aroZSGZaTgVSmO6g,6084
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+ siliconcompiler/flows/_common.py,sha256=hcKVUPRK74t6JYU23UnY4qkFnu1-uauLwzsZjqzaYu0,2110
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+ siliconcompiler/flows/asicflow.py,sha256=Hj0goWMxYGSqLmX_07z_uFePJvWcDGhY0afTeJblz7E,8113
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@@ -59,8 +60,8 @@ siliconcompiler/pdks/gf180.py,sha256=yT_tQmfXTMuU-NngX1lakxPXVxZxwdl_FwNP-Rxx2rU
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- siliconcompiler/remote/client.py,sha256=5wPYCPmYqXH3jJ5qWt7Lbkrkkin4b09PoHA96W2Ae8I,31938
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+ siliconcompiler/remote/__init__.py,sha256=MoYnC1lkgbT5hN5Qi-0gTItaTWI2U1E8OuleffdTDSQ,977
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+ siliconcompiler/remote/client.py,sha256=vndAQRgveaCCvnlM8QjQX30ioy4rA5MI2p5ACZOy_sw,32695
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- siliconcompiler/report/report.py,sha256=OPJhuKAnUzP-dm-6CG6Fy45Gm_rbMapey2WKuJiouYI,14924
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+ siliconcompiler/schema/schema_cfg.py,sha256=8PZakYMN4lvCXtC0dtFZiD24-TqeQaMbLnYU1pe2sW8,184229
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+ siliconcompiler/tools/openroad/rcx_bench.py,sha256=6ASma7QGgM4Hk5oXYdDAR1BgElxhYN9L7RoDbQi9LBE,3655
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+ siliconcompiler/tools/openroad/repair_design.py,sha256=R28PPT_OXmPoQFvZC0sxG5u1y9GiUg1ZlUUNZCzu1Vo,1573
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+ siliconcompiler/tools/openroad/scripts/sc_rcx.tcl,sha256=eLbIVoKo9RgxZUcVAmkVMylxDUi7kSeIF1x518c_cZA,1254
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+ siliconcompiler/tools/openroad/scripts/sc_rdlroute.tcl,sha256=DM8ShbsQdOSq0eXCn2paD2sH3XWQlyVG40yiFCmvWmc,4983
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+ siliconcompiler/tools/openroad/scripts/sc_show.tcl,sha256=5Kra4ONIhvXFyk1At5aLeYMISHQ5UpC3KzHLAo1B9yU,2551
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+ siliconcompiler/tools/openroad/scripts/apr/postamble.tcl,sha256=9CLpG_DLvRKMgFRQMR5xWSzGIF9QERIBMkKTxcDYaWA,1130
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+ siliconcompiler/tools/openroad/scripts/apr/sc_antenna_repair.tcl,sha256=Zyd9w7Md6iyCIBmDl-mTYPWkXIx5T0NE9qid339KqLA,1489
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+ siliconcompiler/tools/openroad/scripts/apr/sc_clock_tree_synthesis.tcl,sha256=SjfWC5uKJTveQE0Chw_LaraX6fH9ZX35ZEY5cYdqFpU,1861
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+ siliconcompiler/tools/openroad/scripts/apr/sc_detailed_placement.tcl,sha256=Xcvz-kilJTsrcvNmVZZSzYtCWkC2I1EWYLMVy6DjSxw,924
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+ siliconcompiler/tools/openroad/scripts/apr/sc_detailed_route.tcl,sha256=GlFud8C-89kktBVck4YdSpr_QBDZw62vkEERLyKNzAI,2314
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+ siliconcompiler/tools/openroad/scripts/apr/sc_endcap_tapcell_insertion.tcl,sha256=A_eiApMbYlT0WOvreVtqkS-Ou1rdRu-m0Vtj7yKCGFg,1288
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+ siliconcompiler/tools/openroad/scripts/apr/sc_fillercell_insertion.tcl,sha256=uc7MdGV64PWeH_MAkxx2jrzXVXeoOAVYyYIGgMilPDk,571
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+ siliconcompiler/tools/openroad/scripts/apr/sc_fillmetal_insertion.tcl,sha256=Qk16mhbcVo1g4wBKjYwV4aNr2zAEFXsF8XnehA9xbWY,896
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+ siliconcompiler/tools/openroad/scripts/apr/sc_global_placement.tcl,sha256=wADPZeYFGVsmfNN11U6JCdGjqonsNcWhpuRO9TchE7A,555
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+ siliconcompiler/tools/openroad/scripts/apr/sc_global_route.tcl,sha256=v8149E4GbJrdDAc7i_WFhh2dQomuzSlf149DNqm1DVI,1853
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+ siliconcompiler/tools/openroad/scripts/apr/sc_init_floorplan.tcl,sha256=j3sY5GMGtriQks2yaAEzxrcWhvFIsOrH8cfh5wj_aRQ,10431
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+ siliconcompiler/tools/openroad/scripts/apr/sc_macro_placement.tcl,sha256=RWQRQaFEtrlmaYah4FBwTMldL55FowefsPoq_rgurAw,5087
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+ siliconcompiler/tools/openroad/scripts/apr/sc_metrics.tcl,sha256=Y3EtUBTT1XJIM6CgnXqGAoRg46GNYuMG3dJ6tw-2ShE,500
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+ siliconcompiler/tools/openroad/scripts/apr/sc_pin_placement.tcl,sha256=FpHZ7b88rH-sxlg0w9PpWrmAZIj3Q6yLNiEFFm9wzkw,1114
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+ siliconcompiler/tools/openroad/scripts/apr/sc_power_grid.tcl,sha256=1yV9CZjE7iT99nInjc_cdYe5z2iCmtIJCAqlOkBy7k0,1503
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+ siliconcompiler/tools/openroad/scripts/apr/sc_repair_design.tcl,sha256=MGX50YV22tulRiCaSLGcU_m6fB5h8lbasQQZdBm7M5E,1687
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+ siliconcompiler/tools/openroad/scripts/apr/sc_repair_timing.tcl,sha256=ScaMAP_VtNWl_BTaqfq8sKIJTi9KJXMALhp5EOB8v9c,2357
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+ siliconcompiler/tools/openroad/scripts/apr/sc_write_data.tcl,sha256=q0I3s-hBZtoiFkZHCfeEHBQGNbbgUmiMJ7U7Gsr1pQI,3696
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+ siliconcompiler/tools/openroad/scripts/common/debugging.tcl,sha256=i4oNtC0rQq3JaFf1-oKyr_jZQyu5ZF_--zskvG0hdKg,943
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+ siliconcompiler/tools/openroad/scripts/common/procs.tcl,sha256=TKKpR0Fsoeu408ffKXRYoWMGr3VeqCXLvUG0tW8jz1k,20168
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+ siliconcompiler/tools/openroad/scripts/common/read_input_files.tcl,sha256=sEL4hvDS30E5oHdkyDC2wqdYCKUY3bja4tobzSzWsDw,2020
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+ siliconcompiler/tools/openroad/scripts/common/read_liberty.tcl,sha256=GeXZ8H3a8fg8o-4KyfZj2N4Db_P9XArZl2T4apfMSZI,778
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+ siliconcompiler/tools/openroad/scripts/common/read_timing_constraints.tcl,sha256=fsHSSGXkrqOKXjwH7U8XMLMnEPoZpavBVkl4qzLugOU,515
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+ siliconcompiler/tools/openroad/scripts/common/reports.tcl,sha256=ouBfFyvevH0kG_AToMIa1q2_szdNjUbBNBjyPLrFSgU,6086
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+ siliconcompiler/tools/openroad/scripts/common/screenshot.tcl,sha256=OEE4JpafdOK1cVJw3sie_Fvo03ZkheElhPpvKsgCV0E,447
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+ siliconcompiler/tools/openroad/scripts/common/write_data.tcl,sha256=5N7ZKWU_8NdEYO-n6tuTXCmWCYtClDjHykOidKyFWdk,168
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+ siliconcompiler/tools/openroad/scripts/common/write_images.tcl,sha256=lP9ycPyQ4p-etIuir-fGWr4vq1UqT6LZiy5cRhLZQh8,11031
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+ siliconcompiler/tools/openroad/scripts/rcx/sc_rcx_bench.tcl,sha256=95p_XiRPA1PnofMTMUTesI4JniHnvB8f9_oANGRuC8M,692
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+ siliconcompiler/tools/openroad/scripts/rcx/sc_rcx_extract.tcl,sha256=Aj9J_8aiOR1WqcQvdx99WyUDcN8RafxXwtrexcS5UcU,489
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  siliconcompiler/tools/openroad/templates/pex.tcl,sha256=t-54kEYkIFkC5hIiMWw6IZD9guRwG90zT4Mt9erYUnY,299
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- siliconcompiler/tools/opensta/__init__.py,sha256=CbwN01FDTGohrldYiSkc-Ny_5Wm2yDCRXMrw9CYSKLo,3679
277
+ siliconcompiler/tools/opensta/__init__.py,sha256=M8zNG1mxKv_u-Cflq2ixrImVECPmWVsh4WL6fLk-NR0,3675
251
278
  siliconcompiler/tools/opensta/report_libraries.py,sha256=9DPPQyh7QEEJi1HZR0m086WZPbB22h5aG-yTuHNW_uE,828
252
279
  siliconcompiler/tools/opensta/timing.py,sha256=UbnpTGPtYN4sg0ZurF7V78los6J24RuzVzeIL6Ry6fg,8742
253
280
  siliconcompiler/tools/opensta/scripts/__init__.py,sha256=47DEQpj8HBSa-_TImW-5JCeuQeRkm5NMpJWZG3hSuFU,0
@@ -271,16 +298,16 @@ siliconcompiler/tools/verilator/lint.py,sha256=Lp-PXk6kYtnemN2cMuvCyZxodDIDzLEmK
271
298
  siliconcompiler/tools/verilator/parse.py,sha256=ZAYNgcK7wxRabW1mcgdGfmrcn6cLusPgK1X9vJkWUok,806
272
299
  siliconcompiler/tools/verilator/verilator.py,sha256=tSfUWzXbMPwLPGydeBhLAstZpXLt-3V4LnIfzeKWbYU,6434
273
300
  siliconcompiler/tools/vivado/__init__.py,sha256=f3DdiwAnqqXZZMWp8AAzljLE2pp0Gqarhv9LxzP1ruE,115
274
- siliconcompiler/tools/vivado/bitstream.py,sha256=eZ0Kb6XuwG0lbT9C1RBoUHC27oTaLcK4YLRgByIAU5Y,669
275
- siliconcompiler/tools/vivado/place.py,sha256=L-Z1CAQDQO4zG96rcuqcozCyfPAWvQB-iP2JWk1Kv4U,657
276
- siliconcompiler/tools/vivado/route.py,sha256=1lVPJn9zKP4YT1D-YtltcytrYYmHhCdc2SaY4-RBvto,655
277
- siliconcompiler/tools/vivado/syn_fpga.py,sha256=3C1CQJs5XibX6FbqzMsUq0Ck0TzQG57PTxzbjECFL9o,636
278
- siliconcompiler/tools/vivado/vivado.py,sha256=O59TKyGnokuKKzPcOk7PXfMfEmQFHYOkN6WTcfBPvO4,4960
301
+ siliconcompiler/tools/vivado/bitstream.py,sha256=361b51W7S_0umzGx_Q7VaXFRHpmanrJiNZCXTS5sXkg,972
302
+ siliconcompiler/tools/vivado/place.py,sha256=tvD4-pPeJ-pjptaytY7jTrbllYyYgsDv59NWPvH-eSU,844
303
+ siliconcompiler/tools/vivado/route.py,sha256=OiYWbVxBjlibDla-KTOXVbUtcg8LPsCUtuLhCc7zDfo,842
304
+ siliconcompiler/tools/vivado/syn_fpga.py,sha256=MkcB0d7RjfKhyrCtCUlgDdfbFRu1Z3NQsu8Canw74cI,834
305
+ siliconcompiler/tools/vivado/vivado.py,sha256=3k3iWV6pGivslG377tVGowOW5KvhoamzX2HXnRa4mYg,5522
279
306
  siliconcompiler/tools/vivado/scripts/__init__.py,sha256=47DEQpj8HBSa-_TImW-5JCeuQeRkm5NMpJWZG3hSuFU,0
280
- siliconcompiler/tools/vivado/scripts/sc_bitstream.tcl,sha256=3hF8WODWWDJ5r39XNY6_9Eum9HUxPkpz8yz-sE37DhM,230
281
- siliconcompiler/tools/vivado/scripts/sc_place.tcl,sha256=0smyg_IMSoNCbJnlItnQi3JQdmSGwvBe1SJj5U37uJM,66
282
- siliconcompiler/tools/vivado/scripts/sc_route.tcl,sha256=GcMHmtYChB66igTmhtIP24xWlQjlVEw5y0Heaq1_NXQ,99
283
- siliconcompiler/tools/vivado/scripts/sc_run.tcl,sha256=46nBe16DW16S15VF_fj9T_ktHDFn7BKKXiue6ig3at8,1285
307
+ siliconcompiler/tools/vivado/scripts/sc_bitstream.tcl,sha256=77ftp1FdB7KQ9raHYR2Dd66Fs61dwmqXeUiP4tXK_6o,219
308
+ siliconcompiler/tools/vivado/scripts/sc_place.tcl,sha256=x-3Tu9ZranEJFrqekyuFB1eru6LomCcw3IQiM0Jl_A4,55
309
+ siliconcompiler/tools/vivado/scripts/sc_route.tcl,sha256=yqkSukM7FmDvQVyz5D7xdtSbHyQHQrshHPD-0H_Asww,88
310
+ siliconcompiler/tools/vivado/scripts/sc_run.tcl,sha256=ycNYc71Sfw7KUxU4yZ8T6NCypWoRRW4nWX8yE5PZ-Q4,1359
284
311
  siliconcompiler/tools/vivado/scripts/sc_syn_fpga.tcl,sha256=wBFkbSkmF7jzBz7PWqnllEFeg6vpK4RZUKLqktIM-HY,720
285
312
  siliconcompiler/tools/vpr/__init__.py,sha256=47DEQpj8HBSa-_TImW-5JCeuQeRkm5NMpJWZG3hSuFU,0
286
313
  siliconcompiler/tools/vpr/_json_constraint.py,sha256=7cEKHmzgFKd0K3NLiIxVgiUOa1tbeSLv7M132SLuQig,2254
@@ -289,7 +316,7 @@ siliconcompiler/tools/vpr/place.py,sha256=CwzEmQELZ5IUnQ6lg964icDhmcBOxcNI32Ysdg
289
316
  siliconcompiler/tools/vpr/route.py,sha256=uD4A2fSahluRhSJayjW1rfXt9pI3wWAbLIRU_YuXwlA,4876
290
317
  siliconcompiler/tools/vpr/screenshot.py,sha256=5Ji6J9p0R0C7C9WkuCwLu2InGQpeCo_Ciif7wUXz9ng,1818
291
318
  siliconcompiler/tools/vpr/show.py,sha256=Dm0efQaOa2G6FsDeo6BpNYEp0farqKQOXeF_JLBuSYo,3120
292
- siliconcompiler/tools/vpr/vpr.py,sha256=Ydzh25XqK70tH-IAdF2ZMBfYsCqpG7I9KSAaJEtuF4s,14410
319
+ siliconcompiler/tools/vpr/vpr.py,sha256=tg6D_RqZXB7aRGnQInV01v92qnSFTwA7-3vB1x88s54,14641
293
320
  siliconcompiler/tools/xdm/__init__.py,sha256=uEo7uTPRdoARmk0E5U8yQ_MZOntO-cWJfGb6_pPA0ZQ,729
294
321
  siliconcompiler/tools/xdm/convert.py,sha256=rlirszWfNs2x9KApd3AiKpx78B3bfQ5VVWv5Nk_LSuU,2371
295
322
  siliconcompiler/tools/xyce/__init__.py,sha256=YTSk-XGtviqthGmGHb6RCDEAIMUQ7ElYZjZzpa1aSBg,1297
@@ -302,17 +329,17 @@ siliconcompiler/tools/yosys/sc_lec.tcl,sha256=U86yboSq1TKiHKG2hjYUeO9wsCGvHLeQ6y
302
329
  siliconcompiler/tools/yosys/sc_screenshot.tcl,sha256=-7Bb-HhJsZjSdSIlYCTZnZgigwBoN_1FNik9Ba_flos,2853
303
330
  siliconcompiler/tools/yosys/sc_syn.tcl,sha256=ZtLbH-x9tPdZgHwcCLWZ4qQ4zqh1imLluj2LyW86P4k,2321
304
331
  siliconcompiler/tools/yosys/screenshot.py,sha256=Octzl15bG8LmXdyU-hv9QsP9GTrhoLYzdvi_yTRzXXo,5629
305
- siliconcompiler/tools/yosys/syn_asic.py,sha256=jEYfQTaTIPj4UHY2AKJocW3wMW2Prtgu6t55esNpZ_E,24106
306
- siliconcompiler/tools/yosys/syn_asic.tcl,sha256=MNUmV_qdkHfgDAPDb0urVwRLE65Y5xNodGOW4Zo7nTM,11957
332
+ siliconcompiler/tools/yosys/syn_asic.py,sha256=Q4s2lEiVVEeV_IEq4Qf8z3tp88G46HKpGhCL4ioTxsE,24495
333
+ siliconcompiler/tools/yosys/syn_asic.tcl,sha256=OXo20mKGy6LUYrXag3h51QzLePlp4pJgfbOj4WttngI,12487
307
334
  siliconcompiler/tools/yosys/syn_fpga.py,sha256=rF4TMBUhmtiWwdx1KJeW-cNiAnkTXmo_0htyuUE7plY,5427
308
- siliconcompiler/tools/yosys/syn_fpga.tcl,sha256=03w87fLgDwD65tDiUbkTBI-rKQUkMDnHI0u42UrA6D8,8030
335
+ siliconcompiler/tools/yosys/syn_fpga.tcl,sha256=GU1PACd1t6K_jLk2Ny7U6D8cxGHTgcwTmbCY1m4NEAs,8417
309
336
  siliconcompiler/tools/yosys/syn_strategies.tcl,sha256=YJ5bXCdUNDZZ4EY4wBGS-9m0EeNlANBIO9e5a_6A0KA,5329
310
337
  siliconcompiler/tools/yosys/yosys.py,sha256=77GTkg_ifbkJI5D2aRbj6rl1YNSDhZ139OWfXHag5VQ,4986
311
338
  siliconcompiler/tools/yosys/techmaps/__init__.py,sha256=47DEQpj8HBSa-_TImW-5JCeuQeRkm5NMpJWZG3hSuFU,0
312
339
  siliconcompiler/tools/yosys/techmaps/lcu_kogge_stone.v,sha256=M4T-ygiKmlsprl5eGGLaV5w6HVqlEepn0wlUDmOkapg,773
313
340
  siliconcompiler/tools/yosys/templates/__init__.py,sha256=47DEQpj8HBSa-_TImW-5JCeuQeRkm5NMpJWZG3hSuFU,0
314
341
  siliconcompiler/tools/yosys/templates/abc.const,sha256=TAq9ThdLMYCJGrtToEU0gWcLuEtjE4Gk8huBbTm1v-I,116
315
- siliconcompiler/toolscripts/_tools.json,sha256=I7xm0H0ev5Xe8_mZG94ABEJ5NO4fnO5DBBmbleFHYIU,3959
342
+ siliconcompiler/toolscripts/_tools.json,sha256=nc4Ro0ey2i10zpCRSjn1roD8QiwcnY4rRwkkn4GC3GY,3961
316
343
  siliconcompiler/toolscripts/_tools.py,sha256=P30KY_xbbjl8eHGsPAxDcAzWvJJpiL07ZfGZZDQbdR8,7174
317
344
  siliconcompiler/toolscripts/rhel8/install-chisel.sh,sha256=lPORZN7vlBX6sJSv01JOIiDE9-_7GcCZGA7EP5ri3MQ,525
318
345
  siliconcompiler/toolscripts/rhel8/install-ghdl.sh,sha256=xCLeEUuJVI_6PVEvnTwBsTWoEHiQg0TY3x-tJXfg6Zk,459
@@ -412,9 +439,9 @@ siliconcompiler/toolscripts/ubuntu24/install-yosys.sh,sha256=zpyt0MVI7tY8kGY2GII
412
439
  siliconcompiler/utils/__init__.py,sha256=6u8A5atgPW7cbC1xrerU67rlOM0FitCgxFIu5F_n5zo,14126
413
440
  siliconcompiler/utils/asic.py,sha256=cMLs7dneSmh5BlHS0-bZ1tLUpvghTw__gNaUCMpyBds,4986
414
441
  siliconcompiler/utils/showtools.py,sha256=qc5HLqCQxUITdhp9rESf0w_blAkKVYL6JpkXQdrew00,1406
415
- siliconcompiler-0.28.8.dist-info/LICENSE,sha256=lbLR6sRo_CYJOf7SVgHi-U6CZdD8esESEZE5TZazOQE,10766
416
- siliconcompiler-0.28.8.dist-info/METADATA,sha256=gebkDkb8zph1f-QBL3MlH-uAXGcbz8b5FU6hvNiHRm4,10907
417
- siliconcompiler-0.28.8.dist-info/WHEEL,sha256=R06PA3UVYHThwHvxuRWMqaGcr-PuniXahwjmQRFMEkY,91
418
- siliconcompiler-0.28.8.dist-info/entry_points.txt,sha256=TZVS-8akO-8Z1Z1oMjgWryzk_F9dAW74d2ArJV843pg,501
419
- siliconcompiler-0.28.8.dist-info/top_level.txt,sha256=H8TOYhnEUZAV1RJTa8JRtjLIebwHzkQUhA2wkNU2O6M,16
420
- siliconcompiler-0.28.8.dist-info/RECORD,,
442
+ siliconcompiler-0.29.0.dist-info/LICENSE,sha256=lbLR6sRo_CYJOf7SVgHi-U6CZdD8esESEZE5TZazOQE,10766
443
+ siliconcompiler-0.29.0.dist-info/METADATA,sha256=aCX3gJqoYrOrEmkz4LHcAVR2foZwz_ainn-xVzSkM1o,10939
444
+ siliconcompiler-0.29.0.dist-info/WHEEL,sha256=PZUExdf71Ui_so67QXpySuHtCi3-J3wvF4ORK6k_S8U,91
445
+ siliconcompiler-0.29.0.dist-info/entry_points.txt,sha256=TZVS-8akO-8Z1Z1oMjgWryzk_F9dAW74d2ArJV843pg,501
446
+ siliconcompiler-0.29.0.dist-info/top_level.txt,sha256=H8TOYhnEUZAV1RJTa8JRtjLIebwHzkQUhA2wkNU2O6M,16
447
+ siliconcompiler-0.29.0.dist-info/RECORD,,
@@ -1,5 +1,5 @@
1
1
  Wheel-Version: 1.0
2
- Generator: setuptools (75.5.0)
2
+ Generator: setuptools (75.6.0)
3
3
  Root-Is-Purelib: true
4
4
  Tag: py3-none-any
5
5
 
@@ -1,45 +0,0 @@
1
-
2
- from siliconcompiler.tools.openroad.openroad import setup as setup_tool
3
- from siliconcompiler.tools.openroad.openroad import build_pex_corners
4
- from siliconcompiler.tools.openroad.openroad import post_process as or_post_process
5
- from siliconcompiler.tools.openroad.openroad import pre_process as or_pre_process
6
- from siliconcompiler.tools.openroad.openroad import _set_reports, set_pnr_inputs, set_pnr_outputs
7
-
8
-
9
- def setup(chip):
10
- '''
11
- Perform clock tree synthesis and timing repair
12
- '''
13
-
14
- # Generic tool setup.
15
- setup_tool(chip)
16
-
17
- set_pnr_inputs(chip)
18
- set_pnr_outputs(chip)
19
-
20
- _set_reports(chip, [
21
- 'setup',
22
- 'hold',
23
- 'unconstrained',
24
- 'clock_skew',
25
- 'power',
26
- 'drv_violations',
27
- 'fmax',
28
-
29
- # Images
30
- 'placement_density',
31
- 'routing_congestion',
32
- 'power_density',
33
- 'clock_placement',
34
- 'clock_trees',
35
- 'optimization_placement'
36
- ])
37
-
38
-
39
- def pre_process(chip):
40
- or_pre_process(chip)
41
- build_pex_corners(chip)
42
-
43
-
44
- def post_process(chip):
45
- or_post_process(chip)
@@ -1,75 +0,0 @@
1
- from siliconcompiler.tools._common import input_provides, add_common_file, get_tool_task
2
- from siliconcompiler.tools._common.asic import set_tool_task_var
3
- from siliconcompiler.tools.openroad.openroad import setup as setup_tool
4
- from siliconcompiler.tools.openroad.openroad import build_pex_corners
5
- from siliconcompiler.tools.openroad.openroad import post_process as or_post_process
6
- from siliconcompiler.tools.openroad.openroad import pre_process as or_pre_process
7
- from siliconcompiler.tools.openroad.openroad import _set_reports, set_pnr_inputs, set_pnr_outputs
8
-
9
-
10
- def setup(chip):
11
- '''
12
- Perform floorplanning, pin placements, macro placements and power grid generation
13
- '''
14
-
15
- # Generic tool setup.
16
- setup_tool(chip)
17
-
18
- tool = 'openroad'
19
- design = chip.top()
20
- step = chip.get('arg', 'step')
21
- index = chip.get('arg', 'index')
22
- _, task = get_tool_task(chip, step, index)
23
-
24
- if chip.valid('input', 'asic', 'floorplan') and \
25
- chip.get('input', 'asic', 'floorplan', step=step, index=index):
26
- chip.add('tool', tool, 'task', task, 'require',
27
- ",".join(['input', 'asic', 'floorplan']),
28
- step=step, index=index)
29
-
30
- if f'{design}.vg' in input_provides(chip, step, index):
31
- chip.add('tool', tool, 'task', task, 'input', design + '.vg',
32
- step=step, index=index)
33
- else:
34
- chip.add('tool', tool, 'task', task, 'require', 'input,netlist,verilog',
35
- step=step, index=index)
36
-
37
- set_pnr_inputs(chip)
38
- set_pnr_outputs(chip)
39
-
40
- if chip.valid('tool', tool, 'task', task, 'file', 'padring') and \
41
- chip.get('tool', tool, 'task', task, 'file', 'padring',
42
- step=step, index=index):
43
- chip.add('tool', tool, 'task', task, 'require',
44
- ','.join(['tool', tool, 'task', task, 'file', 'padring']),
45
- step=step, index=index)
46
- chip.set('tool', tool, 'task', task, 'file', 'padring',
47
- 'script to insert the padring',
48
- field='help')
49
-
50
- set_tool_task_var(chip, param_key='remove_synth_buffers',
51
- default_value=True,
52
- schelp='remove buffers inserted by synthesis')
53
-
54
- snap = chip.get('tool', tool, 'task', task, 'var', 'ifp_snap_strategy',
55
- step=step, index=index)[0]
56
- snaps_allowed = ('none', 'site', 'manufacturing_grid')
57
- if snap not in snaps_allowed:
58
- chip.error(f'{snap} is not a supported snapping strategy. Allowed values: {snaps_allowed}')
59
-
60
- add_common_file(chip, 'sc_pin_constraint', 'tcl/sc_pin_constraints.tcl')
61
-
62
- _set_reports(chip, [
63
- 'setup',
64
- 'unconstrained',
65
- 'power'
66
- ])
67
-
68
-
69
- def pre_process(chip):
70
- or_pre_process(chip)
71
- build_pex_corners(chip)
72
-
73
-
74
- def post_process(chip):
75
- or_post_process(chip)
@@ -1,27 +0,0 @@
1
-
2
- from siliconcompiler.tools.openroad.openroad import setup as setup_tool
3
- from siliconcompiler.tools.openroad.openroad import build_pex_corners
4
- from siliconcompiler.tools.openroad.openroad import post_process as or_post_process
5
- from siliconcompiler.tools.openroad.openroad import pre_process as or_pre_process
6
- from siliconcompiler.tools.openroad.openroad import set_pnr_inputs, set_pnr_outputs
7
-
8
-
9
- def setup(chip):
10
- '''
11
- Not implemented yet
12
- '''
13
-
14
- # Generic tool setup.
15
- setup_tool(chip)
16
-
17
- set_pnr_inputs(chip)
18
- set_pnr_outputs(chip)
19
-
20
-
21
- def pre_process(chip):
22
- or_pre_process(chip)
23
- build_pex_corners(chip)
24
-
25
-
26
- def post_process(chip):
27
- or_post_process(chip)
@@ -1,41 +0,0 @@
1
-
2
- from siliconcompiler.tools.openroad.openroad import setup as setup_tool
3
- from siliconcompiler.tools.openroad.openroad import build_pex_corners
4
- from siliconcompiler.tools.openroad.openroad import post_process as or_post_process
5
- from siliconcompiler.tools.openroad.openroad import pre_process as or_pre_process
6
- from siliconcompiler.tools.openroad.openroad import _set_reports, set_pnr_inputs, set_pnr_outputs
7
-
8
-
9
- def setup(chip):
10
- '''
11
- Perform global and detail placements along with design violation repairs
12
- '''
13
-
14
- # Generic tool setup.
15
- setup_tool(chip)
16
-
17
- set_pnr_inputs(chip)
18
- set_pnr_outputs(chip)
19
-
20
- _set_reports(chip, [
21
- 'setup',
22
- 'unconstrained',
23
- 'power',
24
- 'drv_violations',
25
- 'fmax',
26
-
27
- # Images
28
- 'placement_density',
29
- 'routing_congestion',
30
- 'power_density',
31
- 'optimization_placement'
32
- ])
33
-
34
-
35
- def pre_process(chip):
36
- or_pre_process(chip)
37
- build_pex_corners(chip)
38
-
39
-
40
- def post_process(chip):
41
- or_post_process(chip)
@@ -1,45 +0,0 @@
1
-
2
- from siliconcompiler.tools.openroad.openroad import setup as setup_tool
3
- from siliconcompiler.tools.openroad.openroad import build_pex_corners
4
- from siliconcompiler.tools.openroad.openroad import post_process as or_post_process
5
- from siliconcompiler.tools.openroad.openroad import pre_process as or_pre_process
6
- from siliconcompiler.tools.openroad.openroad import _set_reports, set_pnr_inputs, set_pnr_outputs
7
-
8
-
9
- def setup(chip):
10
- '''
11
- Performs filler insertion, global routing, antenna repair, and detailed routing
12
- '''
13
-
14
- # Generic tool setup.
15
- setup_tool(chip)
16
-
17
- set_pnr_inputs(chip)
18
- set_pnr_outputs(chip)
19
-
20
- _set_reports(chip, [
21
- 'setup',
22
- 'hold',
23
- 'unconstrained',
24
- 'clock_skew',
25
- 'power',
26
- 'drv_violations',
27
- 'fmax',
28
-
29
- # Images
30
- 'placement_density',
31
- 'routing_congestion',
32
- 'power_density',
33
- 'clock_placement',
34
- 'clock_trees',
35
- 'optimization_placement'
36
- ])
37
-
38
-
39
- def pre_process(chip):
40
- or_pre_process(chip)
41
- build_pex_corners(chip)
42
-
43
-
44
- def post_process(chip):
45
- or_post_process(chip)
File without changes