siliconcompiler 0.28.8__py3-none-any.whl → 0.29.0__py3-none-any.whl

siliconcompiler/tools/vivado/vivado.py

@@ -67,36 +67,52 @@ def normalize_version(version):
 
 
 def _parse_qor_summary(chip, step, index):
-    if not os.path.isfile('qor_summary.json'):
+    if not os.path.isfile('reports/qor_summary.json'):
         return
 
-    with sc_open('qor_summary.json') as f:
+    with sc_open('reports/qor_summary.json') as f:
         data = json.load(f)
 
         # Data is organized as list of tasks that Vivado has completed, with
         # metrics associated with each. The tasks appear to be in chronological
         # order, so we pull metrics from the last one.
         task = data['Design QoR Summary'][-1]
-        setup_wns = task['Wns(ns)']
-        setup_tns = task['Tns(ns)']
-        hold_wns = task['Whs(ns)']
-        hold_tns = task['Ths(ns)']
+        setup_wns = None
+        for metric in ('Wns(ns)', 'WNS(ns)'):
+            if metric in task:
+                setup_wns = task[metric]
+                break
+        setup_tns = None
+        for metric in ('Tns(ns)', 'TNS(ns)'):
+            if metric in task:
+                setup_tns = task[metric]
+                break
+        hold_wns = None
+        for metric in ('Whs(ns)', 'WHS(ns)'):
+            if metric in task:
+                hold_wns = task[metric]
+                break
+        hold_tns = None
+        for metric in ('Ths(ns)', 'THS(ns)'):
+            if metric in task:
+                hold_tns = task[metric]
+                break
 
         if setup_wns:
             record_metric(chip, step, index, 'setupwns', setup_wns,
-                          'qor_summary.json',
+                          'reports/qor_summary.json',
                           source_unit='ns')
         if setup_tns:
             record_metric(chip, step, index, 'setuptns', setup_tns,
-                          'qor_summary.json',
+                          'reports/qor_summary.json',
                           source_unit='ns')
         if hold_wns:
             record_metric(chip, step, index, 'holdwns', hold_wns,
-                          'qor_summary.json',
+                          'reports/qor_summary.json',
                           source_unit='ns')
         if hold_tns:
             record_metric(chip, step, index, 'holdtns', hold_tns,
-                          'qor_summary.json',
+                          'reports/qor_summary.json',
                           source_unit='ns')
 
 

siliconcompiler/tools/vpr/vpr.py

@@ -94,6 +94,11 @@ def runtime_options(chip):
 
     options.append(f"--device {device_code[0]}")
 
+    # Medium-term solution:  VPR performs hash digest checks that
+    # fail if file paths are changed between steps.  We wish to
+    # disable the digest checks to work around this
+    options.append("--verify_file_digests off")
+
     options.append(f"--write_block_usage {__block_file}")
     options.append("--outfile_prefix outputs/")
 

siliconcompiler/tools/yosys/syn_asic.py

@@ -108,6 +108,13 @@ def setup_asic(chip):
         chip.add('tool', tool, 'task', task, 'require',
                  ",".join(['library', mainlib, 'option', 'file', 'yosys_addermap']),
                  step=step, index=index)
+    library_has_tbufmap = \
+        chip.valid('library', mainlib, 'option', 'file', 'yosys_tbufmap') and \
+        chip.get('library', mainlib, 'option', 'file', 'yosys_tbufmap')
+    if library_has_tbufmap:
+        chip.add('tool', tool, 'task', task, 'require',
+                 ",".join(['library', mainlib, 'option', 'file', 'yosys_tbufmap']),
+                 step=step, index=index)
 
     for var0, var1 in [('memory_libmap', 'memory_techmap')]:
         key0 = ['tool', tool, 'tak', task, 'file', var0]

siliconcompiler/tools/yosys/syn_asic.tcl

@@ -120,7 +120,7 @@ if { [sc_cfg_tool_task_exists file memory_techmap] } {
 # Schema helper functions
 #########################
 
-proc has_tie_cell { type } {
+proc sc_has_tie_cell { type } {
     upvar sc_cfg sc_cfg
     upvar sc_mainlib sc_mainlib
     upvar sc_tool sc_tool
@@ -131,7 +131,7 @@ proc has_tie_cell { type } {
     }]
 }
 
-proc get_tie_cell { type } {
+proc sc_get_tie_cell { type } {
     upvar sc_cfg sc_cfg
     upvar sc_mainlib sc_mainlib
     upvar sc_tool sc_tool
@@ -209,6 +209,18 @@ yosys hierarchy -top $sc_design
 # Mark modules to keep from getting removed in flattening
 preserve_modules
 
+# Handle tristate buffers
+set sc_tbuf "false"
+if {
+    [sc_cfg_exists library $sc_mainlib option file yosys_tbufmap] &&
+    [llength [sc_cfg_get library $sc_mainlib option file yosys_tbufmap]] != 0
+} {
+    set sc_tbuf "true"
+
+    yosys tribuf
+    yosys stat
+}
+
 set flatten_design [expr {
     [lindex [sc_cfg_tool_task_get var flatten] 0]
     == "true"
@@ -260,6 +272,15 @@ yosys opt -purge
 # Technology Mapping
 ########################################################
 
+# Handle tristate buffers
+if { $sc_tbuf == "true" } {
+    set sc_tbuf_techmap \
+        [lindex [sc_cfg_get library $sc_mainlib option file yosys_tbufmap] 0]
+    # Map tristate buffers
+    yosys techmap -map $sc_tbuf_techmap
+    post_techmap -fast
+}
+
 if { [sc_cfg_tool_task_get var map_adders] == "true" } {
     set sc_adder_techmap \
         [lindex [sc_cfg_get library $sc_mainlib option {file} yosys_addermap] 0]
@@ -356,11 +377,11 @@ yosys splitnets
 yosys clean -purge
 
 set yosys_hilomap_args []
-if { [has_tie_cell low] } {
-    lappend yosys_hilomap_args -locell {*}[get_tie_cell low]
+if { [sc_has_tie_cell low] } {
+    lappend yosys_hilomap_args -locell {*}[sc_get_tie_cell low]
 }
-if { [has_tie_cell high] } {
-    lappend yosys_hilomap_args -hicell {*}[get_tie_cell high]
+if { [sc_has_tie_cell high] } {
+    lappend yosys_hilomap_args -hicell {*}[sc_get_tie_cell high]
 }
 if { [llength $yosys_hilomap_args] != 0 } {
     yosys hilomap -singleton {*}$yosys_hilomap_args

siliconcompiler/tools/yosys/syn_fpga.tcl

@@ -125,6 +125,30 @@ if { [string match {ice*} $sc_partname] } {
     yosys proc
     yosys flatten
 
+    # Note there are two possibilities for how macro mapping might be done:
+    # using the extract command (to pattern match user RTL against
+    # the techmap) or using the techmap command.  The latter is better
+    # for mapping simple multipliers; the former is better (for now)
+    # for mapping more complex DSP blocks (MAC, pipelined blocks, etc).
+    # and is also more easily extensible to arbitrary hard macros.
+    # Run separate passes of both to get best of both worlds
+
+    # An extract pass needs to happen prior to other optimizations,
+    # otherwise yosys can transform its internal model into something
+    # that doesn't match the patterns defined in the extract library
+    if { [sc_cfg_exists fpga $sc_partname file yosys_extractlib] } {
+        set sc_syn_extractlibs \
+            [sc_cfg_get fpga $sc_partname file yosys_extractlib]
+
+        foreach extractlib $sc_syn_extractlibs {
+            yosys log "Run extract with $extractlib"
+            yosys extract -map $extractlib
+        }
+    }
+
+    # Other hard macro passes can happen after the generic optimization
+    # passes take place.
+
     #Generic optimization passes; this is a fusion of the VTR reference
     #flow and the Yosys synth_ice40 flow
     yosys opt_expr
@@ -141,28 +165,12 @@ if { [string match {ice*} $sc_partname] } {
     yosys opt_expr
     yosys opt_clean
 
+    # Here is a remaining customization pass for DSP tech mapping
+
     #Map DSP blocks before doing anything else,
     #so that we don't convert any math blocks
     #into other primitives
 
-    # Note there are two possibilities for how mapping might be done:
-    # using the extract command (to pattern match user RTL against
-    # the techmap) or using the techmap command.  The latter is better
-    # for mapping simple multipliers; the former is better (for now)
-    # for mapping more complex DSP blocks (MAC, pipelined blocks, etc).
-    # and also more extensible to arbitrary hard macros.  Run separate
-    # passes of both to get best of both worlds
-
-    if { [sc_cfg_exists fpga $sc_partname file yosys_extractlib] } {
-        set sc_syn_extractlibs \
-            [sc_cfg_get fpga $sc_partname file yosys_extractlib]
-
-        foreach extractlib $sc_syn_extractlibs {
-            yosys log "Run extract with $extractlib"
-            yosys extract -map $extractlib
-        }
-    }
-
     if { [sc_cfg_exists fpga $sc_partname file yosys_dsp_techmap] } {
         set sc_syn_dsp_library \
             [sc_cfg_get fpga $sc_partname file yosys_dsp_techmap]

siliconcompiler/toolscripts/_tools.json

@@ -1,7 +1,7 @@
 {
   "openroad": {
     "git-url": "https://github.com/The-OpenROAD-Project/OpenROAD.git",
-    "git-commit": "c3e802e73aa2ca2974874e487ae481fc4f2cb8c3",
+    "git-commit": "8495fc80c78f4ab98bebd8cf2050fa63bc0b93c1",
     "docker-cmds": [
       "# Remove OR-Tools files",
       "RUN rm -f $SC_PREFIX/Makefile $SC_PREFIX/README.md",
@@ -36,7 +36,7 @@
     "auto-update": false
   },
   "klayout": {
-    "version": "0.29.8",
+    "version": "0.29.10",
     "git-url": "https://github.com/KLayout/klayout.git",
     "docker-skip": true,
     "auto-update": true,
@@ -45,7 +45,7 @@
   },
   "sv2v": {
     "git-url": "https://github.com/zachjs/sv2v.git",
-    "git-commit": "7808819c48c167978aeb5ef34c6e5ed416e90875",
+    "git-commit": "5a636724d783edd403ac4618d6cc4def72e39cbc",
     "auto-update": true
   },
   "verilator": {
@@ -66,7 +66,7 @@
   },
   "vpr": {
     "git-url": "https://github.com/verilog-to-routing/vtr-verilog-to-routing.git",
-    "git-commit": "9dd5ff66e3ab43238f5a4cb14cafe17bc4afe527",
+    "git-commit": "de31f094aa4f894a5e6e0dc32c66365f4b341190",
     "auto-update": false
   },
   "icepack": {
@@ -91,7 +91,7 @@
   },
   "yosys": {
     "git-url": "https://github.com/YosysHQ/yosys.git",
-    "git-commit": "0.47",
+    "git-commit": "v0.48",
     "version-prefix": "",
     "auto-update": true
   },

{siliconcompiler-0.28.8.dist-info → siliconcompiler-0.29.0.dist-info}/METADATA

@@ -1,6 +1,6 @@
 Metadata-Version: 2.1
 Name: siliconcompiler
-Version: 0.28.8
+Version: 0.29.0
 Summary: A compiler framework that automates translation from source code to silicon.
 Author-email: Andreas Olofsson <andreas.d.olofsson@gmail.com>
 License: Apache License 2.0
@@ -25,55 +25,57 @@ Classifier: Topic :: Software Development :: Build Tools
 Requires-Python: >=3.8
 Description-Content-Type: text/markdown
 License-File: LICENSE
-Requires-Dist: requests ==2.32.3
-Requires-Dist: PyYAML ==6.0.2
-Requires-Dist: pandas >=1.1.5
-Requires-Dist: Jinja2 >=2.11.3
-Requires-Dist: graphviz ==0.20.3
-Requires-Dist: distro ==1.9.0
-Requires-Dist: packaging <24,>=21.3
-Requires-Dist: psutil >=5.8.0
-Requires-Dist: GitPython ==3.1.43
-Requires-Dist: lambdapdk >=0.1.38
-Requires-Dist: PyGithub ==2.5.0
-Requires-Dist: urllib3 >=1.26.0
-Requires-Dist: fasteners ==0.19
-Requires-Dist: fastjsonschema ==2.20.0
-Requires-Dist: docker ==7.1.0
-Requires-Dist: sc-surelog ==1.84.1
-Requires-Dist: orjson ==3.10.11
-Requires-Dist: streamlit ==1.40.1 ; python_full_version != "3.9.7"
-Requires-Dist: streamlit-agraph ==0.0.45 ; python_full_version != "3.9.7"
-Requires-Dist: streamlit-antd-components ==0.3.2 ; python_full_version != "3.9.7"
-Requires-Dist: streamlit-javascript ==0.1.5 ; python_full_version != "3.9.7"
-Requires-Dist: streamlit-autorefresh ==1.0.1 ; python_full_version != "3.9.7"
-Requires-Dist: importlib-metadata ; python_version < "3.10"
-Requires-Dist: aiohttp ==3.10.11 ; python_version <= "3.8"
-Requires-Dist: Pillow ==10.4.0 ; python_version <= "3.8"
-Requires-Dist: aiohttp ==3.11.2 ; python_version >= "3.9"
-Requires-Dist: Pillow ==11.0.0 ; python_version >= "3.9"
+Requires-Dist: aiohttp==3.10.11; python_version <= "3.8"
+Requires-Dist: aiohttp==3.11.10; python_version >= "3.9"
+Requires-Dist: requests==2.32.3
+Requires-Dist: PyYAML==6.0.2
+Requires-Dist: pandas>=1.1.5
+Requires-Dist: Jinja2>=2.11.3
+Requires-Dist: graphviz==0.20.3
+Requires-Dist: distro==1.9.0
+Requires-Dist: packaging<25,>=21.3
+Requires-Dist: psutil>=5.8.0
+Requires-Dist: Pillow==10.4.0; python_version <= "3.8"
+Requires-Dist: Pillow==11.0.0; python_version >= "3.9"
+Requires-Dist: GitPython==3.1.43
+Requires-Dist: lambdapdk>=0.1.40
+Requires-Dist: PyGithub==2.5.0
+Requires-Dist: urllib3>=1.26.0
+Requires-Dist: fasteners==0.19
+Requires-Dist: fastjsonschema==2.21.1
+Requires-Dist: docker==7.1.0
+Requires-Dist: importlib_metadata; python_version < "3.10"
+Requires-Dist: sc-surelog==1.84.1
+Requires-Dist: orjson==3.10.12
+Requires-Dist: streamlit==1.40.1; python_version <= "3.8"
+Requires-Dist: streamlit==1.40.2; python_version >= "3.9" and python_full_version != "3.9.7"
+Requires-Dist: streamlit_agraph==0.0.45; python_full_version != "3.9.7"
+Requires-Dist: streamlit-antd-components==0.3.2; python_full_version != "3.9.7"
+Requires-Dist: streamlit_javascript==0.1.5; python_full_version != "3.9.7"
+Requires-Dist: streamlit-autorefresh==1.0.1; python_full_version != "3.9.7"
+Provides-Extra: test
+Requires-Dist: pytest==8.3.4; extra == "test"
+Requires-Dist: pytest-xdist==3.6.1; extra == "test"
+Requires-Dist: pytest-timeout==2.3.1; extra == "test"
+Requires-Dist: pytest-asyncio==0.24.0; extra == "test"
+Requires-Dist: pytest-cov==5.0.0; python_version <= "3.8" and extra == "test"
+Requires-Dist: pytest-cov==6.0.0; python_version >= "3.9" and extra == "test"
+Requires-Dist: responses==0.25.3; extra == "test"
+Requires-Dist: PyVirtualDisplay==3.0; extra == "test"
+Provides-Extra: lint
+Requires-Dist: flake8==7.1.1; extra == "lint"
+Requires-Dist: tclint==0.5.0; extra == "lint"
+Requires-Dist: codespell==2.3.0; extra == "lint"
 Provides-Extra: docs
-Requires-Dist: Sphinx ==8.1.3 ; extra == 'docs'
-Requires-Dist: pip-licenses ==5.0.0 ; extra == 'docs'
-Requires-Dist: pydata-sphinx-theme ==0.16.0 ; extra == 'docs'
-Requires-Dist: sc-leflib >=0.2.0 ; extra == 'docs'
-Provides-Extra: examples
-Requires-Dist: migen ==0.9.2 ; extra == 'examples'
-Requires-Dist: lambdalib ==0.3.1 ; extra == 'examples'
+Requires-Dist: Sphinx==8.1.3; extra == "docs"
+Requires-Dist: pip-licenses==5.0.0; extra == "docs"
+Requires-Dist: pydata-sphinx-theme==0.16.0; extra == "docs"
+Requires-Dist: sc-leflib>=0.2.0; extra == "docs"
 Provides-Extra: profile
-Requires-Dist: gprof2dot ==2024.6.6 ; extra == 'profile'
-Provides-Extra: test
-Requires-Dist: pytest ==8.3.3 ; extra == 'test'
-Requires-Dist: pytest-xdist ==3.6.1 ; extra == 'test'
-Requires-Dist: pytest-timeout ==2.3.1 ; extra == 'test'
-Requires-Dist: pytest-asyncio ==0.24.0 ; extra == 'test'
-Requires-Dist: responses ==0.25.3 ; extra == 'test'
-Requires-Dist: PyVirtualDisplay ==3.0 ; extra == 'test'
-Requires-Dist: flake8 ==7.1.1 ; extra == 'test'
-Requires-Dist: tclint ==0.4.2 ; extra == 'test'
-Requires-Dist: codespell ==2.3.0 ; extra == 'test'
-Requires-Dist: pytest-cov ==5.0.0 ; (python_version <= "3.8") and extra == 'test'
-Requires-Dist: pytest-cov ==6.0.0 ; (python_version >= "3.9") and extra == 'test'
+Requires-Dist: gprof2dot==2024.6.6; extra == "profile"
+Provides-Extra: examples
+Requires-Dist: migen==0.9.2; extra == "examples"
+Requires-Dist: lambdalib==0.3.2; extra == "examples"
 
 ![SiliconCompiler](https://raw.githubusercontent.com/siliconcompiler/siliconcompiler/main/docs/_static/sc_logo_with_text.png)