siliconcompiler 0.28.3__py3-none-any.whl → 0.28.5__py3-none-any.whl

siliconcompiler/tools/openroad/scripts/sc_write_images.tcl

@@ -226,6 +226,12 @@ proc sc_image_clocks { } {
 proc sc_image_clocktree { } {
   gui::show_widget "Clock Tree Viewer"
   global sc_scenarios
+  global sc_design
+
+  sc_image_setup_default
+  gui::set_display_controls "Layers/*" visible true
+  gui::set_display_controls "Nets/*" visible false
+  gui::set_display_controls "Nets/Clock" visible true
 
   set clock_state []
   foreach clock [all_clocks] {
@@ -233,6 +239,7 @@ proc sc_image_clocktree { } {
   }
   set_propagated_clock [all_clocks]
 
+  file mkdir reports/images/clocks
   foreach clock [get_clocks *] {
     if { [llength [get_property $clock sources]] == 0 } {
       # Skip virtual clocks
@@ -243,13 +250,18 @@ proc sc_image_clocktree { } {
     set clock_name [get_name $clock]
     foreach corner $sc_scenarios {
       set path reports/images/clocktree/${clock_name}.${corner}.png
-      utl::info FLW 1 "Saving $clock_name clock tree for $corner in $path"
+      utl::info FLW 1 "Saving \"$clock_name\" clock tree for $corner to $path"
       save_clocktree_image $path \
         -clock $clock_name \
         -width 1024 \
         -height 1024 \
         -corner $corner
     }
+
+    if { [info commands gui::select_clockviewer_clock] != "" } {
+      gui::select_clockviewer_clock ${clock_name}
+      sc_save_image "clock - ${clock_name}" reports/images/clocks/${sc_design}.${clock_name}.png
+    }
   }
 
   foreach {clock state} $clock_state {
@@ -306,21 +318,39 @@ proc sc_image_optimizer { } {
   sc_save_image "optimizer" reports/images/${sc_design}.optimizer.png
 }
 
+proc sc_image_markers { } {
+  global sc_design
+  sc_image_setup_default
+
+  file mkdir reports/images/markers
+  foreach markerdb [[ord::get_db_block] getMarkerCategories] {
+    if { [$markerdb getMarkerCount] == 0 } {
+      continue
+    }
+
+    gui::select_marker_category $markerdb
+
+    sc_save_image \
+      "markers - [$markerdb getName]" \
+      reports/images/markers/${sc_design}.[$markerdb getName].png
+  }
+
+  gui::select_marker_category NULL
+}
+
 # Setup
 file mkdir reports/images
 gui::save_display_controls
 sc_image_setup_default
 
-if { [file exists reports/${sc_design}_drc.rpt] } {
-  # Show the drc markers (if any)
-  gui::load_drc reports/${sc_design}_drc.rpt
-}
-
 # General images
 sc_image_everything
 sc_image_placement
 sc_image_routing
 
+# Markers
+sc_image_markers
+
 # Heatmaps
 if { [sc_cfg_tool_task_check_in_list placement_density var reports] } {
   sc_image_placement_density

siliconcompiler/tools/opensta/scripts/sc_report_libraries.tcl

@@ -55,7 +55,17 @@ foreach lib "$sc_targetlibs $sc_macrolibs" {
 
 # Report cells
 foreach cell [get_lib_cells *] {
-    puts [get_full_name $cell]
+    set desc ""
+    if { [get_property $cell is_buffer] } {
+        set desc " (buffer)"
+    } elseif { [get_property $cell is_inverter] } {
+        set desc " (inverter)"
+    } elseif {
+        [llength [get_lib_pins -quiet [get_full_name $cell]/* -filter is_register_clock==1]] != 0
+    } {
+        set desc " (register)"
+    }
+    puts "[get_full_name $cell]$desc"
 
     set pins [get_lib_pins -quiet [get_full_name $cell]/*]
     if { [llength $pins] == 0 } {

siliconcompiler/tools/surelog/__init__.py

@@ -61,24 +61,36 @@ def setup(chip):
              field='help')
     chip.set('tool', tool, 'task', task, 'var', 'enable_lowmem', 'false',
              step=step, index=index, clobber=False)
+    chip.add('tool', tool, 'task', task, 'require',
+             ','.join(['tool', tool, 'task', task, 'var', 'enable_lowmem']),
+             step=step, index=index)
 
     chip.set('tool', tool, 'task', task, 'var', 'disable_write_cache',
              'true/false, when true instructs Surelog to not write to its cache.',
              field='help')
     chip.set('tool', tool, 'task', task, 'var', 'disable_write_cache', 'false',
              step=step, index=index, clobber=False)
+    chip.add('tool', tool, 'task', task, 'require',
+             ','.join(['tool', tool, 'task', task, 'var', 'disable_write_cache']),
+             step=step, index=index)
 
     chip.set('tool', tool, 'task', task, 'var', 'disable_info',
              'true/false, when true instructs Surelog to not log infos.',
              field='help')
     chip.set('tool', tool, 'task', task, 'var', 'disable_info', 'false',
              step=step, index=index, clobber=False)
+    chip.add('tool', tool, 'task', task, 'require',
+             ','.join(['tool', tool, 'task', task, 'var', 'disable_info']),
+             step=step, index=index)
 
     chip.set('tool', tool, 'task', task, 'var', 'disable_note',
              'true/false, when true instructs Surelog to not log notes.',
              field='help')
     chip.set('tool', tool, 'task', task, 'var', 'disable_note', 'false',
              step=step, index=index, clobber=False)
+    chip.add('tool', tool, 'task', task, 'require',
+             ','.join(['tool', tool, 'task', task, 'var', 'disable_note']),
+             step=step, index=index)
 
 
 def parse_version(stdout):

siliconcompiler/tools/verilator/compile.py

@@ -34,24 +34,42 @@ def setup(chip):
     if mode not in (['cc'], ['systemc']):
         chip.error(f"Invalid mode {mode} provided to verilator/compile. Expected one of 'cc' or "
                    "'systemc'")
+    chip.add('tool', tool, 'task', task, 'require',
+             ','.join(['tool', tool, 'task', task, 'var', 'mode']),
+             step=step, index=index)
 
     trace_type = chip.get('tool', tool, 'task', task, 'var', 'trace_type', step=step, index=index)
     if trace_type not in (['vcd'], ['fst']):
         chip.error(f"Invalid trace type {trace_type} provided to verilator/compile. Expected "
                    "one of 'vcd' or 'fst'.")
+    chip.add('tool', tool, 'task', task, 'require',
+             ','.join(['tool', tool, 'task', task, 'var', 'trace_type']),
+             step=step, index=index)
 
     chip.set('tool', tool, 'task', task, 'var', 'cflags',
              'flags to provide to the C++ compiler invoked by Verilator',
              field='help')
+    if chip.get('tool', tool, 'task', task, 'var', 'cflags', step=step, index=index):
+        chip.add('tool', tool, 'task', task, 'require',
+                 ','.join(['tool', tool, 'task', task, 'var', 'cflags']),
+                 step=step, index=index)
 
     chip.set('tool', tool, 'task', task, 'var', 'ldflags',
              'flags to provide to the linker invoked by Verilator',
              field='help')
+    if chip.get('tool', tool, 'task', task, 'var', 'ldflags', step=step, index=index):
+        chip.add('tool', tool, 'task', task, 'require',
+                 ','.join(['tool', tool, 'task', task, 'var', 'ldflags']),
+                 step=step, index=index)
 
     chip.set('tool', tool, 'task', task, 'var', 'pins_bv',
              'controls datatypes used to represent SystemC inputs/outputs. See --pins-bv in '
              'Verilator docs for more info.',
              field='help')
+    if chip.get('tool', tool, 'task', task, 'var', 'pins_bv', step=step, index=index):
+        chip.add('tool', tool, 'task', task, 'require',
+                 ','.join(['tool', tool, 'task', task, 'var', 'pins_bv']),
+                 step=step, index=index)
 
     chip.set('tool', tool, 'task', task, 'var', 'mode',
              "defines compilation mode for Verilator. Valid options are 'cc' for C++, or 'systemc' "
@@ -61,10 +79,19 @@ def setup(chip):
     chip.set('tool', tool, 'task', task, 'dir', 'cincludes',
              'include directories to provide to the C++ compiler invoked by Verilator',
              field='help')
+    if chip.get('tool', tool, 'task', task, 'dir', 'cincludes', step=step, index=index):
+        chip.add('tool', tool, 'task', task, 'require',
+                 ','.join(['tool', tool, 'task', task, 'dir', 'cincludes']),
+                 step=step, index=index)
 
     chip.set('tool', tool, 'task', task, 'var', 'trace',
              "if true, enables trace generation.",
              field='help')
+    if chip.get('tool', tool, 'task', task, 'var', 'trace', step=step, index=index):
+        chip.add('tool', tool, 'task', task, 'require',
+                 ','.join(['tool', tool, 'task', task, 'var', 'trace']),
+                 step=step, index=index)
+
     chip.set('tool', tool, 'task', task, 'var', 'trace_type',
              "specifies type of wave file to create when [trace] is set. Valid options are "
              "'vcd' or 'fst'. Defaults to 'vcd'.",

siliconcompiler/tools/verilator/verilator.py

@@ -71,6 +71,10 @@ def setup(chip):
     chip.set('tool', tool, 'task', task, 'file', 'config',
              'Verilator configuration file',
              field='help')
+    if chip.get('tool', tool, 'task', task, 'file', 'config', step=step, index=index):
+        chip.add('tool', tool, 'task', task, 'require',
+                 ','.join(['tool', tool, 'task', task, 'file', 'config']),
+                 step=step, index=index)
 
     chip.set('tool', tool, 'task', task, 'var', 'enable_assert',
              'true/false, when true assertions are enabled in Verilator.',
@@ -78,6 +82,11 @@ def setup(chip):
     chip.set('tool', tool, 'task', task, 'var', 'enable_assert', 'false',
              step=step, index=index, clobber=False)
 
+    if chip.get('tool', tool, 'task', task, 'var', 'enable_assert', step=step, index=index):
+        chip.add('tool', tool, 'task', task, 'require',
+                 ','.join(['tool', tool, 'task', task, 'var', 'enable_assert']),
+                 step=step, index=index)
+
     if f'{chip.top()}.v' not in input_provides(chip, step, index):
         add_require_input(chip, 'input', 'rtl', 'verilog')
         add_require_input(chip, 'input', 'rtl', 'systemverilog')

siliconcompiler/tools/vpr/vpr.py

@@ -66,6 +66,20 @@ def setup_tool(chip, clobber=True):
         chip.add('tool', tool, 'task', task, 'require', f'fpga,{part_name},var,{resource}',
                  step=step, index=index)
 
+    add_tool_requirements(chip)
+
+
+def add_tool_requirements(chip):
+
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    tool, task = get_tool_task(chip, step, index)
+
+    part_name = chip.get('fpga', 'partname')
+
+    chip.add('tool', tool, 'task', task, 'require', f'fpga,{part_name},var,vpr_device_code',
+             step=step, index=index)
+
 
 def runtime_options(chip):
 
@@ -76,6 +90,10 @@ def runtime_options(chip):
 
     options = []
 
+    device_code = chip.get('fpga', part_name, 'var', 'vpr_device_code')
+
+    options.append(f"--device {device_code[0]}")
+
     options.append(f"--write_block_usage {__block_file}")
     options.append("--outfile_prefix outputs/")
 

siliconcompiler/tools/xyce/__init__.py

@@ -7,7 +7,7 @@ and small-scale parallel runs on Unix-like systems.
 
 Documentation: https://xyce.sandia.gov/documentation-tutorials/
 
-Sources: https://github.com/Xyce/Xyce
+Sources: https://xyce.sandia.gov/downloads/source-code/
 
 Installation: https://xyce.sandia.gov/documentation-tutorials/building-guide/
 

siliconcompiler/tools/yosys/{syn_asic_fpga_shared.tcl → procs.tcl}

@@ -29,3 +29,26 @@ proc sc_map_memory { lib_file techmap_file do_rom } {
 
     return $design_mod
 }
+
+proc sc_apply_params { } {
+    global sc_design
+
+    yosys chparam -list $sc_design
+    if { [sc_cfg_exists option param] } {
+        yosys echo off
+        set module_params [yosys tee -q -s result.string chparam -list $sc_design]
+        yosys echo on
+
+        dict for {key value} [sc_cfg_get option param] {
+            if { ![string is integer $value] } {
+                set value [concat \"$value\"]
+            }
+
+            if { [string first $key $module_params] != -1 } {
+                yosys chparam -set $key $value $sc_design
+            } else {
+                puts "Warning: $key is not a defined parameter in $sc_design"
+            }
+        }
+    }
+}

siliconcompiler/tools/yosys/sc_screenshot.tcl

@@ -0,0 +1,104 @@
+###############################
+# Reading SC Schema
+###############################
+
+source ./sc_manifest.tcl
+
+yosys echo on
+
+###############################
+# Schema Adapter
+###############################
+
+set sc_tool yosys
+set sc_step [sc_cfg_get arg step]
+set sc_index [sc_cfg_get arg index]
+set sc_flow [sc_cfg_get option flow]
+set sc_task [sc_cfg_get flowgraph $sc_flow $sc_step $sc_index task]
+set sc_refdir [sc_cfg_tool_task_get refdir]
+
+####################
+# DESIGNER's CHOICE
+####################
+
+set sc_design [sc_top]
+
+########################################################
+# Helper function
+########################################################
+
+source "$sc_refdir/procs.tcl"
+
+########################################################
+# Design Inputs
+########################################################
+
+if { [file exists "inputs/$sc_design.v"] } {
+    set input_verilog "inputs/$sc_design.v"
+    yosys read_verilog -noblackbox -sv $input_verilog
+    set file_type "v"
+} elseif { [file exists "inputs/$sc_design.vg"] } {
+    set input_verilog "inputs/$sc_design.vg"
+    yosys read_verilog -noblackbox -sv $input_verilog
+    set file_type "vg"
+} elseif { [sc_cfg_tool_task_exists var show_filepath] } {
+    yosys read_verilog -noblackbox -sv [sc_cfg_tool_task_get var show_filepath]
+    set file_type [lindex [sc_cfg_tool_task_get var show_filetype] 0]
+}
+
+########################################################
+# Override top level parameters
+########################################################
+
+sc_apply_params
+
+########################################################
+# Read Libraries
+########################################################
+
+set sc_logiclibs [sc_get_asic_libraries logic]
+set sc_macrolibs [sc_get_asic_libraries macro]
+
+set sc_libraries [sc_cfg_tool_task_get {file} synthesis_libraries]
+if { [sc_cfg_tool_task_exists {file} synthesis_libraries_macros] } {
+    set sc_macro_libraries \
+        [sc_cfg_tool_task_get {file} synthesis_libraries_macros]
+} else {
+    set sc_macro_libraries []
+}
+
+set sc_blackboxes []
+foreach lib $sc_macrolibs {
+    if { [sc_cfg_exists library $lib output blackbox verilog] } {
+        foreach lib_f [sc_cfg_get library $lib output blackbox verilog] {
+            lappend sc_blackboxes $lib_f
+        }
+    }
+}
+
+foreach lib_file "$sc_libraries $sc_macro_libraries" {
+    yosys read_liberty -lib $lib_file
+}
+foreach bb_file $sc_blackboxes {
+    yosys log "Reading blackbox model file: $bb_file"
+    yosys read_verilog -sv $bb_file
+}
+
+########################################################
+# Screenshot
+########################################################
+
+yosys hierarchy -top $sc_design
+
+if { $file_type == "v" } {
+    yosys proc
+}
+
+yosys show \
+    -nobg \
+    -format png \
+    -width \
+    -signed \
+    -stretch \
+    -prefix outputs/${sc_design} \
+    $sc_design

siliconcompiler/tools/yosys/sc_syn.tcl

@@ -26,6 +26,12 @@ set sc_flow [sc_cfg_get option flow]
 set sc_optmode [sc_cfg_get option optmode]
 set sc_pdk [sc_cfg_get option pdk]
 
+########################################################
+# Helper function
+########################################################
+
+source "$sc_refdir/procs.tcl"
+
 ########################################################
 # Design Inputs
 ########################################################
@@ -57,15 +63,7 @@ if { [file exists "inputs/$sc_design.v"] } {
 # Override top level parameters
 ########################################################
 
-yosys chparam -list
-if { [sc_cfg_exists option param] } {
-    dict for {key value} [sc_cfg_get option param] {
-        if { ![string is integer $value] } {
-            set value [concat \"$value\"]
-        }
-        yosys chparam -set $key $value $sc_design
-    }
-}
+sc_apply_params
 
 ########################################################
 # Synthesis based on mode

siliconcompiler/tools/yosys/screenshot.py

@@ -0,0 +1,153 @@
+from siliconcompiler.tools.yosys.yosys import setup as tool_setup
+import os
+import siliconcompiler.tools.yosys.prepareLib as prepareLib
+from siliconcompiler.tools._common.asic import get_libraries
+from siliconcompiler.tools._common import get_tool_task
+from siliconcompiler.targets import asap7_demo
+
+
+def make_docs(chip):
+    chip.use(asap7_demo)
+
+
+def setup(chip):
+    '''
+    Generate a screenshot of the design
+    '''
+
+    # Generic tool setup.
+    tool_setup(chip)
+
+    # ASIC-specific setup.
+    # setup_asic(chip)
+
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    tool, task = get_tool_task(chip, step, index)
+    chip.set('tool', tool, 'task', task, 'input', [], step=step, index=index)
+    chip.set('tool', tool, 'task', task, 'script', 'sc_screenshot.tcl',
+             step=step, index=index)
+
+    design = chip.top()
+    chip.set('tool', tool, 'task', task, 'output', [design + '.dot', design + '.png'],
+             step=step, index=index)
+
+
+################################
+# format liberty files for yosys
+################################
+def prepare_asic_libraries(chip):
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    tool, task = get_tool_task(chip, step, index)
+
+    # Clear in case of rerun
+    for libtype in ('synthesis_libraries', 'synthesis_libraries_macros'):
+        chip.set('tool', tool, 'task', task, 'file', libtype, [],
+                 step=step, index=index)
+
+    # Generate synthesis_libraries and synthesis_macro_libraries for Yosys use
+
+    # mark libs with dont_use since ABC cannot get this information via its commands
+    # this also ensures the liberty files have been decompressed and corrected formatting
+    # issues that generally cannot be handled by yosys or yosys-abc
+    def get_synthesis_libraries(lib):
+        keypath = _get_synthesis_library_key(chip, lib)
+        if keypath and chip.valid(*keypath):
+            return chip.find_files(*keypath, step=step, index=index)
+        return []
+
+    for libtype in ('logic', 'macro'):
+        for lib in get_libraries(chip, libtype):
+            lib_content = {}
+            # Mark dont use
+            for lib_file in get_synthesis_libraries(lib):
+                # Ensure a unique name is used for library
+                lib_file_name_base = os.path.basename(lib_file)
+                if lib_file_name_base.lower().endswith('.gz'):
+                    lib_file_name_base = lib_file_name_base[0:-3]
+                if lib_file_name_base.lower().endswith('.lib'):
+                    lib_file_name_base = lib_file_name_base[0:-4]
+
+                lib_file_name = lib_file_name_base
+                unique_ident = 0
+                while lib_file_name in lib_content:
+                    lib_file_name = f'{lib_file_name_base}_{unique_ident}'
+                    unique_ident += 1
+
+                lib_content[lib_file_name] = prepareLib.processLibertyFile(
+                        lib_file,
+                        logger=None if chip.get('option', 'quiet',
+                                                step=step, index=index) else chip.logger)
+
+            if not lib_content:
+                continue
+
+            var_name = 'synthesis_libraries'
+            if libtype == "macro":
+                var_name = 'synthesis_libraries_macros'
+
+            for file, content in lib_content.items():
+                output_file = os.path.join(
+                    chip.getworkdir(step=step, index=index),
+                    'inputs',
+                    f'sc_{libtype}_{lib}_{file}.lib'
+                )
+
+                with open(output_file, 'w') as f:
+                    f.write(content)
+
+                chip.add('tool', tool, 'task', task, 'file', var_name, output_file,
+                         step=step, index=index)
+
+
+def get_synthesis_corner(chip):
+    tool = 'yosys'
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    _, task = get_tool_task(chip, step, index)
+
+    syn_corners = chip.get('tool', tool, 'task', task, 'var', 'synthesis_corner',
+                           step=step, index=index)
+    if syn_corners:
+        return syn_corners
+
+    # determine corner based on setup corner from constraints
+    corner = None
+    for constraint in chip.getkeys('constraint', 'timing'):
+        checks = chip.get('constraint', 'timing', constraint, 'check', step=step, index=index)
+        if "setup" in checks and not corner:
+            corner = chip.get('constraint', 'timing', constraint, 'libcorner',
+                              step=step, index=index)
+
+    if not corner:
+        # try getting it from first constraint with a valid libcorner
+        for constraint in chip.getkeys('constraint', 'timing'):
+            if not corner:
+                corner = chip.get('constraint', 'timing', constraint, 'libcorner',
+                                  step=step, index=index)
+
+    return corner
+
+
+def _get_synthesis_library_key(chip, lib):
+    if chip.valid('library', lib, 'option', 'file', 'yosys_synthesis_libraries'):
+        return ('library', lib, 'option', 'file', 'yosys_synthesis_libraries')
+
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    delaymodel = chip.get('asic', 'delaymodel', step=step, index=index)
+
+    for corner in chip.getkeys('library', lib, 'output'):
+        if chip.valid('library', lib, 'output', corner, delaymodel):
+            return ('library', lib, 'output', corner, delaymodel)
+
+    return None
+
+
+##################################################
+def pre_process(chip):
+    ''' Tool specific function to run before step execution
+    '''
+
+    prepare_asic_libraries(chip)

siliconcompiler/tools/yosys/syn_asic.py

@@ -74,6 +74,7 @@ def setup_asic(chip):
     mainlib = get_mainlib(chip)
     for option, value in [
             ('flatten', "true"),
+            ('auto_flatten', "true"),
             ('hier_iterations', "10"),
             ('hier_threshold', "1000"),
             ('autoname', "true"),
@@ -171,6 +172,8 @@ def setup_asic(chip):
     chip.set('tool', tool, 'task', task, 'var', 'add_buffers',
              'true/false, flag to indicate whether to add buffers or not.', field='help')
 
+    chip.set('tool', tool, 'task', task, 'var', 'auto_flatten',
+             'true/false, attempt to determine how to flatten the design', field='help')
     chip.set('tool', tool, 'task', task, 'var', 'hier_iterations',
              'Number of iterations to attempt to determine the hierarchy to flatten',
              field='help')

siliconcompiler/tools/yosys/syn_asic.tcl

@@ -1,8 +1,6 @@
 ####################
 # Helper functions
 ####################
-source "$sc_refdir/syn_asic_fpga_shared.tcl"
-
 proc preserve_modules { } {
     global sc_cfg
     global sc_tool
@@ -232,7 +230,7 @@ yosys synth {*}$synth_args -top $sc_design -run begin:fine
 sc_map_memory $sc_memory_libmap_files $sc_memory_techmap_files 0
 
 # Perform hierarchy flattening
-if { !$flatten_design } {
+if { !$flatten_design && [lindex [sc_cfg_tool_task_get var auto_flatten] 0] == "true" } {
     set sc_hier_iterations \
         [lindex [sc_cfg_tool_task_get var hier_iterations] 0]
     set sc_hier_threshold \

siliconcompiler/tools/yosys/syn_fpga.tcl

@@ -1,5 +1,6 @@
-source "$sc_refdir/syn_asic_fpga_shared.tcl"
-
+####################
+# Helper functions
+####################
 proc legalize_flops { feature_set } {
     set legalize_flop_types []
 

siliconcompiler/toolscripts/_tools.json

@@ -1,7 +1,7 @@
 {
   "openroad": {
     "git-url": "https://github.com/The-OpenROAD-Project/OpenROAD.git",
-    "git-commit": "3a75eb5d52a207622c3dfd52937d3a02488f76b5",
+    "git-commit": "1531ad983bfe91384e9253769fdc5f8dcf24fea8",
     "docker-cmds": [
       "# Remove OR-Tools files",
       "RUN rm -f $SC_PREFIX/Makefile $SC_PREFIX/README.md",
@@ -36,7 +36,7 @@
     "auto-update": false
   },
   "klayout": {
-    "version": "0.29.7",
+    "version": "0.29.8",
     "git-url": "https://github.com/KLayout/klayout.git",
     "docker-skip": true,
     "auto-update": true,
@@ -45,7 +45,7 @@
   },
   "sv2v": {
     "git-url": "https://github.com/zachjs/sv2v.git",
-    "git-commit": "5374679e4bb26e115b9a9b4a2d8ef4253d7a8bf3",
+    "git-commit": "7808819c48c167978aeb5ef34c6e5ed416e90875",
     "auto-update": true
   },
   "verilator": {
@@ -91,13 +91,12 @@
   },
   "yosys": {
     "git-url": "https://github.com/YosysHQ/yosys.git",
-    "git-commit": "0.46",
+    "git-commit": "0.47",
     "version-prefix": "",
     "auto-update": true
   },
   "xyce": {
-    "git-url": "https://github.com/Xyce/Xyce.git",
-    "version": "7.8.0",
+    "version": "7.8",
     "auto-update": false
   },
   "xdm": {