siliconcompiler 0.28.3__py3-none-any.whl → 0.28.5__py3-none-any.whl

siliconcompiler/tools/_common/__init__.py

@@ -2,7 +2,7 @@ import os
 import pkgutil
 
 
-def get_libraries(chip, include_asic=True, library=None, libraries=None):
+def __get_library_keys(chip, include_asic=True, library=None, libraries=None):
     '''
     Returns a list of libraries included in this step/index
 
@@ -24,18 +24,52 @@ def get_libraries(chip, include_asic=True, library=None, libraries=None):
 
     def get_libs(*key):
         if chip.valid(*key) and chip.get(*key, step=step, index=index):
-            return chip.get(*key, step=step, index=index)
+            if chip.get(*key, step=step, index=index):
+                return [key]
         return []
 
     if include_asic:
         libs.extend(get_libs(*pref_key, 'asic', 'logiclib'))
         libs.extend(get_libs(*pref_key, 'asic', 'macrolib'))
 
-    for lib in get_libs(*pref_key, 'option', 'library'):
-        if lib in libs or lib in libraries:
+    libnames = set()
+    if library:
+        libnames.add(library)
+    for lib_key in get_libs(*pref_key, 'option', 'library'):
+        if lib_key in libs:
             continue
-        libs.append(lib)
-        libs.extend(get_libraries(chip, include_asic=include_asic, library=lib, libraries=libs))
+
+        libs.append(lib_key)
+
+        for libname in chip.get(*lib_key, step=step, index=index):
+            if libname in libnames:
+                continue
+
+            libnames.add(libname)
+            libs.extend(__get_library_keys(
+                chip,
+                include_asic=include_asic,
+                library=libname,
+                libraries=libnames))
+
+    return set(libs)
+
+
+def get_libraries(chip, include_asic=True):
+    '''
+    Returns a list of libraries included in this step/index
+
+    Args:
+        chip (Chip): Chip object
+        include_asic (bool): include the asic libraries.
+    '''
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+
+    libs = []
+
+    for key in __get_library_keys(chip, include_asic=include_asic):
+        libs.extend(chip.get(*key, step=step, index=index))
 
     return set(libs)
 
@@ -212,6 +246,10 @@ def add_frontend_requires(chip, supports=None):
     step = chip.get('arg', 'step')
     index = chip.get('arg', 'index')
     tool, task = get_tool_task(chip, step, index)
+
+    for libkey in __get_library_keys(chip):
+        chip.add('tool', tool, 'task', task, 'require', ','.join(libkey), step=step, index=index)
+
     for opt in supports:
         for key in opt_keys[opt]:
             chip.add('tool', tool, 'task', task, 'require', ','.join(key), step=step, index=index)

siliconcompiler/tools/_common/asic.py

@@ -47,7 +47,8 @@ def set_tool_task_var(chip,
                       option_key=None,
                       pdk_key=None,
                       lib_key=None,
-                      require=None):
+                      require=None,
+                      skip=None):
     '''
     Set parameter from PDK -> main library -> option -> default_value
     '''
@@ -56,7 +57,11 @@ def set_tool_task_var(chip,
     tool, task = _common.get_tool_task(chip, step, index)
     pdkname = chip.get('option', 'pdk')
     stackup = chip.get('option', 'stackup')
-    mainlib = get_mainlib(chip)
+
+    if not skip:
+        skip = []
+    if not isinstance(skip, (list, tuple)):
+        skip = [skip]
 
     if not require:
         require = []
@@ -66,31 +71,35 @@ def set_tool_task_var(chip,
     check_keys = []
 
     # Add PDK key
-    if not pdk_key:
-        pdk_key = param_key
-    check_keys.append(['pdk', pdkname, 'var', tool, stackup, pdk_key])
-    if 'pdk' in require:
-        chip.add('tool', tool, 'task', task, 'require',
-                 ','.join(check_keys[-1]),
-                 step=step, index=index)
+    if 'pdk' not in skip:
+        if not pdk_key:
+            pdk_key = param_key
+        check_keys.append(['pdk', pdkname, 'var', tool, stackup, pdk_key])
+        if 'pdk' in require:
+            chip.add('tool', tool, 'task', task, 'require',
+                     ','.join(check_keys[-1]),
+                     step=step, index=index)
 
     # Add library key
-    if not lib_key:
-        lib_key = f'{tool}_{param_key}'
-    check_keys.append(['library', mainlib, 'option', 'var', lib_key])
-    if 'lib' in require:
-        chip.add('tool', tool, 'task', task, 'require',
-                 ','.join(check_keys[-1]),
-                 step=step, index=index)
+    if 'lib' not in skip:
+        mainlib = get_mainlib(chip)
+        if not lib_key:
+            lib_key = f'{tool}_{param_key}'
+        check_keys.append(['library', mainlib, 'option', 'var', lib_key])
+        if 'lib' in require:
+            chip.add('tool', tool, 'task', task, 'require',
+                     ','.join(check_keys[-1]),
+                     step=step, index=index)
 
     # Add option key
-    if not option_key:
-        option_key = f'{tool}_{param_key}'
-    check_keys.append(['option', 'var', option_key])
-    if 'option' in require:
-        chip.add('tool', tool, 'task', task, 'require',
-                 ','.join(check_keys[-1]),
-                 step=step, index=index)
+    if 'option' not in skip:
+        if not option_key:
+            option_key = f'{tool}_{param_key}'
+        check_keys.append(['option', 'var', option_key])
+        if 'option' in require:
+            chip.add('tool', tool, 'task', task, 'require',
+                     ','.join(check_keys[-1]),
+                     step=step, index=index)
 
     require_key, value = _common.pick_key(chip, reversed(check_keys), step=step, index=index)
     if not value:
@@ -113,3 +122,50 @@ def set_tool_task_var(chip,
     if schelp:
         chip.set('tool', tool, 'task', task, 'var', param_key,
                  schelp, field='help')
+
+    return value
+
+
+def get_tool_task_var(chip,
+                      param_key,
+                      option_key=None,
+                      pdk_key=None,
+                      lib_key=None,
+                      skip=None):
+    '''
+    Get parameter from PDK -> main library -> option -> default_value
+    '''
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    tool, _ = _common.get_tool_task(chip, step, index)
+    pdkname = chip.get('option', 'pdk')
+    stackup = chip.get('option', 'stackup')
+
+    if not skip:
+        skip = []
+    if not isinstance(skip, (list, tuple)):
+        skip = [skip]
+
+    check_keys = []
+    # Add PDK key
+    if 'pdk' not in skip:
+        if not pdk_key:
+            pdk_key = param_key
+        check_keys.append(['pdk', pdkname, 'var', tool, stackup, pdk_key])
+
+    # Add library key
+    if 'lib' not in skip:
+        mainlib = get_mainlib(chip)
+        if not lib_key:
+            lib_key = f'{tool}_{param_key}'
+        check_keys.append(['library', mainlib, 'option', 'var', lib_key])
+
+    # Add option key
+    if 'option' not in skip:
+        if not option_key:
+            option_key = f'{tool}_{param_key}'
+        check_keys.append(['option', 'var', option_key])
+
+    _, value = _common.pick_key(chip, reversed(check_keys), step=step, index=index)
+
+    return value

siliconcompiler/tools/genfasm/genfasm.py

@@ -1,5 +1,6 @@
 from siliconcompiler.tools.vpr.vpr import parse_version as vpr_parse_version
 from siliconcompiler.tools.vpr.vpr import normalize_version as vpr_normalize_version
+from siliconcompiler.tools.vpr.vpr import add_tool_requirements as add_vpr_requirements
 
 '''
 Generate a `FSAM <https://github.com/chipsalliance/fasm>`_ file from the output of
@@ -25,6 +26,12 @@ def setup(chip):
     chip.set('tool', 'genfasm', 'vswitch', '--version')
     chip.set('tool', 'genfasm', 'version', '>=8.1.0', clobber=False)
 
+    add_tool_requirements(chip)
+
+
+def add_tool_requirements(chip):
+    add_vpr_requirements(chip)
+
 
 def parse_version(chip):
     return vpr_parse_version(chip)

siliconcompiler/tools/ghdl/convert.py

@@ -40,6 +40,13 @@ def setup(chip):
 
     chip.set('tool', tool, 'task', task, 'output', f'{design}.v', step=step, index=index)
 
+    chip.set('tool', tool, 'task', task, 'var', 'extraopts', 'extra options to pass to ghdl',
+             field='help')
+    if chip.get('tool', tool, 'task', task, 'var', 'extraopts', step=step, index=index):
+        chip.add('tool', tool, 'task', task, 'require',
+                 ','.join(['tool', tool, 'task', task, 'var', 'extraopts']),
+                 step=step, index=index)
+
 
 ################################
 #  Custom runtime options

siliconcompiler/tools/klayout/convert_drc_db.py

@@ -0,0 +1,60 @@
+from siliconcompiler.tools._common import input_provides, input_file_node_name, get_tool_task
+
+from siliconcompiler.tools.klayout import klayout
+from siliconcompiler.tools.klayout.klayout import setup as setup_tool
+
+
+def make_docs(chip):
+    klayout.make_docs(chip)
+
+
+def setup(chip):
+    '''
+    Convert a DRC db from .lyrdb or .ascii to an openroad json marker file
+    '''
+
+    # Generic tool setup.
+    setup_tool(chip)
+
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    tool, task = get_tool_task(chip, step, index)
+    design = chip.top()
+
+    clobber = False
+
+    chip.set('tool', tool, 'task', task, 'threads', 1,
+             step=step, index=index, clobber=clobber)
+
+    script = 'klayout_convert_drc_db.py'
+    option = ['-z', '-nc', '-rx', '-r']
+    chip.set('tool', tool, 'task', task, 'script', script,
+             step=step, index=index, clobber=clobber)
+    chip.set('tool', tool, 'task', task, 'option', option,
+             step=step, index=index, clobber=clobber)
+
+    input_nodes = set()
+    for nodes in input_provides(chip, step, index).values():
+        input_nodes.update(nodes)
+
+    chip.set('tool', tool, 'task', task, 'input', [], step=step, index=index)
+    chip.set('tool', tool, 'task', task, 'output', [], step=step, index=index)
+    for file, nodes in input_provides(chip, step, index).items():
+        if file not in (f'{design}.lyrdb', f'{design}.ascii'):
+            continue
+
+        if len(input_nodes) == 1:
+            chip.add('tool', tool, 'task', task, 'input',
+                     file,
+                     step=step, index=index)
+        else:
+            for in_step, in_index in nodes:
+                chip.add('tool', tool, 'task', task, 'input',
+                         input_file_node_name(file, in_step, in_index),
+                         step=step, index=index)
+    if not chip.get('tool', tool, 'task', task, 'input', step=step, index=index):
+        chip.add('tool', tool, 'task', task, 'input', f'{design}.lyrdb',
+                 step=step, index=index)
+
+    chip.set('tool', tool, 'task', task, 'output', f'{design}.json',
+             step=step, index=index)

siliconcompiler/tools/klayout/drc.py

@@ -0,0 +1,156 @@
+import os
+import shlex
+
+from siliconcompiler.tools._common import input_provides, has_input_files, \
+    get_input_files, get_tool_task, record_metric
+from siliconcompiler.tools._common.asic import set_tool_task_var, get_tool_task_var
+
+from siliconcompiler.tools.klayout import klayout
+from siliconcompiler.tools.klayout.klayout import setup as setup_tool
+import xml.etree.ElementTree as ET
+
+
+def make_docs(chip):
+    klayout.make_docs(chip)
+    chip.set('tool', 'klayout', 'task', 'drc', 'var', 'drc_name', '<drc_name>',
+             step='<step>', index='<index>')
+
+
+def setup(chip):
+    '''
+    Performs a design rule check on the provided layout
+    '''
+
+    # Generic tool setup.
+    setup_tool(chip)
+
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    tool, task = get_tool_task(chip, step, index)
+    design = chip.top()
+
+    clobber = False
+
+    option = ['-z', '-nc', '-rx']
+    chip.set('tool', tool, 'task', task, 'option', option,
+             step=step, index=index, clobber=clobber)
+
+    chip.set('tool', tool, 'task', task, 'threads', os.cpu_count(),
+             step=step, index=index, clobber=clobber)
+
+    chip.add('tool', tool, 'task', task, 'require', 'option,pdk')
+    chip.add('tool', tool, 'task', task, 'require', 'option,stackup')
+
+    chip.set('tool', tool, 'task', task, 'var', 'drc_name', 'drc',
+             step=step, index=index, clobber=False)
+    chip.add('tool', tool, 'task', task, 'require', f'tool,{tool},task,{task},var,drc_name',
+             step=step, index=index)
+
+    drc_name = chip.get('tool', tool, 'task', task, 'var', 'drc_name', step=step, index=index)
+    if not drc_name:
+        raise ValueError('drc_name is required')
+    drc_name = drc_name[0]
+
+    pdk = chip.get('option', 'pdk')
+    stackup = chip.get('option', 'stackup')
+    chip.add('tool', tool, 'task', task, 'require',
+             f'pdk,{pdk},drc,runset,klayout,{stackup},{drc_name}')
+
+    if f'{design}.gds' in input_provides(chip, step, index):
+        chip.add('tool', tool, 'task', task, 'input', design + '.gds',
+                 step=step, index=index)
+    elif f'{design}.oas' in input_provides(chip, step, index):
+        chip.add('tool', tool, 'task', task, 'input', design + '.oas',
+                 step=step, index=index)
+    elif has_input_files(chip, 'input', 'layout', 'oas', check_library_files=False):
+        chip.add('tool', tool, 'task', task, 'require', 'input,layout,oas',
+                 step=step, index=index)
+    else:
+        chip.add('tool', tool, 'task', task, 'require', 'input,layout,gds',
+                 step=step, index=index)
+
+    chip.add('tool', tool, 'task', task, 'output', design + '.lyrdb',
+             step=step, index=index)
+
+    set_tool_task_var(
+        chip,
+        f'drc_params:{drc_name}',
+        schelp="Input parameter to DRC script, in the form of key=value, if the value "
+               "is <topcell>, <input>, <report>, <threads> these will be automatically "
+               "determined.",
+        skip='lib')
+
+
+def runtime_options(chip):
+    design = chip.top()
+
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    tool, task = get_tool_task(chip, step, index)
+
+    pdk = chip.get('option', 'pdk')
+    stackup = chip.get('option', 'stackup')
+
+    layout = None
+    for file in [f'inputs/{design}.gds', f'inputs/{design}.oas']:
+        if os.path.isfile(file):
+            layout = file
+            break
+
+    if not layout:
+        for file in [
+                get_input_files(chip, 'input', 'layout', 'oas', add_library_files=False),
+                get_input_files(chip, 'input', 'layout', 'gds', add_library_files=False)]:
+            if file:
+                layout = file[0]
+
+    threads = chip.get('tool', tool, 'task', task, 'threads', step=step, index=index)
+    if not threads:
+        threads = 1
+
+    drc_name = chip.get('tool', tool, 'task', task, 'var', 'drc_name',
+                        step=step, index=index)[0]
+    report = os.path.abspath(f"outputs/{chip.top()}.lyrdb")
+
+    runset = chip.find_files('pdk', pdk, 'drc', 'runset', 'klayout', stackup, drc_name)[0]
+
+    params_lookup = {
+        "<topcell>": chip.top(),
+        "<report>": shlex.quote(report),
+        "<threads>": threads,
+        "<input>": shlex.quote(layout)
+    }
+
+    args = [
+        '-r', shlex.quote(runset)
+    ]
+
+    for param in get_tool_task_var(chip, f'drc_params:{drc_name}', skip='lib'):
+        for lookup, value in params_lookup.items():
+            param = param.replace(lookup, str(value))
+        args.extend(
+            ['-rd', param]
+        )
+    return args
+
+
+def post_process(chip):
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+
+    drc_db = f"outputs/{chip.top()}.lyrdb"
+
+    drc_report = None
+    if os.path.isfile(drc_db):
+        with open(drc_db, "r") as f:
+            drc_report = ET.fromstring(f.read())
+    if drc_report is None:
+        drc_db = []
+
+    violation_count = 0
+    if drc_report:
+        violations = drc_report.find('items')
+        if violations:
+            violation_count = len(violations.findall('item'))
+
+    record_metric(chip, step, index, 'drcs', violation_count, drc_db)

siliconcompiler/tools/klayout/export.py

@@ -19,6 +19,8 @@ def setup(chip):
     _, task = get_tool_task(chip, step, index)
     clobber = False
 
+    chip.set('tool', tool, 'task', task, 'threads', 1, step=step, index=index, clobber=clobber)
+
     script = 'klayout_export.py'
     option = ['-z', '-nc', '-rx', '-r']
     chip.set('tool', tool, 'task', task, 'script', script, step=step, index=index, clobber=clobber)
@@ -39,11 +41,9 @@ def setup(chip):
                               step=step, index=index)[0]
     sc_stream_order = [default_stream, *[s for s in streams if s != default_stream]]
 
-    if stackup and targetlibs:
+    if stackup:
         macrolibs = get_libraries(chip, 'macro')
 
-        chip.add('tool', tool, 'task', task, 'require', ",".join(['asic', 'logiclib']),
-                 step=step, index=index)
         chip.add('tool', tool, 'task', task, 'require', ",".join(['option', 'stackup']),
                  step=step, index=index)
         req_set = False
@@ -81,7 +81,12 @@ def setup(chip):
                      ",".join(['library', lib, 'output', stackup, 'lef']),
                      step=step, index=index)
     else:
-        chip.error('Stackup and targetlib parameters required for Klayout.')
+        chip.error('Stackup parameter required for Klayout.')
+
+    if not targetlibs:
+        chip.add('tool', tool, 'task', task, 'require',
+                 'option,var,klayout_libtype',
+                 step=step, index=index)
 
     # Input/Output requirements for default flow
     design = chip.top()

siliconcompiler/tools/klayout/klayout.py

@@ -82,7 +82,6 @@ def setup(chip, mode="batch"):
 
     chip.set('tool', tool, 'task', task, 'refdir', refdir, step=step, index=index,
              package='siliconcompiler', clobber=clobber)
-    chip.set('tool', tool, 'task', task, 'threads', 1, step=step, index=index, clobber=clobber)
 
     if chip.get('option', 'nodisplay'):
         # Tells QT to use the offscreen platform if nodisplay is used