siliconcompiler 0.28.3__py3-none-any.whl → 0.28.5__py3-none-any.whl
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- siliconcompiler/_metadata.py +1 -1
- siliconcompiler/apps/_common.py +88 -56
- siliconcompiler/apps/sc.py +33 -14
- siliconcompiler/apps/sc_dashboard.py +17 -10
- siliconcompiler/apps/sc_show.py +17 -15
- siliconcompiler/core.py +95 -55
- siliconcompiler/flows/drcflow.py +13 -0
- siliconcompiler/flows/interposerflow.py +17 -0
- siliconcompiler/fpgas/vpr_example.py +8 -0
- siliconcompiler/libs/interposer.py +8 -0
- siliconcompiler/package.py +3 -2
- siliconcompiler/pdks/interposer.py +8 -0
- siliconcompiler/remote/schema.py +11 -1
- siliconcompiler/remote/server.py +7 -2
- siliconcompiler/report/dashboard/__init__.py +9 -0
- siliconcompiler/report/dashboard/components/__init__.py +13 -1
- siliconcompiler/report/dashboard/layouts/vertical_flowgraph.py +4 -3
- siliconcompiler/report/dashboard/layouts/vertical_flowgraph_node_tab.py +4 -1
- siliconcompiler/report/dashboard/layouts/vertical_flowgraph_sac_tabs.py +4 -1
- siliconcompiler/report/dashboard/state.py +3 -1
- siliconcompiler/report/summary_table.py +1 -2
- siliconcompiler/report/utils.py +1 -2
- siliconcompiler/scheduler/__init__.py +95 -0
- siliconcompiler/schema/schema_cfg.py +15 -3
- siliconcompiler/schema/schema_obj.py +51 -1
- siliconcompiler/sphinx_ext/dynamicgen.py +6 -0
- siliconcompiler/targets/interposer_demo.py +56 -0
- siliconcompiler/templates/tcl/manifest.tcl.j2 +2 -0
- siliconcompiler/tools/_common/__init__.py +44 -6
- siliconcompiler/tools/_common/asic.py +79 -23
- siliconcompiler/tools/genfasm/genfasm.py +7 -0
- siliconcompiler/tools/ghdl/convert.py +7 -0
- siliconcompiler/tools/klayout/convert_drc_db.py +60 -0
- siliconcompiler/tools/klayout/drc.py +156 -0
- siliconcompiler/tools/klayout/export.py +9 -4
- siliconcompiler/tools/klayout/klayout.py +0 -1
- siliconcompiler/tools/klayout/klayout_convert_drc_db.py +182 -0
- siliconcompiler/tools/klayout/klayout_export.py +3 -0
- siliconcompiler/tools/klayout/klayout_utils.py +8 -2
- siliconcompiler/tools/klayout/operations.py +2 -0
- siliconcompiler/tools/klayout/screenshot.py +2 -0
- siliconcompiler/tools/klayout/show.py +4 -4
- siliconcompiler/tools/magic/drc.py +21 -0
- siliconcompiler/tools/magic/extspice.py +21 -0
- siliconcompiler/tools/magic/magic.py +29 -0
- siliconcompiler/tools/magic/sc_drc.tcl +2 -12
- siliconcompiler/tools/magic/sc_extspice.tcl +3 -15
- siliconcompiler/tools/openroad/metrics.py +45 -0
- siliconcompiler/tools/openroad/openroad.py +47 -2
- siliconcompiler/tools/openroad/rdlroute.py +97 -0
- siliconcompiler/tools/openroad/scripts/sc_apr.tcl +16 -1
- siliconcompiler/tools/openroad/scripts/sc_floorplan.tcl +55 -9
- siliconcompiler/tools/openroad/scripts/sc_metrics.tcl +0 -159
- siliconcompiler/tools/openroad/scripts/sc_procs.tcl +3 -1
- siliconcompiler/tools/openroad/scripts/sc_rdlroute.tcl +184 -0
- siliconcompiler/tools/openroad/scripts/sc_report.tcl +170 -0
- siliconcompiler/tools/openroad/scripts/sc_route.tcl +8 -2
- siliconcompiler/tools/openroad/scripts/sc_screenshot.tcl +0 -5
- siliconcompiler/tools/openroad/scripts/sc_write_images.tcl +36 -6
- siliconcompiler/tools/opensta/scripts/sc_report_libraries.tcl +11 -1
- siliconcompiler/tools/surelog/__init__.py +12 -0
- siliconcompiler/tools/verilator/compile.py +27 -0
- siliconcompiler/tools/verilator/verilator.py +9 -0
- siliconcompiler/tools/vpr/vpr.py +18 -0
- siliconcompiler/tools/xyce/__init__.py +1 -1
- siliconcompiler/tools/yosys/{syn_asic_fpga_shared.tcl → procs.tcl} +23 -0
- siliconcompiler/tools/yosys/sc_screenshot.tcl +104 -0
- siliconcompiler/tools/yosys/sc_syn.tcl +7 -9
- siliconcompiler/tools/yosys/screenshot.py +153 -0
- siliconcompiler/tools/yosys/syn_asic.py +3 -0
- siliconcompiler/tools/yosys/syn_asic.tcl +1 -3
- siliconcompiler/tools/yosys/syn_fpga.tcl +3 -2
- siliconcompiler/toolscripts/_tools.json +5 -6
- siliconcompiler/toolscripts/rhel8/install-xyce.sh +4 -5
- siliconcompiler/toolscripts/rhel9/install-xyce.sh +4 -5
- siliconcompiler/toolscripts/ubuntu20/install-xyce.sh +5 -5
- siliconcompiler/toolscripts/ubuntu22/install-xyce.sh +2 -2
- siliconcompiler/toolscripts/ubuntu24/install-xyce.sh +2 -2
- siliconcompiler/utils/__init__.py +30 -1
- siliconcompiler/utils/showtools.py +4 -0
- {siliconcompiler-0.28.3.dist-info → siliconcompiler-0.28.5.dist-info}/METADATA +18 -5
- {siliconcompiler-0.28.3.dist-info → siliconcompiler-0.28.5.dist-info}/RECORD +86 -72
- {siliconcompiler-0.28.3.dist-info → siliconcompiler-0.28.5.dist-info}/WHEEL +1 -1
- {siliconcompiler-0.28.3.dist-info → siliconcompiler-0.28.5.dist-info}/LICENSE +0 -0
- {siliconcompiler-0.28.3.dist-info → siliconcompiler-0.28.5.dist-info}/entry_points.txt +0 -0
- {siliconcompiler-0.28.3.dist-info → siliconcompiler-0.28.5.dist-info}/top_level.txt +0 -0
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@@ -265,10 +265,24 @@ set openroad_mpl_macro_place_channel [dict get $openroad_task_vars macro_place_c
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set openroad_ppl_arguments [dict get $openroad_task_vars ppl_arguments]
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set openroad_rtlmp_enable [lindex [dict get $openroad_task_vars rtlmp_enable] 0]
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set openroad_rtlmp_max_levels [lindex [dict get $openroad_task_vars rtlmp_max_levels] 0]
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set openroad_rtlmp_min_instances [lindex [dict get $openroad_task_vars rtlmp_min_instances] 0]
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set openroad_rtlmp_max_instances [lindex [dict get $openroad_task_vars rtlmp_max_instances] 0]
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set openroad_rtlmp_min_macros [lindex [dict get $openroad_task_vars rtlmp_min_macros] 0]
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set openroad_rtlmp_max_macros [lindex [dict get $openroad_task_vars rtlmp_max_macros] 0]
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set openroad_rtlmp_min_aspect_ratio [lindex [dict get $openroad_task_vars rtlmp_min_aspect_ratio] 0]
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set openroad_rtlmp_fence [dict get $openroad_task_vars rtlmp_fence]
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set openroad_rtlmp_bus_planning [lindex [dict get $openroad_task_vars rtlmp_bus_planning] 0]
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set openroad_rtlmp_target_dead_space \
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[lindex [dict get $openroad_task_vars rtlmp_target_dead_space] 0]
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set openroad_rtlmp_area_weight [lindex [dict get $openroad_task_vars rtlmp_area_weight] 0]
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set openroad_rtlmp_outline_weight [lindex [dict get $openroad_task_vars rtlmp_outline_weight] 0]
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set openroad_rtlmp_wirelength_weight \
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[lindex [dict get $openroad_task_vars rtlmp_wirelength_weight] 0]
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set openroad_rtlmp_guidance_weight [lindex [dict get $openroad_task_vars rtlmp_guidance_weight] 0]
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set openroad_rtlmp_fence_weight [lindex [dict get $openroad_task_vars rtlmp_fence_weight] 0]
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set openroad_rtlmp_notch_weight [lindex [dict get $openroad_task_vars rtlmp_notch_weight] 0]
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set openroad_rtlmp_blockage_weight [lindex [dict get $openroad_task_vars rtlmp_blockage_weight] 0]
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set openroad_gpl_place_density [lindex [dict get $openroad_task_vars place_density] 0]
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set openroad_gpl_padding [lindex [dict get $openroad_task_vars pad_global_place] 0]
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@@ -427,6 +441,7 @@ if { $sc_task != "floorplan" } {
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# Setup reports directories
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file mkdir reports/timing
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file mkdir reports/power
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file mkdir reports/markers
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if { $sc_task == "show" || $sc_task == "screenshot" } {
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if { $sc_task == "screenshot" } {
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@@ -489,7 +504,7 @@ if { $sc_task == "show" || $sc_task == "screenshot" } {
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###############################
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utl::push_metrics_stage "sc__metric__{}"
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source "$sc_refdir/
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source "$sc_refdir/sc_report.tcl"
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utl::pop_metrics_stage
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# Images
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@@ -290,12 +290,12 @@ if { $do_automatic_pins } {
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# since we get an error otherwise.
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if { [sc_design_has_unplaced_macros] } {
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if { $openroad_rtlmp_enable == "true" } {
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-
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max([lindex $openroad_mpl_macro_place_halo 0],
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[lindex $openroad_mpl_macro_place_halo 1])
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}]
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lassign $openroad_mpl_macro_place_halo halo_x halo_y
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set rtlmp_args []
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if { $openroad_rtlmp_max_levels != "" } {
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lappend rtlmp_args -max_num_level $openroad_rtlmp_max_levels
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}
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if { $openroad_rtlmp_min_instances != "" } {
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lappend rtlmp_args -min_num_inst $openroad_rtlmp_min_instances
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}
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@@ -308,9 +308,48 @@ if { [sc_design_has_unplaced_macros] } {
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if { $openroad_rtlmp_max_macros != "" } {
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lappend rtlmp_args -max_num_macro $openroad_rtlmp_max_macros
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}
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if { $openroad_rtlmp_min_aspect_ratio != "" } {
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lappend rtlmp_args -min_ar $openroad_rtlmp_min_aspect_ratio
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}
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if { $openroad_rtlmp_fence != "" } {
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lappend rtlmp_args -fence_lx [lindex $openroad_rtlmp_fence 0]
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lappend rtlmp_args -fence_ly [lindex $openroad_rtlmp_fence 1]
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lappend rtlmp_args -fence_ux [lindex $openroad_rtlmp_fence 2]
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lappend rtlmp_args -fence_uy [lindex $openroad_rtlmp_fence 3]
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}
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if { $openroad_rtlmp_bus_planning == "true" } {
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lappend rtlmp_args -bus_planning
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}
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if { $openroad_rtlmp_target_dead_space != "" } {
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lappend rtlmp_args -target_dead_space $openroad_rtlmp_target_dead_space
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}
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if { $openroad_rtlmp_area_weight != "" } {
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lappend rtlmp_args -area_weight $openroad_rtlmp_area_weight
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}
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if { $openroad_rtlmp_outline_weight != "" } {
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lappend rtlmp_args -outline_weight $openroad_rtlmp_outline_weight
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}
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if { $openroad_rtlmp_wirelength_weight != "" } {
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lappend rtlmp_args -wirelength_weight $openroad_rtlmp_wirelength_weight
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}
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if { $openroad_rtlmp_guidance_weight != "" } {
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lappend rtlmp_args -guidance_weight $openroad_rtlmp_guidance_weight
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}
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if { $openroad_rtlmp_fence_weight != "" } {
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lappend rtlmp_args -fence_weight $openroad_rtlmp_fence_weight
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}
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if { $openroad_rtlmp_notch_weight != "" } {
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lappend rtlmp_args -notch_weight $openroad_rtlmp_notch_weight
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}
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if { $openroad_rtlmp_blockage_weight != "" } {
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lappend rtlmp_args -blockage_weight $openroad_rtlmp_blockage_weight
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}
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rtl_macro_placer -report_directory reports/rtlmp \
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-halo_width $
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-halo_width $halo_x \
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-halo_height $halo_y \
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-target_util [sc_global_placement_density] \
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{*}$rtlmp_args
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} else {
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###########################
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@@ -352,11 +391,18 @@ global_connect
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# Tap Cells
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###########################
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if {
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if {
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[sc_cfg_tool_task_exists {file} ifp_tapcell] &&
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[llength [sc_cfg_tool_task_get {file} ifp_tapcell]] > 0
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} {
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foreach tapcell_file [sc_cfg_tool_task_get {file} ifp_tapcell] {
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puts "Sourcing tapcell file: ${tapcell_file}"
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source $tapcell_file
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}
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global_connect
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} else {
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utl::warn FLW 1 "Tapcell configuration not provided"
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cut_rows
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}
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###########################
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@@ -1,160 +1 @@
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###############################
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# Report Metrics
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###############################
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proc sc_display_report { report } {
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if { ![file exists $report] } {
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return
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}
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set fid [open $report r]
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set report_content [read $fid]
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close $fid
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puts $report_content
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}
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set fields "{capacitance slew input_pins nets fanout}"
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set PREFIX "SC_METRIC:"
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if { [sc_cfg_tool_task_check_in_list setup var reports] } {
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puts "$PREFIX report_checks -path_delay max"
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report_checks -fields $fields -path_delay max -format full_clock_expanded \
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> reports/timing/setup.rpt
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sc_display_report reports/timing/setup.rpt
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report_checks -path_delay max -group_count $openroad_sta_top_n_paths \
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> reports/timing/setup.topN.rpt
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puts "$PREFIX setupslack"
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report_worst_slack -max > reports/timing/worst_slack.setup.rpt
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sc_display_report reports/timing/worst_slack.setup.rpt
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report_worst_slack_metric -setup
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puts "$PREFIX tns"
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report_tns > reports/timing/total_negative_slack.rpt
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sc_display_report reports/timing/total_negative_slack.rpt
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report_tns_metric -setup
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}
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if { [sc_cfg_tool_task_check_in_list hold var reports] } {
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puts "$PREFIX report_checks -path_delay min"
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report_checks -fields $fields -path_delay min -format full_clock_expanded \
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> reports/timing/hold.rpt
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sc_display_report reports/timing/hold.rpt
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report_checks -path_delay min -group_count $openroad_sta_top_n_paths \
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> reports/timing/hold.topN.rpt
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puts "$PREFIX holdslack"
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report_worst_slack -min > reports/timing/worst_slack.hold.rpt
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sc_display_report reports/timing/worst_slack.hold.rpt
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report_worst_slack_metric -hold
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report_tns_metric -hold
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}
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if { [sc_cfg_tool_task_check_in_list unconstrained var reports] } {
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puts "$PREFIX unconstrained"
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report_checks -fields $fields -unconstrained -format full_clock_expanded \
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> reports/timing/unconstrained.rpt
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sc_display_report reports/timing/unconstrained.rpt
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report_checks -unconstrained -group_count $openroad_sta_top_n_paths \
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> reports/timing/unconstrained.topN.rpt
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}
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if {
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[sc_cfg_tool_task_check_in_list clock_skew var reports] &&
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[llength [all_clocks]] > 0
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} {
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puts "$PREFIX clock_skew"
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report_clock_skew -setup -digits 4 > reports/timing/skew.setup.rpt
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sc_display_report reports/timing/skew.setup.rpt
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report_clock_skew_metric -setup
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report_clock_skew -hold -digits 4 > reports/timing/skew.hold.rpt
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sc_display_report reports/timing/skew.hold.rpt
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}
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if { [sc_cfg_tool_task_check_in_list drv_violations var reports] } {
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puts "$PREFIX DRV violators"
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report_check_types -max_slew -max_capacitance -max_fanout -violators \
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> reports/timing/drv_violators.rpt
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sc_display_report reports/timing/drv_violators.rpt
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80
|
-
report_erc_metrics
|
|
81
|
-
|
|
82
|
-
puts "$PREFIX floating nets"
|
|
83
|
-
report_floating_nets -verbose > reports/floating_nets.rpt
|
|
84
|
-
sc_display_report reports/floating_nets.rpt
|
|
85
|
-
}
|
|
86
|
-
|
|
87
|
-
utl::metric_int "timing__clocks" [llength [all_clocks]]
|
|
88
|
-
|
|
89
|
-
if { [sc_cfg_tool_task_check_in_list fmax var reports] } {
|
|
90
|
-
puts "$PREFIX fmax"
|
|
91
|
-
# Model on: https://github.com/The-OpenROAD-Project/OpenSTA/blob/f913c3ddbb3e7b4364ed4437c65ac78c4da9174b/tcl/Search.tcl#L1078
|
|
92
|
-
set fmax_metric 0
|
|
93
|
-
foreach clk [sta::sort_by_name [all_clocks]] {
|
|
94
|
-
set clk_name [get_name $clk]
|
|
95
|
-
set min_period [sta::find_clk_min_period $clk 1]
|
|
96
|
-
if { $min_period == 0.0 } {
|
|
97
|
-
continue
|
|
98
|
-
}
|
|
99
|
-
set fmax [expr { 1.0 / $min_period }]
|
|
100
|
-
utl::metric_float "timing__fmax__clock:${clk_name}" $fmax
|
|
101
|
-
puts "$clk_name fmax = [format %.2f [expr { $fmax / 1e6 }]] MHz"
|
|
102
|
-
set fmax_metric [expr { max($fmax_metric, $fmax) }]
|
|
103
|
-
}
|
|
104
|
-
if { $fmax_metric > 0 } {
|
|
105
|
-
utl::metric_float "timing__fmax" $fmax_metric
|
|
106
|
-
}
|
|
107
|
-
}
|
|
108
|
-
|
|
109
|
-
# get logic depth of design
|
|
110
|
-
utl::metric_int "design__logic__depth" [count_logic_depth]
|
|
111
|
-
|
|
112
|
-
if { [sc_cfg_tool_task_check_in_list power var reports] } {
|
|
113
|
-
puts "$PREFIX power"
|
|
114
|
-
foreach corner [sta::corners] {
|
|
115
|
-
set corner_name [$corner name]
|
|
116
|
-
puts "Power for corner: $corner_name"
|
|
117
|
-
report_power -corner $corner_name > reports/power/${corner_name}.rpt
|
|
118
|
-
sc_display_report reports/power/${corner_name}.rpt
|
|
119
|
-
}
|
|
120
|
-
report_power_metric -corner $sc_power_corner
|
|
121
|
-
}
|
|
122
|
-
|
|
123
|
-
puts "$PREFIX cellarea"
|
|
124
|
-
report_design_area
|
|
125
|
-
report_design_area_metrics
|
|
126
|
-
|
|
127
|
-
# get number of nets in design
|
|
128
|
-
utl::metric_int "design__nets" [llength [[ord::get_db_block] getNets]]
|
|
129
|
-
|
|
130
|
-
# get number of registers
|
|
131
|
-
utl::metric_int "design__registers" [llength [all_registers]]
|
|
132
|
-
|
|
133
|
-
# get number of buffers
|
|
134
|
-
set bufs 0
|
|
135
|
-
set invs 0
|
|
136
|
-
foreach inst [get_cells -hierarchical *] {
|
|
137
|
-
set cell [$inst cell]
|
|
138
|
-
if { $cell == "NULL" } {
|
|
139
|
-
continue
|
|
140
|
-
}
|
|
141
|
-
set liberty_cell [$cell liberty_cell]
|
|
142
|
-
if { $liberty_cell == "NULL" } {
|
|
143
|
-
continue
|
|
144
|
-
}
|
|
145
|
-
if { [$liberty_cell is_buffer] } {
|
|
146
|
-
incr bufs
|
|
147
|
-
} elseif { [$liberty_cell is_inverter] } {
|
|
148
|
-
incr invs
|
|
149
|
-
}
|
|
150
|
-
}
|
|
151
|
-
utl::metric_int "design__buffers" $bufs
|
|
152
|
-
utl::metric_int "design__inverters" $invs
|
|
153
|
-
|
|
154
|
-
# get number of unconstrained endpoints
|
|
155
|
-
with_output_to_variable endpoints {check_setup -unconstrained_endpoints}
|
|
156
|
-
set unconstrained_endpoints [regexp -all -inline {[0-9]+} $endpoints]
|
|
157
|
-
if { $unconstrained_endpoints == "" } {
|
|
158
|
-
set unconstrained_endpoints 0
|
|
159
|
-
}
|
|
160
|
-
utl::metric_int "timing__unconstrained" $unconstrained_endpoints
|
|
@@ -72,8 +72,10 @@ proc sc_global_placement { args } {
|
|
|
72
72
|
lappend openroad_gpl_args "-skip_io"
|
|
73
73
|
}
|
|
74
74
|
|
|
75
|
+
set density [sc_global_placement_density]
|
|
76
|
+
|
|
75
77
|
global_placement {*}$openroad_gpl_args \
|
|
76
|
-
-density
|
|
78
|
+
-density $density \
|
|
77
79
|
-pad_left $openroad_gpl_padding \
|
|
78
80
|
-pad_right $openroad_gpl_padding
|
|
79
81
|
}
|
|
@@ -0,0 +1,184 @@
|
|
|
1
|
+
###############################
|
|
2
|
+
# Reading SC Schema
|
|
3
|
+
###############################
|
|
4
|
+
|
|
5
|
+
source ./sc_manifest.tcl > /dev/null
|
|
6
|
+
|
|
7
|
+
##############################
|
|
8
|
+
# Schema Adapter
|
|
9
|
+
###############################
|
|
10
|
+
|
|
11
|
+
set sc_tool openroad
|
|
12
|
+
set sc_step [sc_cfg_get arg step]
|
|
13
|
+
set sc_index [sc_cfg_get arg index]
|
|
14
|
+
set sc_flow [sc_cfg_get option flow]
|
|
15
|
+
set sc_task [sc_cfg_get flowgraph $sc_flow $sc_step $sc_index task]
|
|
16
|
+
|
|
17
|
+
set sc_refdir [sc_cfg_tool_task_get refdir]
|
|
18
|
+
|
|
19
|
+
# Design
|
|
20
|
+
set sc_design [sc_top]
|
|
21
|
+
set sc_optmode [sc_cfg_get option optmode]
|
|
22
|
+
set sc_pdk [sc_cfg_get option pdk]
|
|
23
|
+
set sc_stackup [sc_cfg_get option stackup]
|
|
24
|
+
|
|
25
|
+
# PDK Design Rules
|
|
26
|
+
set sc_libtype [lindex [sc_cfg_get option var openroad_libtype] 0]
|
|
27
|
+
set sc_techlef [sc_cfg_get pdk $sc_pdk aprtech openroad $sc_stackup $sc_libtype lef]
|
|
28
|
+
|
|
29
|
+
set sc_threads [sc_cfg_tool_task_get threads]
|
|
30
|
+
|
|
31
|
+
###############################
|
|
32
|
+
# Optional
|
|
33
|
+
###############################
|
|
34
|
+
|
|
35
|
+
# MACROS
|
|
36
|
+
set sc_macrolibs [sc_get_asic_libraries macro]
|
|
37
|
+
|
|
38
|
+
###############################
|
|
39
|
+
# Suppress messages if requested
|
|
40
|
+
###############################
|
|
41
|
+
|
|
42
|
+
foreach msg [sc_cfg_tool_task_get warningoff] {
|
|
43
|
+
set or_msg [split $msg "-"]
|
|
44
|
+
if { [llength $or_msg] != 2 } {
|
|
45
|
+
utl::warn FLW 1 "$msg is not a valid message id"
|
|
46
|
+
} else {
|
|
47
|
+
set or_tool [lindex $or_msg 0]
|
|
48
|
+
set or_msg_id [expr { int([lindex $or_msg 1]) }]
|
|
49
|
+
utl::info FLW 1 "Suppressing $msg messages"
|
|
50
|
+
suppress_message $or_tool $or_msg_id
|
|
51
|
+
}
|
|
52
|
+
}
|
|
53
|
+
|
|
54
|
+
###############################
|
|
55
|
+
# Source helper functions
|
|
56
|
+
###############################
|
|
57
|
+
|
|
58
|
+
source "$sc_refdir/sc_procs.tcl"
|
|
59
|
+
|
|
60
|
+
###############################
|
|
61
|
+
# Common Setup
|
|
62
|
+
###############################
|
|
63
|
+
|
|
64
|
+
set_thread_count $sc_threads
|
|
65
|
+
|
|
66
|
+
# Read techlef
|
|
67
|
+
puts "Reading techlef: ${sc_techlef}"
|
|
68
|
+
read_lef $sc_techlef
|
|
69
|
+
|
|
70
|
+
# Read Lefs
|
|
71
|
+
foreach lib "$sc_macrolibs" {
|
|
72
|
+
foreach lef_file [sc_cfg_get library $lib output $sc_stackup lef] {
|
|
73
|
+
puts "Reading lef: ${lef_file}"
|
|
74
|
+
read_lef $lef_file
|
|
75
|
+
}
|
|
76
|
+
}
|
|
77
|
+
|
|
78
|
+
# Read Verilog
|
|
79
|
+
if { [file exists "inputs/${sc_design}.vg"] } {
|
|
80
|
+
puts "Reading netlist verilog: inputs/${sc_design}.vg"
|
|
81
|
+
read_verilog "inputs/${sc_design}.vg"
|
|
82
|
+
} else {
|
|
83
|
+
foreach netlist [sc_cfg_get input netlist verilog] {
|
|
84
|
+
puts "Reading netlist verilog: ${netlist}"
|
|
85
|
+
read_verilog $netlist
|
|
86
|
+
}
|
|
87
|
+
}
|
|
88
|
+
link_design $sc_design
|
|
89
|
+
|
|
90
|
+
###############################
|
|
91
|
+
# Source Step Script
|
|
92
|
+
###############################
|
|
93
|
+
|
|
94
|
+
utl::push_metrics_stage "sc__prestep__{}"
|
|
95
|
+
if { [sc_cfg_tool_task_exists prescript] } {
|
|
96
|
+
foreach sc_pre_script [sc_cfg_tool_task_get prescript] {
|
|
97
|
+
puts "Sourcing pre script: ${sc_pre_script}"
|
|
98
|
+
source -echo $sc_pre_script
|
|
99
|
+
}
|
|
100
|
+
}
|
|
101
|
+
utl::pop_metrics_stage
|
|
102
|
+
|
|
103
|
+
utl::push_metrics_stage "sc__step__{}"
|
|
104
|
+
|
|
105
|
+
###########################
|
|
106
|
+
# Initialize floorplan
|
|
107
|
+
###########################
|
|
108
|
+
|
|
109
|
+
if { [sc_cfg_exists input asic floorplan] } {
|
|
110
|
+
set def [lindex [sc_cfg_get input asic floorplan] 0]
|
|
111
|
+
puts "Reading floorplan DEF: ${def}"
|
|
112
|
+
read_def -floorplan_initialize $def
|
|
113
|
+
} else {
|
|
114
|
+
#NOTE: assuming a two tuple value as lower left, upper right
|
|
115
|
+
set sc_diearea [sc_cfg_get constraint outline]
|
|
116
|
+
|
|
117
|
+
# Use die and core sizes
|
|
118
|
+
set sc_diesize "[lindex $sc_diearea 0] [lindex $sc_diearea 1]"
|
|
119
|
+
|
|
120
|
+
set outline [odb::Rect]
|
|
121
|
+
$outline set_xlo [ord::microns_to_dbu [lindex $sc_diesize 0]]
|
|
122
|
+
$outline set_ylo [ord::microns_to_dbu [lindex $sc_diesize 1]]
|
|
123
|
+
$outline set_xhi [ord::microns_to_dbu [lindex $sc_diesize 2]]
|
|
124
|
+
$outline set_yhi [ord::microns_to_dbu [lindex $sc_diesize 3]]
|
|
125
|
+
|
|
126
|
+
[ord::get_db_block] setDieArea $outline
|
|
127
|
+
}
|
|
128
|
+
|
|
129
|
+
puts "Floorplan information:"
|
|
130
|
+
puts "Die area: [ord::get_die_area]"
|
|
131
|
+
|
|
132
|
+
###########################
|
|
133
|
+
# Track Creation
|
|
134
|
+
###########################
|
|
135
|
+
|
|
136
|
+
# source tracks from file if found, else else use schema entries
|
|
137
|
+
make_tracks
|
|
138
|
+
|
|
139
|
+
###########################
|
|
140
|
+
# RDL Routing
|
|
141
|
+
###########################
|
|
142
|
+
foreach rdl_file [sc_cfg_tool_task_get {file} rdlroute] {
|
|
143
|
+
puts "Sourcing rdlroute: ${rdl_file}"
|
|
144
|
+
source $rdl_file
|
|
145
|
+
}
|
|
146
|
+
|
|
147
|
+
######################
|
|
148
|
+
# Do fill
|
|
149
|
+
######################
|
|
150
|
+
|
|
151
|
+
set removed_obs 0
|
|
152
|
+
foreach obstruction [[ord::get_db_block] getObstructions] {
|
|
153
|
+
odb::dbObstruction_destroy $obstruction
|
|
154
|
+
incr removed_obs
|
|
155
|
+
}
|
|
156
|
+
utl::info FLW 1 "Deleted $removed_obs routing obstructions"
|
|
157
|
+
|
|
158
|
+
if {
|
|
159
|
+
[lindex [sc_cfg_tool_task_get var fin_add_fill] 0] == "true" &&
|
|
160
|
+
[sc_cfg_exists pdk $sc_pdk aprtech openroad $sc_stackup $sc_libtype fill]
|
|
161
|
+
} {
|
|
162
|
+
set sc_fillrules \
|
|
163
|
+
[lindex [sc_cfg_get pdk $sc_pdk aprtech openroad $sc_stackup $sc_libtype fill] 0]
|
|
164
|
+
density_fill -rules $sc_fillrules
|
|
165
|
+
}
|
|
166
|
+
|
|
167
|
+
utl::pop_metrics_stage
|
|
168
|
+
|
|
169
|
+
utl::push_metrics_stage "sc__poststep__{}"
|
|
170
|
+
if { [sc_cfg_tool_task_exists postscript] } {
|
|
171
|
+
foreach sc_post_script [sc_cfg_tool_task_get postscript] {
|
|
172
|
+
puts "Sourcing post script: ${sc_post_script}"
|
|
173
|
+
source -echo $sc_post_script
|
|
174
|
+
}
|
|
175
|
+
}
|
|
176
|
+
utl::pop_metrics_stage
|
|
177
|
+
|
|
178
|
+
###############################
|
|
179
|
+
# Write Design Data
|
|
180
|
+
###############################
|
|
181
|
+
|
|
182
|
+
utl::push_metrics_stage "sc__write__{}"
|
|
183
|
+
source "$sc_refdir/sc_write.tcl"
|
|
184
|
+
utl::pop_metrics_stage
|
|
@@ -0,0 +1,170 @@
|
|
|
1
|
+
###############################
|
|
2
|
+
# Report Metrics
|
|
3
|
+
###############################
|
|
4
|
+
|
|
5
|
+
proc sc_display_report { report } {
|
|
6
|
+
if { ![file exists $report] } {
|
|
7
|
+
return
|
|
8
|
+
}
|
|
9
|
+
set fid [open $report r]
|
|
10
|
+
set report_content [read $fid]
|
|
11
|
+
close $fid
|
|
12
|
+
puts $report_content
|
|
13
|
+
}
|
|
14
|
+
|
|
15
|
+
set fields "{capacitance slew input_pins nets fanout}"
|
|
16
|
+
set PREFIX "SC_METRIC:"
|
|
17
|
+
|
|
18
|
+
if { [sc_cfg_tool_task_check_in_list setup var reports] } {
|
|
19
|
+
puts "$PREFIX report_checks -path_delay max"
|
|
20
|
+
report_checks -fields $fields -path_delay max -format full_clock_expanded \
|
|
21
|
+
> reports/timing/setup.rpt
|
|
22
|
+
sc_display_report reports/timing/setup.rpt
|
|
23
|
+
report_checks -path_delay max -group_count $openroad_sta_top_n_paths \
|
|
24
|
+
> reports/timing/setup.topN.rpt
|
|
25
|
+
|
|
26
|
+
puts "$PREFIX setupslack"
|
|
27
|
+
report_worst_slack -max > reports/timing/worst_slack.setup.rpt
|
|
28
|
+
sc_display_report reports/timing/worst_slack.setup.rpt
|
|
29
|
+
report_worst_slack_metric -setup
|
|
30
|
+
|
|
31
|
+
puts "$PREFIX tns"
|
|
32
|
+
report_tns > reports/timing/total_negative_slack.rpt
|
|
33
|
+
sc_display_report reports/timing/total_negative_slack.rpt
|
|
34
|
+
report_tns_metric -setup
|
|
35
|
+
}
|
|
36
|
+
|
|
37
|
+
if { [sc_cfg_tool_task_check_in_list hold var reports] } {
|
|
38
|
+
puts "$PREFIX report_checks -path_delay min"
|
|
39
|
+
report_checks -fields $fields -path_delay min -format full_clock_expanded \
|
|
40
|
+
> reports/timing/hold.rpt
|
|
41
|
+
sc_display_report reports/timing/hold.rpt
|
|
42
|
+
report_checks -path_delay min -group_count $openroad_sta_top_n_paths \
|
|
43
|
+
> reports/timing/hold.topN.rpt
|
|
44
|
+
|
|
45
|
+
puts "$PREFIX holdslack"
|
|
46
|
+
report_worst_slack -min > reports/timing/worst_slack.hold.rpt
|
|
47
|
+
sc_display_report reports/timing/worst_slack.hold.rpt
|
|
48
|
+
report_worst_slack_metric -hold
|
|
49
|
+
|
|
50
|
+
report_tns_metric -hold
|
|
51
|
+
}
|
|
52
|
+
|
|
53
|
+
if { [sc_cfg_tool_task_check_in_list unconstrained var reports] } {
|
|
54
|
+
puts "$PREFIX unconstrained"
|
|
55
|
+
report_checks -fields $fields -unconstrained -format full_clock_expanded \
|
|
56
|
+
> reports/timing/unconstrained.rpt
|
|
57
|
+
sc_display_report reports/timing/unconstrained.rpt
|
|
58
|
+
report_checks -unconstrained -group_count $openroad_sta_top_n_paths \
|
|
59
|
+
> reports/timing/unconstrained.topN.rpt
|
|
60
|
+
}
|
|
61
|
+
|
|
62
|
+
if {
|
|
63
|
+
[sc_cfg_tool_task_check_in_list clock_skew var reports] &&
|
|
64
|
+
[llength [all_clocks]] > 0
|
|
65
|
+
} {
|
|
66
|
+
puts "$PREFIX clock_skew"
|
|
67
|
+
report_clock_skew -setup -digits 4 > reports/timing/skew.setup.rpt
|
|
68
|
+
sc_display_report reports/timing/skew.setup.rpt
|
|
69
|
+
report_clock_skew_metric -setup
|
|
70
|
+
report_clock_skew -hold -digits 4 > reports/timing/skew.hold.rpt
|
|
71
|
+
sc_display_report reports/timing/skew.hold.rpt
|
|
72
|
+
report_clock_skew_metric -hold
|
|
73
|
+
}
|
|
74
|
+
|
|
75
|
+
if { [sc_cfg_tool_task_check_in_list drv_violations var reports] } {
|
|
76
|
+
puts "$PREFIX DRV violators"
|
|
77
|
+
report_check_types -max_slew -max_capacitance -max_fanout -violators \
|
|
78
|
+
> reports/timing/drv_violators.rpt
|
|
79
|
+
sc_display_report reports/timing/drv_violators.rpt
|
|
80
|
+
report_erc_metrics
|
|
81
|
+
|
|
82
|
+
puts "$PREFIX floating nets"
|
|
83
|
+
report_floating_nets -verbose > reports/floating_nets.rpt
|
|
84
|
+
sc_display_report reports/floating_nets.rpt
|
|
85
|
+
}
|
|
86
|
+
|
|
87
|
+
utl::metric_int "timing__clocks" [llength [all_clocks]]
|
|
88
|
+
|
|
89
|
+
if { [sc_cfg_tool_task_check_in_list fmax var reports] } {
|
|
90
|
+
puts "$PREFIX fmax"
|
|
91
|
+
# Model on: https://github.com/The-OpenROAD-Project/OpenSTA/blob/f913c3ddbb3e7b4364ed4437c65ac78c4da9174b/tcl/Search.tcl#L1078
|
|
92
|
+
set fmax_metric 0
|
|
93
|
+
foreach clk [sta::sort_by_name [all_clocks]] {
|
|
94
|
+
set clk_name [get_name $clk]
|
|
95
|
+
set min_period [sta::find_clk_min_period $clk 1]
|
|
96
|
+
if { $min_period == 0.0 } {
|
|
97
|
+
continue
|
|
98
|
+
}
|
|
99
|
+
set fmax [expr { 1.0 / $min_period }]
|
|
100
|
+
utl::metric_float "timing__fmax__clock:${clk_name}" $fmax
|
|
101
|
+
puts "$clk_name fmax = [format %.2f [expr { $fmax / 1e6 }]] MHz"
|
|
102
|
+
set fmax_metric [expr { max($fmax_metric, $fmax) }]
|
|
103
|
+
}
|
|
104
|
+
if { $fmax_metric > 0 } {
|
|
105
|
+
utl::metric_float "timing__fmax" $fmax_metric
|
|
106
|
+
}
|
|
107
|
+
}
|
|
108
|
+
|
|
109
|
+
# get logic depth of design
|
|
110
|
+
utl::metric_int "design__logic__depth" [count_logic_depth]
|
|
111
|
+
|
|
112
|
+
if { [sc_cfg_tool_task_check_in_list power var reports] } {
|
|
113
|
+
puts "$PREFIX power"
|
|
114
|
+
foreach corner [sta::corners] {
|
|
115
|
+
set corner_name [$corner name]
|
|
116
|
+
puts "Power for corner: $corner_name"
|
|
117
|
+
report_power -corner $corner_name > reports/power/${corner_name}.rpt
|
|
118
|
+
sc_display_report reports/power/${corner_name}.rpt
|
|
119
|
+
}
|
|
120
|
+
report_power_metric -corner $sc_power_corner
|
|
121
|
+
}
|
|
122
|
+
|
|
123
|
+
puts "$PREFIX cellarea"
|
|
124
|
+
report_design_area
|
|
125
|
+
report_design_area_metrics
|
|
126
|
+
|
|
127
|
+
# get number of nets in design
|
|
128
|
+
utl::metric_int "design__nets" [llength [[ord::get_db_block] getNets]]
|
|
129
|
+
|
|
130
|
+
# get number of registers
|
|
131
|
+
utl::metric_int "design__registers" [llength [all_registers]]
|
|
132
|
+
|
|
133
|
+
# get number of buffers
|
|
134
|
+
set bufs 0
|
|
135
|
+
set invs 0
|
|
136
|
+
foreach inst [get_cells -hierarchical *] {
|
|
137
|
+
set cell [$inst cell]
|
|
138
|
+
if { $cell == "NULL" } {
|
|
139
|
+
continue
|
|
140
|
+
}
|
|
141
|
+
set liberty_cell [$cell liberty_cell]
|
|
142
|
+
if { $liberty_cell == "NULL" } {
|
|
143
|
+
continue
|
|
144
|
+
}
|
|
145
|
+
if { [$liberty_cell is_buffer] } {
|
|
146
|
+
incr bufs
|
|
147
|
+
} elseif { [$liberty_cell is_inverter] } {
|
|
148
|
+
incr invs
|
|
149
|
+
}
|
|
150
|
+
}
|
|
151
|
+
utl::metric_int "design__buffers" $bufs
|
|
152
|
+
utl::metric_int "design__inverters" $invs
|
|
153
|
+
|
|
154
|
+
# get number of unconstrained endpoints
|
|
155
|
+
with_output_to_variable endpoints {check_setup -unconstrained_endpoints}
|
|
156
|
+
set unconstrained_endpoints [regexp -all -inline {[0-9]+} $endpoints]
|
|
157
|
+
if { $unconstrained_endpoints == "" } {
|
|
158
|
+
set unconstrained_endpoints 0
|
|
159
|
+
}
|
|
160
|
+
utl::metric_int "timing__unconstrained" $unconstrained_endpoints
|
|
161
|
+
|
|
162
|
+
# Write markers
|
|
163
|
+
foreach markerdb [[ord::get_db_block] getMarkerCategories] {
|
|
164
|
+
if { [$markerdb getMarkerCount] == 0 } {
|
|
165
|
+
continue
|
|
166
|
+
}
|
|
167
|
+
|
|
168
|
+
$markerdb writeTR "reports/markers/${sc_design}.[$markerdb getName].rpt"
|
|
169
|
+
$markerdb writeJSON "reports/markers/${sc_design}.[$markerdb getName].json"
|
|
170
|
+
}
|
|
@@ -8,8 +8,14 @@
|
|
|
8
8
|
|
|
9
9
|
proc insert_fillers { } {
|
|
10
10
|
upvar sc_filler sc_filler
|
|
11
|
-
|
|
12
|
-
|
|
11
|
+
global sc_mainlib
|
|
12
|
+
|
|
13
|
+
set fillers $sc_filler
|
|
14
|
+
if { [lindex [sc_cfg_tool_task_get var dpl_use_decap_fillers] 0] == "true" } {
|
|
15
|
+
lappend fillers {*}[sc_cfg_get library $sc_mainlib asic cells decap]
|
|
16
|
+
}
|
|
17
|
+
if { $fillers != "" } {
|
|
18
|
+
filler_placement $fillers
|
|
13
19
|
}
|
|
14
20
|
|
|
15
21
|
check_placement -verbose
|
|
@@ -3,11 +3,6 @@ gui::save_display_controls
|
|
|
3
3
|
set sc_resolution \
|
|
4
4
|
[lindex [sc_cfg_tool_task_get {var} show_vertical_resolution] 0]
|
|
5
5
|
|
|
6
|
-
# Show the drc markers (if any)
|
|
7
|
-
if { [file exists reports/${sc_design}_drc.rpt] } {
|
|
8
|
-
gui::load_drc reports/${sc_design}_drc.rpt
|
|
9
|
-
}
|
|
10
|
-
|
|
11
6
|
sc_image_setup_default
|
|
12
7
|
|
|
13
8
|
sc_save_image "screenshot" "outputs/${sc_design}.png" $sc_resolution
|