siliconcompiler 0.28.3__py3-none-any.whl → 0.28.5__py3-none-any.whl

siliconcompiler/tools/klayout/klayout_convert_drc_db.py

@@ -0,0 +1,182 @@
+# KLayout script to export an OpenROAD marker DB from a DRC db
+#
+# Based on:
+# https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/blob/master/flow/util/convertDrc.py
+
+import pya
+import glob
+import json
+import os
+import sys
+
+
+def convert_drc(view, path):
+    rdb_id = view.create_rdb(os.path.basename(path))
+    rdb = view.rdb(rdb_id)
+    print(f"[INFO] reading {path}")
+    rdb.load(path)
+
+    source = os.path.abspath(path)
+
+    ordb = {
+        "source": source,
+        "description": "KLayout DRC conversion",
+        "category": {}
+    }
+
+    for category in rdb.each_category():
+        if category.num_items() == 0:
+            # ignore categories with no data
+            continue
+
+        ordb_category = {
+            "description": category.description,
+            "source": source,
+            "violations": []
+        }
+        ordb["category"][category.name()] = ordb_category
+
+        for item in rdb.each_item_per_category(category.rdb_id()):
+            violation = {
+                "visited": item.is_visited(),
+                "visible": True,
+                "waived": "waived" in item.tags_str
+            }
+
+            ordb_category["violations"].append(violation)
+
+            shapes = []
+            violation["shape"] = shapes
+
+            text = []
+
+            for value in item.each_value():
+                if value.is_box():
+                    shapes.append({
+                        "type": "box",
+                        "points": [{
+                            "x": value.box().left,
+                            "y": value.box().bottom
+                        }, {
+                            "x": value.box().right,
+                            "y": value.box().top
+                        }]
+                    })
+                elif value.is_edge():
+                    shapes.append({
+                        "type": "line",
+                        "points": [{
+                            "x": value.edge().p1.x,
+                            "y": value.edge().p1.y
+                        }, {
+                            "x": value.edge().p2.x,
+                            "y": value.edge().p2.y
+                        }]
+                    })
+                elif value.is_edge_pair():
+                    edge1 = value.edge_pair().first
+                    edge2 = value.edge_pair().second
+
+                    shapes.append({
+                        "type": "line",
+                        "points": [{
+                            "x": edge1.p1.x,
+                            "y": edge1.p1.y
+                        }, {
+                            "x": edge1.p2.x,
+                            "y": edge1.p2.y
+                        }]
+                    })
+                    shapes.append({
+                        "type": "line",
+                        "points": [{
+                            "x": edge2.p1.x,
+                            "y": edge2.p1.y
+                        }, {
+                            "x": edge2.p2.x,
+                            "y": edge2.p2.y
+                        }]
+                    })
+                elif value.is_polygon():
+                    points = []
+                    for edge in value.polygon().each_edge():
+                        points.append({
+                            "x": edge.p1.x,
+                            "y": edge.p1.y
+                        })
+                    points.append({
+                        "x": edge.p2.x,
+                        "y": edge.p2.y
+                    })
+                    shapes.append({
+                        "type": "polygon",
+                        "points": points
+                    })
+                elif value.is_path():
+                    points = []
+                    for edge in value.path().polygon().each_edge():
+                        points.append({
+                            "x": edge.p1.x,
+                            "y": edge.p1.y
+                        })
+                    points.append({
+                        "x": edge.p2.x,
+                        "y": edge.p2.y
+                    })
+                    shapes.append({
+                        "type": "polygon",
+                        "points": points
+                    })
+                elif value.is_text():
+                    text.append(value.text())
+                elif value.is_string():
+                    text.append(value.string())
+                else:
+                    print("[WARN] Unknown violation shape:", value)
+
+            comment = ""
+            if hasattr(item, 'comment'):
+                comment = item.comment
+            if text:
+                if comment:
+                    comment += ": "
+                comment += ", ".join(text)
+
+            if comment:
+                violation["comment"] = comment
+
+    return ordb
+
+
+def main():
+    # SC_ROOT provided by CLI
+    sys.path.append(SC_ROOT)  # noqa: F821
+
+    from tools.klayout.klayout_utils import get_schema
+
+    schema = get_schema(manifest='sc_manifest.json')
+
+    design = schema.get('design')
+
+    app = pya.Application.instance()
+    win = app.main_window()
+
+    # Create a dummy view to use for loading
+    cell_view = win.create_layout(0)
+    layout_view = cell_view.view()
+
+    ordb = {}
+    for file in glob.glob(f'inputs/{design}*.lyrdb') + glob.glob('inputs/{design}*.ascii'):
+        name = os.path.basename(file)
+
+        ordb[name] = convert_drc(layout_view, file)
+
+    with open(f"outputs/{design}.json", "w") as outfile:
+        json.dump(
+            ordb,
+            outfile,
+            indent=2)
+
+
+if __name__ == '__main__':
+    main()

siliconcompiler/tools/klayout/klayout_export.py

@@ -61,6 +61,9 @@ def gds_export(design_name, in_def, in_files, out_file, tech, allow_missing, con
     for cell in def_cells:
         print(f"  [INFO] DEF cell: {cell}")
 
+    if f"{design_name}_DEF_FILL" in def_cells:
+        def_cells.remove(f"{design_name}_DEF_FILL")
+
     # Load in the gds to merge
     print("[INFO] Merging GDS/OAS files...")
     for fil in in_files:

siliconcompiler/tools/klayout/klayout_utils.py

@@ -31,8 +31,14 @@ def technology(design, schema):
         sc_stackup = schema.get('option', 'stackup')
     else:
         sc_stackup = schema.get('pdk', sc_pdk, 'stackup')[0]
-    sc_mainlib = schema.get('asic', 'logiclib', step=sc_step, index=sc_index)[0]
-    sc_libtype = schema.get('library', sc_mainlib, 'asic', 'libarch', step=sc_step, index=sc_index)
+
+    logiclibs = schema.get('asic', 'logiclib', step=sc_step, index=sc_index)
+    if not logiclibs:
+        sc_libtype = schema.get('option', 'var', 'klayout_libtype')[0]
+    else:
+        sc_mainlib = logiclibs[0]
+        sc_libtype = schema.get('library', sc_mainlib, 'asic', 'libarch',
+                                step=sc_step, index=sc_index)
 
     sc_libs = []
     sc_libs += get_libraries(schema, 'logic')

siliconcompiler/tools/klayout/operations.py

@@ -109,6 +109,8 @@ def setup(chip):
     _, task = get_tool_task(chip, step, index)
     clobber = False
 
+    chip.set('tool', tool, 'task', task, 'threads', 1, step=step, index=index, clobber=clobber)
+
     script = 'klayout_operations.py'
     option = ['-z', '-nc', '-rx', '-r']
     chip.set('tool', tool, 'task', task, 'script', script, step=step, index=index, clobber=clobber)

siliconcompiler/tools/klayout/screenshot.py

@@ -24,6 +24,8 @@ def setup(chip):
     _, task = get_tool_task(chip, step, index)
     clobber = False
 
+    chip.set('tool', tool, 'task', task, 'threads', 1, step=step, index=index, clobber=clobber)
+
     setup_gui_screenshot(chip)
 
     option = ['-nc', '-z', '-rm']

siliconcompiler/tools/klayout/show.py

@@ -73,12 +73,12 @@ def setup(chip):
 
     step = chip.get('arg', 'step')
     index = chip.get('arg', 'index')
-    _, task = get_tool_task(chip, step, index)
+    tool, task = get_tool_task(chip, step, index)
+    clobber = False
 
-    general_gui_setup(chip, task, False)
+    chip.set('tool', tool, 'task', task, 'threads', 1, step=step, index=index, clobber=clobber)
 
-    tool = 'klayout'
-    clobber = False
+    general_gui_setup(chip, task, False)
 
     option = ['-nc', '-rm']
     chip.set('tool', tool, 'task', task, 'option', option, step=step, index=index, clobber=clobber)

siliconcompiler/tools/magic/drc.py

@@ -1,8 +1,10 @@
 import re
 
 from siliconcompiler.tools.magic.magic import setup as setup_tool
+from siliconcompiler.tools.magic.magic import process_file
 from siliconcompiler import sc_open
 from siliconcompiler.tools._common import get_tool_task, record_metric
+from siliconcompiler.tools._common.asic import get_mainlib, get_libraries
 
 
 def setup(chip):
@@ -22,6 +24,25 @@ def setup(chip):
     chip.set('tool', tool, 'task', task, 'output', f'{design}.drc.mag', step=step, index=index)
 
 
+def pre_process(chip):
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    tool, task = get_tool_task(chip, step, index)
+
+    pdk = chip.get('option', 'pdk')
+    stackup = chip.get('option', 'stackup')
+    mainlib = get_mainlib(chip)
+    libtype = chip.get('library', mainlib, 'asic', 'libarch', step=step, index=index)
+    process_file('lef', chip, 'pdk', pdk, 'aprtech', 'magic', stackup, libtype, 'lef')
+
+    for lib in get_libraries(chip, 'logic'):
+        process_file('lef', chip, 'library', lib, 'output', stackup, 'lef')
+
+    for lib in get_libraries(chip, 'macro'):
+        if lib in chip.get('tool', tool, 'task', task, 'var', 'exclude', step=step, index=index):
+            process_file('lef', chip, 'library', lib, 'output', stackup, 'lef')
+
+
 ################################
 # Post_process (post executable)
 ################################

siliconcompiler/tools/magic/extspice.py

@@ -1,5 +1,7 @@
 from siliconcompiler.tools.magic.magic import setup as setup_tool
+from siliconcompiler.tools.magic.magic import process_file
 from siliconcompiler.tools._common import get_tool_task
+from siliconcompiler.tools._common.asic import get_mainlib, get_libraries
 
 
 def setup(chip):
@@ -17,3 +19,22 @@ def setup(chip):
     design = chip.top()
 
     chip.add('tool', tool, 'task', task, 'output', f'{design}.spice', step=step, index=index)
+
+
+def pre_process(chip):
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    tool, task = get_tool_task(chip, step, index)
+
+    pdk = chip.get('option', 'pdk')
+    stackup = chip.get('option', 'stackup')
+    mainlib = get_mainlib(chip)
+    libtype = chip.get('library', mainlib, 'asic', 'libarch', step=step, index=index)
+    process_file('lef', chip, 'pdk', pdk, 'aprtech', 'magic', stackup, libtype, 'lef')
+
+    for lib in get_libraries(chip, 'logic'):
+        process_file('lef', chip, 'library', lib, 'output', stackup, 'lef')
+
+    for lib in get_libraries(chip, 'macro'):
+        if lib in chip.get('tool', tool, 'task', task, 'var', 'exclude', step=step, index=index):
+            process_file('lef', chip, 'library', lib, 'output', stackup, 'lef')

siliconcompiler/tools/magic/magic.py

@@ -9,9 +9,12 @@ Installation: https://github.com/RTimothyEdwards/magic
 Sources: https://github.com/RTimothyEdwards/magic
 '''
 
+import gzip
+import shutil
 import os
 from siliconcompiler.tools._common import input_provides, get_tool_task
 from siliconcompiler.targets import freepdk45_demo
+from siliconcompiler import utils
 
 
 ####################################################################
@@ -79,6 +82,32 @@ def parse_version(stdout):
     return stdout.strip('\n')
 
 
+def process_file(file_type, chip, *key):
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    tool, task = get_tool_task(chip, step, index)
+
+    if chip.get(*key, field='pernode') == 'never':
+        files = chip.find_files(*key)
+    else:
+        files = chip.find_files(*key, step=step, index=index)
+
+    for file in files:
+        if file.lower().endswith('.gz'):
+            new_file_name = f'inputs/sc_{utils.get_hashed_filename(file[:-3])}'
+
+            with gzip.open(file, 'rt', encoding="utf-8") as fin:
+                with open(new_file_name, 'w') as fout:
+                    fout.write(fin.read().encode("ascii", "ignore").decode("ascii"))
+        else:
+            new_file_name = f'inputs/sc_{utils.get_hashed_filename(file)}'
+            shutil.copy(file, new_file_name)
+
+        chip.add('tool', tool, 'task', task, 'file', f'read_{file_type}',
+                 os.path.join(chip.getworkdir(step=step, index=index), new_file_name),
+                 step=step, index=index)
+
+
 ##################################################
 if __name__ == "__main__":
 

siliconcompiler/tools/magic/sc_drc.tcl

@@ -23,18 +23,8 @@ set sc_design [sc_top]
 set sc_macrolibs [sc_get_asic_libraries macro]
 set sc_stackup [sc_cfg_get option stackup]
 
-if { [sc_cfg_tool_task_exists var exclude] } {
-    set sc_exclude [sc_cfg_tool_task_get var exclude]
-} else {
-    set sc_exclude [list]
-}
-
-# Ignore specific libraries by reading their LEFs (causes magic to abstract them)
-foreach lib $sc_macrolibs {
-    puts $lib
-    if { [lsearch -exact $sc_exclude $lib] >= 0 } {
-        lef read [sc_cfg_get library $lib output $sc_stackup lef]
-    }
+foreach sc_lef [sc_cfg_tool_task_get file read_lef] {
+    lef read $sc_lef
 }
 
 gds noduplicates true

siliconcompiler/tools/magic/sc_extspice.tcl

@@ -14,21 +14,9 @@ set sc_techlef [sc_cfg_get pdk $sc_pdk aprtech magic $sc_stackup $sc_libtype lef
 set sc_liblef [sc_cfg_get library $sc_mainlib output $sc_stackup lef]
 set sc_macrolibs [sc_get_asic_libraries macro]
 
-if { [sc_cfg_tool_task_exists var exclude] } {
-    set sc_exclude [sc_cfg_tool_task_get var exclude]
-} else {
-    set sc_exclude [list]
-}
-
-lef read $sc_techlef
-lef read $sc_liblef
-
-# Ignore specific libraries by reading their LEFs (causes magic to abstract them)
-foreach lib $sc_macrolibs {
-    puts $lib
-    if { [lsearch -exact $sc_exclude $lib] >= 0 } {
-        lef read [sc_cfg_get library $lib output $sc_stackup lef]
-    }
+foreach sc_lef [sc_cfg_tool_task_get file read_lef] {
+    puts "Reading LEF $sc_lef"
+    lef read $sc_lef
 }
 
 if { [file exists "inputs/$sc_design.gds"] } {

siliconcompiler/tools/openroad/metrics.py

@@ -0,0 +1,45 @@
+
+from siliconcompiler.tools.openroad.openroad import setup as setup_tool
+from siliconcompiler.tools.openroad.openroad import build_pex_corners
+from siliconcompiler.tools.openroad.openroad import post_process as or_post_process
+from siliconcompiler.tools.openroad.openroad import pre_process as or_pre_process
+from siliconcompiler.tools.openroad.openroad import _set_reports, set_pnr_inputs, set_pnr_outputs
+
+
+def setup(chip):
+    '''
+    Extract metrics
+    '''
+
+    # Generic tool setup.
+    setup_tool(chip)
+
+    set_pnr_inputs(chip)
+    set_pnr_outputs(chip)
+
+    _set_reports(chip, [
+        'setup',
+        'hold',
+        'unconstrained',
+        'clock_skew',
+        'power',
+        'drv_violations',
+        'fmax',
+
+        # Images
+        'placement_density',
+        'routing_congestion',
+        'power_density',
+        'clock_placement',
+        'clock_trees',
+        'optimization_placement'
+    ])
+
+
+def pre_process(chip):
+    or_pre_process(chip)
+    build_pex_corners(chip)
+
+
+def post_process(chip):
+    or_post_process(chip)

siliconcompiler/tools/openroad/openroad.py

@@ -38,7 +38,7 @@ def setup_tool(chip, exit=True, clobber=True):
 
     chip.set('tool', tool, 'exe', tool)
     chip.set('tool', tool, 'vswitch', '-version')
-    chip.set('tool', tool, 'version', '>=v2.0-13145', clobber=clobber)
+    chip.set('tool', tool, 'version', '>=v2.0-16580', clobber=clobber)
     chip.set('tool', tool, 'format', 'tcl', clobber=clobber)
 
     # exit automatically in batch mode and not breakpoint
@@ -274,7 +274,10 @@ def post_process(chip):
                  "floating_nets.rpt",
                  f"{chip.design}_antenna.rpt",
                  f"{chip.design}_antenna_post_repair.rpt"],
-        "drcs": [f"{chip.design}_drc.rpt"]
+        "drcs": [f"{chip.design}_drc.rpt",
+                 f"markers/{chip.design}.drc.rpt",
+                 f"markers/{chip.design}.drc.json",
+                 f"images/markers/{chip.design}.drc.png"]
     }
     metric_reports["leakagepower"] = metric_reports["peakpower"]
 
@@ -323,6 +326,9 @@ def post_process(chip):
             ('vias', 'sc__step__route__vias', True, None),
             ('wirelength', 'sc__step__route__wirelength', True, 'distance'),
             ('cellarea', 'sc__metric__design__instance__area', True, 'area'),
+            ('stdcellarea', 'sc__metric__design__instance__area__stdcell', True, 'area'),
+            ('macroarea', 'sc__metric__design__instance__area__macros', True, 'area'),
+            ('padcellarea', 'sc__metric__design__instance__area__padcells', True, 'area'),
             ('totalarea', 'sc__metric__design__core__area', True, 'area'),
             ('utilization', 'sc__metric__design__instance__utilization', True, 100.0),
             ('setuptns', 'sc__metric__timing__setup__tns', has_timing, 'time'),
@@ -673,6 +679,10 @@ def _define_dpl_params(chip):
                       default_value='false',
                       schelp='true/false, disallow single site gaps in detail placement')
 
+    set_tool_task_var(chip, param_key='dpl_use_decap_fillers',
+                      default_value='true',
+                      schelp='true/false, use decap fillers along with non-decap fillers')
+
 
 def _define_cts_params(chip):
     step = chip.get('arg', 'step')
@@ -852,6 +862,41 @@ def _define_mpl_params(chip):
                       schelp='minimum number of macros to use while clustering for macro placement')
     set_tool_task_var(chip, param_key='rtlmp_max_macros',
                       schelp='maximum number of macros to use while clustering for macro placement')
+    set_tool_task_var(chip, param_key='rtlmp_max_levels',
+                      schelp='maximum depth of physical hierarchical tree')
+    set_tool_task_var(chip, param_key='rtlmp_min_aspect_ratio',
+                      schelp='Specifies the minimum aspect ratio of its width to height of a '
+                             'standard cell cluster')
+    set_tool_task_var(chip, param_key='rtlmp_fence',
+                      schelp='Defines the global fence bounding box coordinates '
+                             '(llx, lly, urx, ury)')
+    set_tool_task_var(chip, param_key='rtlmp_bus_planning',
+                      schelp='Flag to enable bus planning')
+    set_tool_task_var(chip, param_key='rtlmp_target_dead_space',
+                      schelp='Specifies the target dead space percentage, which influences '
+                             'the utilization of standard cell clusters')
+
+    set_tool_task_var(chip, param_key='rtlmp_area_weight',
+                      schelp='Weight for the area of current floorplan')
+    set_tool_task_var(chip, param_key='rtlmp_outline_weight',
+                      schelp='Weight for violating the fixed outline constraint, meaning that all '
+                             'clusters should be placed within the shape of their parent cluster')
+    set_tool_task_var(chip, param_key='rtlmp_wirelength_weight',
+                      schelp='Weight for half-perimeter wirelength')
+    set_tool_task_var(chip, param_key='rtlmp_guidance_weight',
+                      schelp='Weight for guidance cost or clusters being placed near specified '
+                             'regions if users provide such constraints')
+    set_tool_task_var(chip, param_key='rtlmp_fence_weight',
+                      schelp='Weight for fence cost, or how far the macro is from zero '
+                             'fence violation')
+    set_tool_task_var(chip, param_key='rtlmp_blockage_weight',
+                      schelp='Weight for the boundary, or how far the hard macro clusters are '
+                             'from boundaries')
+    set_tool_task_var(chip, param_key='rtlmp_notch_weight',
+                      schelp='Weight for the notch, or the existence of dead space that cannot be '
+                             'used for placement & routing')
+    set_tool_task_var(chip, param_key='rtlmp_macro_blockage_weight',
+                      schelp='Weight for macro blockage, or the overlapping instances of the macro')
 
 
 def _define_ord_params(chip):

siliconcompiler/tools/openroad/rdlroute.py

@@ -0,0 +1,97 @@
+import os
+
+from siliconcompiler.tools._common import input_provides, get_tool_task
+from siliconcompiler.tools._common.asic import set_tool_task_var
+from siliconcompiler.tools.openroad.openroad import build_pex_corners
+from siliconcompiler.tools.openroad.openroad import post_process as or_post_process
+
+
+def setup(chip):
+    '''
+    Perform floorplanning, pin placements, macro placements and power grid generation
+    '''
+
+    # Generic tool setup.
+    # default tool settings, note, not additive!
+
+    tool = 'openroad'
+    script = 'sc_rdlroute.tcl'
+    refdir = os.path.join('tools', tool, 'scripts')
+
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    tool, task = get_tool_task(chip, step, index)
+
+    design = chip.top()
+
+    chip.set('tool', tool, 'exe', tool)
+    chip.set('tool', tool, 'vswitch', '-version')
+    chip.set('tool', tool, 'version', '>=v2.0-16839')
+    chip.set('tool', tool, 'format', 'tcl')
+
+    # exit automatically in batch mode and not breakpoint
+    option = ''
+    if exit and not chip.get('option', 'breakpoint', step=step, index=index):
+        option += " -exit"
+
+    option += " -metrics reports/metrics.json"
+    chip.set('tool', tool, 'task', task, 'option', option, step=step, index=index)
+
+    # Input/Output requirements for default asicflow steps
+
+    chip.set('tool', tool, 'task', task, 'refdir', refdir,
+             step=step, index=index,
+             package='siliconcompiler')
+    chip.set('tool', tool, 'task', task, 'script', script,
+             step=step, index=index)
+    chip.set('tool', tool, 'task', task, 'threads', os.cpu_count(),
+             step=step, index=index, clobber=False)
+
+    if chip.get('option', 'nodisplay'):
+        # Tells QT to use the offscreen platform if nodisplay is used
+        chip.set('tool', tool, 'task', task, 'env', 'QT_QPA_PLATFORM', 'offscreen',
+                 step=step, index=index)
+
+    # basic warning and error grep check on logfile
+    chip.set('tool', tool, 'task', task, 'regex', 'warnings', r'^\[WARNING|^Warning',
+             step=step, index=index, clobber=False)
+    chip.set('tool', tool, 'task', task, 'regex', 'errors', r'^\[ERROR',
+             step=step, index=index, clobber=False)
+
+    chip.add('tool', tool, 'task', task, 'require',
+             'option,var,openroad_libtype',
+             step=step, index=index)
+    chip.add('tool', tool, 'task', task, 'require',
+             ','.join(['tool', tool, 'task', task, 'file', 'rdlroute']),
+             step=step, index=index)
+    chip.set('tool', tool, 'task', task, 'file', 'rdlroute',
+             'script to perform rdl route',
+             field='help')
+
+    set_tool_task_var(chip, param_key='fin_add_fill',
+                      default_value='false',
+                      schelp='true/false, when true enables adding fill, '
+                             'if enabled by the PDK, to the design',
+                      skip='lib')
+
+    if f'{design}.v' in input_provides(chip, step, index):
+        chip.add('tool', tool, 'task', task, 'input', design + '.v', step=step, index=index)
+    elif f'{design}.vg' in input_provides(chip, step, index):
+        chip.add('tool', tool, 'task', task, 'input', design + '.vg', step=step, index=index)
+    else:
+        chip.add('tool', tool, 'task', task, 'require',
+                 ','.join(['input', 'netlist', 'verilog']),
+                 step=step, index=index)
+
+    chip.add('tool', tool, 'task', task, 'output', design + '.sdc', step=step, index=index)
+    chip.add('tool', tool, 'task', task, 'output', design + '.vg', step=step, index=index)
+    chip.add('tool', tool, 'task', task, 'output', design + '.def', step=step, index=index)
+    chip.add('tool', tool, 'task', task, 'output', design + '.odb', step=step, index=index)
+
+
+def pre_process(chip):
+    build_pex_corners(chip)
+
+
+def post_process(chip):
+    or_post_process(chip)