siliconcompiler 0.27.1__py3-none-any.whl → 0.28.1__py3-none-any.whl

siliconcompiler/tools/xyce/{xyce.py → __init__.py}

@@ -13,8 +13,6 @@ Installation: https://xyce.sandia.gov/documentation-tutorials/building-guide/
 
 Status: SC integration WIP
 '''
-
-import os
 from siliconcompiler.tools._common import get_tool_task
 
 
@@ -23,14 +21,20 @@ from siliconcompiler.tools._common import get_tool_task
 ################################
 def setup(chip):
 
-    tool = 'xyce'
     step = chip.get('arg', 'step')
     index = chip.get('arg', 'index')
-    _, task = get_tool_task(chip, step, index)
+    tool, task = get_tool_task(chip, step, index)
+
+    chip.set('tool', tool, 'exe', 'Xyce')
+    chip.set('tool', tool, 'vswitch', '-v')
+    chip.set('tool', tool, 'version', '>=v7.8')
+
+    chip.set('tool', tool, 'task', task, 'regex', 'warnings', 'warning',
+             step=step, index=index, clobber=False)
+    chip.set('tool', tool, 'task', task, 'regex', 'errors', 'error',
+             step=step, index=index, clobber=False)
 
-    clobber = False
 
-    chip.set('tool', tool, 'exe', tool)
-    chip.set('tool', tool, 'version', '0.0', clobber=clobber)
-    chip.set('tool', tool, 'task', task, 'threads', os.cpu_count(),
-             step=step, index=index, clobber=clobber)
+def parse_version(stdout):
+    ver = stdout.split()[-1]
+    return ver.split('-')[0]

siliconcompiler/tools/xyce/simulate.py

@@ -0,0 +1,70 @@
+from siliconcompiler.tools._common import input_provides, get_tool_task
+from siliconcompiler.tools.xyce import setup as tool_setup
+import os
+
+
+def setup(chip):
+    tool_setup(chip)
+
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    tool, task = get_tool_task(chip, step, index)
+
+    design = chip.top()
+
+    if f'{design}.xyce' in input_provides(chip, step, index):
+        chip.add('tool', tool, 'task', task, 'input', f'{design}.xyce',
+                 step=step, index=index)
+    elif f'{design}.cir' in input_provides(chip, step, index):
+        chip.add('tool', tool, 'task', task, 'input', f'{design}.cir',
+                 step=step, index=index)
+    else:
+        chip.add('tool', tool, 'task', task, 'require', 'input,netlist,spice',
+                 step=step, index=index)
+
+    chip.set('tool', tool, 'task', task, 'var', 'trace', 'false',
+             step=step, index=index, clobber=False)
+    chip.set('tool', tool, 'task', task, 'var', 'trace', 'true/false, enable dumping all signals',
+             field='help')
+
+    allowed_traced = ['ASCII', 'binary']
+    chip.set('tool', tool, 'task', task, 'var', 'trace_format', 'ASCII',
+             step=step, index=index, clobber=False)
+    chip.set('tool', tool, 'task', task, 'var', 'trace_format', 'Format to use for traces. '
+             f'Allowed values are {allowed_traced}',
+             field='help')
+
+    if chip.get('tool', tool, 'task', task, 'var', 'trace_format', step=step, index=index)[0] \
+            not in allowed_traced:
+        raise ValueError(f"{chip.get('tool', tool, 'task', task, 'var', 'trace_format')[0]} "
+                         "is not an accepted value")
+
+    if chip.get('tool', tool, 'task', task, 'var', 'trace_format', step=step, index=index) == \
+            ['ASCII']:
+        chip.add('tool', tool, 'task', task, 'option', '-a',
+                 step=step, index=index)
+
+    if chip.get('tool', tool, 'task', task, 'var', 'trace',
+                step=step, index=index) == ['true']:
+        chip.add('tool', tool, 'task', task, 'output', f'{design}.raw',
+                 step=step, index=index)
+        chip.add('tool', tool, 'task', task, 'option', f'-r outputs/{design}.raw',
+                 step=step, index=index)
+
+
+def runtime_options(chip):
+    design = chip.top()
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+
+    if f'{design}.xyce' in input_provides(chip, step, index):
+        if os.path.isfile(f'inputs/{design}.xyce'):
+            return [f'inputs/{design}.xyce']
+        elif os.path.isfile(f'inputs/{design}.xyce/{design}.cir'):
+            return [f'inputs/{design}.xyce/{design}.cir']
+        else:
+            return [f'inputs/{design}.xyce']
+    elif f'{design}.cir' in input_provides(chip, step, index):
+        return [f'inputs/{design}.cir']
+
+    return chip.find_files('input', 'netlist', 'spice', step=step, index=index)

siliconcompiler/tools/yosys/sc_lec.tcl

@@ -6,14 +6,14 @@ set sc_tool yosys
 yosys echo on
 
 #Handling remote/local script execution
-set sc_step   [sc_cfg_get arg step]
-set sc_index  [sc_cfg_get arg index]
-set sc_flow   [sc_cfg_get option flow]
-set sc_task   [sc_cfg_get flowgraph $sc_flow $sc_step $sc_index task]
-set sc_refdir [sc_cfg_tool_task_get refdir ]
+set sc_step [sc_cfg_get arg step]
+set sc_index [sc_cfg_get arg index]
+set sc_flow [sc_cfg_get option flow]
+set sc_task [sc_cfg_get flowgraph $sc_flow $sc_step $sc_index task]
+set sc_refdir [sc_cfg_tool_task_get refdir]
 
-set sc_design      [sc_top]
-set sc_targetlibs  [sc_get_asic_libraries logic]
+set sc_design [sc_top]
+set sc_targetlibs [sc_get_asic_libraries logic]
 
 # TODO: properly handle complexity here
 set lib [lindex $sc_targetlibs 0]

siliconcompiler/tools/yosys/sc_syn.tcl

@@ -10,21 +10,21 @@ yosys echo on
 # Schema Adapter
 ###############################
 
-set sc_tool   yosys
-set sc_step   [sc_cfg_get arg step]
-set sc_index  [sc_cfg_get arg index]
-set sc_flow   [sc_cfg_get option flow]
-set sc_task   [sc_cfg_get flowgraph $sc_flow $sc_step $sc_index task]
+set sc_tool yosys
+set sc_step [sc_cfg_get arg step]
+set sc_index [sc_cfg_get arg index]
+set sc_flow [sc_cfg_get option flow]
+set sc_task [sc_cfg_get flowgraph $sc_flow $sc_step $sc_index task]
 set sc_refdir [sc_cfg_tool_task_get refdir]
 
 ####################
 # DESIGNER's CHOICE
 ####################
 
-set sc_design      [sc_top]
-set sc_flow        [sc_cfg_get option flow]
-set sc_optmode     [sc_cfg_get option optmode]
-set sc_pdk         [sc_cfg_get option pdk]
+set sc_design [sc_top]
+set sc_flow [sc_cfg_get option flow]
+set sc_optmode [sc_cfg_get option optmode]
+set sc_pdk [sc_cfg_get option pdk]
 
 ########################################################
 # Design Inputs

siliconcompiler/tools/yosys/syn_asic.tcl

@@ -82,8 +82,8 @@ proc determine_keep_hierarchy { iter cell_limit } {
 # DESIGNER's CHOICE
 ####################
 
-set sc_logiclibs        [sc_get_asic_libraries logic]
-set sc_macrolibs        [sc_get_asic_libraries macro]
+set sc_logiclibs [sc_get_asic_libraries logic]
+set sc_macrolibs [sc_get_asic_libraries macro]
 
 set sc_libraries [sc_cfg_tool_task_get {file} synthesis_libraries]
 if { [sc_cfg_tool_task_exists {file} synthesis_libraries_macros] } {
@@ -127,8 +127,10 @@ proc has_tie_cell { type } {
     upvar sc_mainlib sc_mainlib
     upvar sc_tool sc_tool
 
-    return [expr { [sc_cfg_exists library $sc_mainlib option {var} yosys_tie${type}_cell] && \
-                   [sc_cfg_exists library $sc_mainlib option {var} yosys_tie${type}_port] }]
+    return [expr {
+        [sc_cfg_exists library $sc_mainlib option {var} yosys_tie${type}_cell] &&
+        [sc_cfg_exists library $sc_mainlib option {var} yosys_tie${type}_port]
+    }]
 }
 
 proc get_tie_cell { type } {
@@ -149,9 +151,11 @@ proc has_buffer_cell { } {
     upvar sc_mainlib sc_mainlib
     upvar sc_tool sc_tool
 
-    return [expr { [sc_cfg_exists library $sc_mainlib option {var} yosys_buffer_cell] && \
-                   [sc_cfg_exists library $sc_mainlib option {var} yosys_buffer_input] && \
-                   [sc_cfg_exists library $sc_mainlib option {var} yosys_buffer_output] }]
+    return [expr {
+        [sc_cfg_exists library $sc_mainlib option {var} yosys_buffer_cell] &&
+        [sc_cfg_exists library $sc_mainlib option {var} yosys_buffer_input] &&
+        [sc_cfg_exists library $sc_mainlib option {var} yosys_buffer_output]
+    }]
 }
 
 proc get_buffer_cell { } {
@@ -160,8 +164,8 @@ proc get_buffer_cell { } {
     upvar sc_tool sc_tool
 
     set cell [lindex [sc_cfg_get library $sc_mainlib option {var} yosys_buffer_cell] 0]
-    set in   [lindex [sc_cfg_get library $sc_mainlib option {var} yosys_buffer_input] 0]
-    set out  [lindex [sc_cfg_get library $sc_mainlib option {var} yosys_buffer_output] 0]
+    set in [lindex [sc_cfg_get library $sc_mainlib option {var} yosys_buffer_input] 0]
+    set out [lindex [sc_cfg_get library $sc_mainlib option {var} yosys_buffer_output] 0]
 
     return "$cell $in $out"
 }
@@ -207,8 +211,10 @@ yosys hierarchy -top $sc_design
 # Mark modules to keep from getting removed in flattening
 preserve_modules
 
-set flatten_design [expr { [lindex [sc_cfg_tool_task_get var flatten] 0] \
-    == "true" }]
+set flatten_design [expr {
+    [lindex [sc_cfg_tool_task_get var flatten] 0]
+    == "true"
+}]
 set synth_args []
 if { $flatten_design } {
     lappend synth_args "-flatten"
@@ -359,8 +365,10 @@ if { [llength $yosys_hilomap_args] != 0 } {
     yosys hilomap -singleton {*}$yosys_hilomap_args
 }
 
-if { [has_buffer_cell] && \
-     [sc_cfg_tool_task_get var add_buffers] == "true" } {
+if {
+    [has_buffer_cell] &&
+    [sc_cfg_tool_task_get var add_buffers] == "true"
+} {
     yosys insbuf -buf {*}[get_buffer_cell]
 }
 

siliconcompiler/tools/yosys/syn_fpga.tcl

@@ -1,27 +1,31 @@
-
 source "$sc_refdir/syn_asic_fpga_shared.tcl"
 
 proc legalize_flops { feature_set } {
-
     set legalize_flop_types []
 
-    if { [lsearch -exact $feature_set enable] >= 0 && \
-         [lsearch -exact $feature_set async_set] >= 0 && \
-         [lsearch -exact $feature_set async_reset] >= 0 } {
+    if {
+        [lsearch -exact $feature_set enable] >= 0 &&
+        [lsearch -exact $feature_set async_set] >= 0 &&
+        [lsearch -exact $feature_set async_reset] >= 0
+    } {
         lappend legalize_flop_types \$_DFF_P_
         lappend legalize_flop_types \$_DFF_PN?_
         lappend legalize_flop_types \$_DFFE_PP_
         lappend legalize_flop_types \$_DFFE_PN?P_
         lappend legalize_flop_types \$_DFFSR_PNN_
         lappend legalize_flop_types \$_DFFSRE_PNNP_
-    } elseif { [lsearch -exact $feature_set enable] >= 0 && \
-               [lsearch -exact $feature_set async_set] >= 0 } {
+    } elseif {
+        [lsearch -exact $feature_set enable] >= 0 &&
+        [lsearch -exact $feature_set async_set] >= 0
+    } {
         lappend legalize_flop_types \$_DFF_P_
         lappend legalize_flop_types \$_DFF_PN1_
         lappend legalize_flop_types \$_DFFE_PP_
         lappend legalize_flop_types \$_DFFE_PN1P_
-    } elseif { [lsearch -exact $feature_set enable] >= 0 && \
-               [lsearch -exact $feature_set async_reset] >= 0 } {
+    } elseif {
+        [lsearch -exact $feature_set enable] >= 0 &&
+        [lsearch -exact $feature_set async_reset] >= 0
+    } {
         lappend legalize_flop_types \$_DFF_P_
         lappend legalize_flop_types \$_DFF_PN0_
         lappend legalize_flop_types \$_DFFE_PP_
@@ -31,8 +35,10 @@ proc legalize_flops { feature_set } {
         lappend legalize_flop_types \$_DFF_P??_
         lappend legalize_flop_types \$_DFFE_PP_
         lappend legalize_flop_types \$_DFFE_P??P_
-    } elseif { [lsearch -exact $feature_set async_set] >= 0 && \
-               [lsearch -exact $feature_set async_reset] >= 0 } {
+    } elseif {
+        [lsearch -exact $feature_set async_set] >= 0 &&
+        [lsearch -exact $feature_set async_reset] >= 0
+    } {
         lappend legalize_flop_types \$_DFF_P_
         lappend legalize_flop_types \$_DFF_PN?_
         lappend legalize_flop_types \$_DFFSR_PNN_
@@ -59,8 +65,7 @@ proc legalize_flops { feature_set } {
 }
 
 proc get_dsp_options { sc_syn_dsp_options } {
-
-    set option_text [ list ]
+    set option_text [list]
     foreach dsp_option $sc_syn_dsp_options {
         lappend option_text -D $dsp_option
     }
@@ -80,7 +85,7 @@ if { [sc_cfg_exists fpga $sc_partname var feature_set] } {
     set sc_syn_feature_set \
         [sc_cfg_get fpga $sc_partname var feature_set]
 } else {
-    set sc_syn_feature_set [ list ]
+    set sc_syn_feature_set [list]
 }
 
 if { [sc_cfg_exists fpga $sc_partname var yosys_dsp_options] } {
@@ -89,7 +94,7 @@ if { [sc_cfg_exists fpga $sc_partname var yosys_dsp_options] } {
         [sc_cfg_get fpga $sc_partname var yosys_dsp_options]
     yosys log "Yosys DSP techmap options = $sc_syn_dsp_options"
 } else {
-    set sc_syn_dsp_options [ list ]
+    set sc_syn_dsp_options [list]
 }
 
 # TODO: add logic that remaps yosys built in name based on part number
@@ -101,13 +106,11 @@ yosys hierarchy -top $sc_design
 if { [string match {ice*} $sc_partname] } {
     yosys synth_ice40 -top $sc_design -json "${sc_design}.netlist.json"
 } else {
-
     # Pre-processing step:  if DSPs instance are hard-coded into
     # the user's design, we can use a blackbox flow for DSP mapping
     # as follows:
 
     if { [sc_cfg_exists fpga $sc_partname file yosys_macrolib] } {
-
         set sc_syn_macrolibs \
             [sc_cfg_get fpga $sc_partname file yosys_macrolib]
 

siliconcompiler/use.py

@@ -12,7 +12,8 @@ class PackageChip(Chip):
         super().__init__(name)
 
         if len(args) == 2:
-            self.logger.warning(f'passing Chip object to {type(self)} is deprecated')
+            self.logger.warning(
+                f'passing Chip object to {name} ({type(self).__name__}) is deprecated')
 
         path = None
         ref = None

{siliconcompiler-0.27.1.dist-info → siliconcompiler-0.28.1.dist-info}/METADATA

@@ -1,6 +1,6 @@
 Metadata-Version: 2.1
 Name: siliconcompiler
-Version: 0.27.1
+Version: 0.28.1
 Summary: A compiler framework that automates translation from source code to silicon.
 Author-email: Andreas Olofsson <andreas.d.olofsson@gmail.com>
 License: Apache License 2.0
@@ -23,7 +23,7 @@ Requires-Dist: packaging <24,>=21.3
 Requires-Dist: psutil >=5.8.0
 Requires-Dist: Pillow ==10.4.0
 Requires-Dist: GitPython ==3.1.43
-Requires-Dist: lambdapdk >=0.1.25
+Requires-Dist: lambdapdk >=0.1.34
 Requires-Dist: PyGithub ==2.4.0
 Requires-Dist: urllib3 >=1.26.0
 Requires-Dist: fasteners ==0.19
@@ -31,7 +31,7 @@ Requires-Dist: fastjsonschema ==2.20.0
 Requires-Dist: docker ==7.1.0
 Requires-Dist: sc-surelog ==1.84.1
 Requires-Dist: orjson ==3.10.7
-Requires-Dist: streamlit ==1.37.1
+Requires-Dist: streamlit ==1.38.0
 Requires-Dist: streamlit-agraph ==0.0.45
 Requires-Dist: streamlit-tree-select ==0.0.5
 Requires-Dist: streamlit-javascript ==0.1.5
@@ -43,21 +43,22 @@ Requires-Dist: pydata-sphinx-theme ==0.15.4 ; extra == 'docs'
 Requires-Dist: sc-leflib >=0.2.0 ; extra == 'docs'
 Provides-Extra: examples
 Requires-Dist: migen ==0.9.2 ; extra == 'examples'
-Requires-Dist: lambdalib ==0.2.9 ; extra == 'examples'
+Requires-Dist: lambdalib ==0.2.10 ; extra == 'examples'
 Provides-Extra: profile
 Requires-Dist: gprof2dot ==2024.6.6 ; extra == 'profile'
 Provides-Extra: test
-Requires-Dist: pytest ==8.3.2 ; extra == 'test'
+Requires-Dist: pytest ==8.3.3 ; extra == 'test'
 Requires-Dist: pytest-xdist ==3.6.1 ; extra == 'test'
 Requires-Dist: pytest-timeout ==2.3.1 ; extra == 'test'
 Requires-Dist: pytest-asyncio ==0.24.0 ; extra == 'test'
 Requires-Dist: pytest-cov ==5.0.0 ; extra == 'test'
+Requires-Dist: responses ==0.25.3 ; extra == 'test'
 Requires-Dist: PyVirtualDisplay ==3.0 ; extra == 'test'
 Requires-Dist: flake8 ==7.1.1 ; extra == 'test'
-Requires-Dist: tclint ==0.3.2 ; extra == 'test'
+Requires-Dist: tclint ==0.4.0 ; extra == 'test'
 Requires-Dist: codespell ==2.3.0 ; extra == 'test'
 
-![SiliconCompiler](https://raw.githubusercontent.com/siliconcompiler/siliconcompiler/main/docs/_images/sc_logo_with_text.png)
+![SiliconCompiler](https://raw.githubusercontent.com/siliconcompiler/siliconcompiler/main/docs/_static/sc_logo_with_text.png)
 
 [![Python CI Tests](https://github.com/siliconcompiler/siliconcompiler/actions/workflows/python_ci.yml/badge.svg?branch=main)](https://github.com/siliconcompiler/siliconcompiler/actions/workflows/python_ci.yml)
 [![Tools CI Tests](https://github.com/siliconcompiler/siliconcompiler/actions/workflows/tools_ci.yml/badge.svg?branch=main)](https://github.com/siliconcompiler/siliconcompiler/actions/workflows/tools_ci.yml)
@@ -83,7 +84,7 @@ SiliconCompiler is a modular hardware build system ("make for silicon"). The pro
 |**FPGA APR**| VPR, nextpnr, Vivado
 |**Layout Viewer**| Klayout, OpenRoad, Cadence, Synopsys
 |**DRC/LVS**| Magic, Synopsys, Siemens
-|**PDKs**| sky130, gf180, asap7, freepdk45, gf12lp, gf22fdx, intel16
+|**PDKs**| sky130, gf180, asap7, freepdk45, gf12lp, gf22fdx, intel16, ihp130
 
 # Getting Started