siliconcompiler 0.27.1__py3-none-any.whl → 0.28.1__py3-none-any.whl
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- siliconcompiler/_metadata.py +1 -1
- siliconcompiler/core.py +4 -1
- siliconcompiler/data/RobotoMono/__init__.py +0 -0
- siliconcompiler/data/__init__.py +0 -0
- siliconcompiler/flows/dvflow.py +51 -14
- siliconcompiler/flows/generate_openroad_rcx.py +1 -1
- siliconcompiler/libs/sg13g2_stdcell.py +8 -0
- siliconcompiler/pdks/ihp130.py +8 -0
- siliconcompiler/remote/server_schema/__init__.py +0 -0
- siliconcompiler/remote/server_schema/requests/__init__.py +0 -0
- siliconcompiler/remote/server_schema/responses/__init__.py +0 -0
- siliconcompiler/scheduler/__init__.py +6 -4
- siliconcompiler/scheduler/validation/__init__.py +0 -0
- siliconcompiler/schema/schema_cfg.py +351 -281
- siliconcompiler/schema/schema_obj.py +5 -3
- siliconcompiler/sphinx_ext/dynamicgen.py +35 -15
- siliconcompiler/sphinx_ext/schemagen.py +4 -1
- siliconcompiler/targets/ihp130_demo.py +68 -0
- siliconcompiler/templates/__init__.py +0 -0
- siliconcompiler/templates/email/__init__.py +0 -0
- siliconcompiler/templates/issue/__init__.py +0 -0
- siliconcompiler/templates/report/__init__.py +0 -0
- siliconcompiler/templates/slurm/__init__.py +0 -0
- siliconcompiler/templates/tcl/__init__.py +0 -0
- siliconcompiler/tools/_common/sdc/__init__.py +0 -0
- siliconcompiler/tools/_common/tcl/__init__.py +0 -0
- siliconcompiler/tools/_common/tcl/sc_pin_constraints.tcl +1 -2
- siliconcompiler/tools/bambu/__init__.py +0 -0
- siliconcompiler/tools/bluespec/__init__.py +0 -0
- siliconcompiler/tools/builtin/__init__.py +0 -0
- siliconcompiler/tools/builtin/concatenate.py +16 -0
- siliconcompiler/tools/chisel/__init__.py +0 -0
- siliconcompiler/tools/execute/__init__.py +0 -0
- siliconcompiler/tools/genfasm/__init__.py +0 -0
- siliconcompiler/tools/ghdl/__init__.py +0 -0
- siliconcompiler/tools/icarus/__init__.py +0 -0
- siliconcompiler/tools/icepack/__init__.py +0 -0
- siliconcompiler/tools/klayout/__init__.py +0 -0
- siliconcompiler/tools/klayout/klayout.py +1 -0
- siliconcompiler/tools/magic/__init__.py +0 -0
- siliconcompiler/tools/magic/sc_drc.tcl +5 -5
- siliconcompiler/tools/magic/sc_extspice.tcl +3 -3
- siliconcompiler/tools/magic/sc_magic.tcl +2 -2
- siliconcompiler/tools/montage/__init__.py +0 -0
- siliconcompiler/tools/netgen/__init__.py +0 -0
- siliconcompiler/tools/netgen/sc_lvs.tcl +3 -3
- siliconcompiler/tools/nextpnr/__init__.py +0 -0
- siliconcompiler/tools/openroad/scripts/__init__.py +0 -0
- siliconcompiler/tools/openroad/scripts/sc_apr.tcl +36 -34
- siliconcompiler/tools/openroad/scripts/sc_cts.tcl +0 -1
- siliconcompiler/tools/openroad/scripts/sc_dfm.tcl +4 -2
- siliconcompiler/tools/openroad/scripts/sc_export.tcl +4 -2
- siliconcompiler/tools/openroad/scripts/sc_floorplan.tcl +27 -35
- siliconcompiler/tools/openroad/scripts/sc_metrics.tcl +4 -2
- siliconcompiler/tools/openroad/scripts/sc_physyn.tcl +0 -1
- siliconcompiler/tools/openroad/scripts/sc_procs.tcl +38 -6
- siliconcompiler/tools/openroad/scripts/sc_rcx.tcl +9 -9
- siliconcompiler/tools/openroad/scripts/sc_route.tcl +8 -4
- siliconcompiler/tools/openroad/scripts/sc_screenshot.tcl +5 -3
- siliconcompiler/tools/openroad/scripts/sc_write_images.tcl +27 -25
- siliconcompiler/tools/openroad/templates/__init__.py +0 -0
- siliconcompiler/tools/opensta/scripts/__init__.py +0 -0
- siliconcompiler/tools/opensta/scripts/sc_procs.tcl +0 -1
- siliconcompiler/tools/surelog/templates/__init__.py +0 -0
- siliconcompiler/tools/sv2v/__init__.py +0 -0
- siliconcompiler/tools/template/__init__.py +0 -0
- siliconcompiler/tools/verilator/__init__.py +0 -0
- siliconcompiler/tools/verilator/compile.py +1 -4
- siliconcompiler/tools/verilator/verilator.py +1 -2
- siliconcompiler/tools/vivado/scripts/__init__.py +0 -0
- siliconcompiler/tools/vivado/scripts/sc_run.tcl +7 -8
- siliconcompiler/tools/vivado/vivado.py +1 -1
- siliconcompiler/tools/vpr/__init__.py +0 -0
- siliconcompiler/tools/vpr/place.py +20 -6
- siliconcompiler/tools/vpr/vpr.py +1 -1
- siliconcompiler/tools/xdm/__init__.py +28 -0
- siliconcompiler/tools/xdm/convert.py +71 -0
- siliconcompiler/tools/xyce/{xyce.py → __init__.py} +13 -9
- siliconcompiler/tools/xyce/simulate.py +70 -0
- siliconcompiler/tools/yosys/__init__.py +0 -0
- siliconcompiler/tools/yosys/sc_lec.tcl +7 -7
- siliconcompiler/tools/yosys/sc_syn.tcl +9 -9
- siliconcompiler/tools/yosys/syn_asic.tcl +21 -13
- siliconcompiler/tools/yosys/syn_fpga.tcl +20 -17
- siliconcompiler/tools/yosys/techmaps/__init__.py +0 -0
- siliconcompiler/tools/yosys/templates/__init__.py +0 -0
- siliconcompiler/use.py +2 -1
- {siliconcompiler-0.27.1.dist-info → siliconcompiler-0.28.1.dist-info}/METADATA +9 -8
- {siliconcompiler-0.27.1.dist-info → siliconcompiler-0.28.1.dist-info}/RECORD +93 -48
- {siliconcompiler-0.27.1.dist-info → siliconcompiler-0.28.1.dist-info}/WHEEL +1 -1
- siliconcompiler/tools/openfpgaloader/openfpgaloader.py +0 -39
- {siliconcompiler-0.27.1.dist-info → siliconcompiler-0.28.1.dist-info}/LICENSE +0 -0
- {siliconcompiler-0.27.1.dist-info → siliconcompiler-0.28.1.dist-info}/entry_points.txt +0 -0
- {siliconcompiler-0.27.1.dist-info → siliconcompiler-0.28.1.dist-info}/top_level.txt +0 -0
siliconcompiler/_metadata.py
CHANGED
siliconcompiler/core.py
CHANGED
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@@ -529,6 +529,9 @@ class Chip:
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self.logger.warning(".load_target is deprecated, use .use() instead.")
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if isinstance(module, str):
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raise ValueError(f"module cannot be a string: {module}")
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self.use(module, **kwargs)
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##########################################################################
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else:
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result.append(None)
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if not missing_ok:
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self.error(f'Could not find {path} in {dependency}.')
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self.error(f'Could not find {path} in {dependency}. ({keypath})')
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continue
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result.append(utils.find_sc_file(self,
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path,
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siliconcompiler/flows/dvflow.py
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@@ -3,6 +3,8 @@ import siliconcompiler
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from siliconcompiler.tools.icarus import compile as icarus_compile
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from siliconcompiler.tools.verilator import compile as verilator_compile
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from siliconcompiler.tools.execute import exec_input
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from siliconcompiler.tools.xyce import simulate as xyce_simulate
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from siliconcompiler.tools.xdm import convert as xdm_convert
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############################################################################
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Setting 'np' > 1 results in multiple independent verification
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pipelines to be launched.
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Supported tools are:
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* icarus
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* verilator
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* xyce
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* xdm-xyce
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This flow is a WIP
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'''
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flow = siliconcompiler.Flow(flowname)
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tasks = {
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'sim': None
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}
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tasks = {}
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flow_np = {}
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if tool == 'icarus':
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tasks['compile'] = icarus_compile
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tasks['sim'] = exec_input
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flowpipe = [
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]
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flow_np = {
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'compile': 1,
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'sim': np
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}
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elif tool == 'verilator':
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tasks['compile'] = verilator_compile
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flowpipe = [
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tasks['sim'] = xyce_simulate
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}
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elif tool == 'xdm-xyce':
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tasks['compile'] = xdm_convert
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tasks['sim'] = xyce_simulate
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'sim': np
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}
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raise ValueError(f'{tool} is not a supported tool for {flowname}')
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prevstep = None
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# Flow setup
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flow.node(flowname, 'bench', rcx_bench)
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local_processes.append((step, index))
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processes[node] =
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processes[node] = multiprocessing.Process(target=_runtask,
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args=(chip, flow, step, index, exec_func))
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init_func(chip)
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