siliconcompiler 0.27.1__py3-none-any.whl → 0.28.1__py3-none-any.whl

siliconcompiler/tools/openroad/scripts/sc_floorplan.tcl

@@ -23,12 +23,14 @@ if { [sc_cfg_exists input asic floorplan] } {
   read_def -floorplan_initialize $def
 } else {
   #NOTE: assuming a two tuple value as lower left, upper right
-  set sc_diearea   [sc_cfg_get constraint outline]
-  set sc_corearea  [sc_cfg_get constraint corearea]
-  if { $sc_diearea != "" && \
-       $sc_corearea != "" } {
+  set sc_diearea [sc_cfg_get constraint outline]
+  set sc_corearea [sc_cfg_get constraint corearea]
+  if {
+    $sc_diearea != "" &&
+    $sc_corearea != ""
+  } {
     # Use die and core sizes
-    set sc_diesize  "[lindex $sc_diearea 0] [lindex $sc_diearea 1]"
+    set sc_diesize "[lindex $sc_diearea 0] [lindex $sc_diearea 1]"
     set sc_coresize "[lindex $sc_corearea 0] [lindex $sc_corearea 1]"
 
     initialize_floorplan -die_area $sc_diesize \
@@ -61,8 +63,10 @@ if { [sc_cfg_exists library $sc_mainlib option file openroad_tracks] } {
 }
 
 set do_automatic_pins 1
-if { [sc_cfg_tool_task_exists file padring] && \
-     [llength [sc_cfg_tool_task_get file padring]] > 0 } {
+if {
+  [sc_cfg_tool_task_exists file padring] &&
+  [llength [sc_cfg_tool_task_get file padring]] > 0
+} {
   set do_automatic_pins 0
 
   ###########################
@@ -208,7 +212,7 @@ if { [sc_cfg_exists constraint component] } {
       }
 
       set site_height [$site getHeight]
-      set site_width  [$site getWidth]
+      set site_width [$site getWidth]
       if { $y_grid == 0 } {
         set y_grid $site_height
       } elseif { $y_grid > $site_height } {
@@ -236,12 +240,8 @@ if { [sc_cfg_exists constraint component] } {
 
   dict for {name params} [sc_cfg_get constraint component] {
     set location [dict get $params placement]
-    set rotation [dict get $params rotation]
-    if { [llength $rotation] == 0 } {
-      set rotation 0
-    }
-    set rotation [expr { int($rotation) }]
-    set flip     [dict get $params flip]
+    set rotation [sc_convert_rotation [dict get $params rotation]]
+
     if { [dict exists $params partname] } {
       set cell [dict get $params partname]
     } else {
@@ -251,14 +251,7 @@ if { [sc_cfg_exists constraint component] } {
       utl::warn FLW 1 "Halo is not supported in OpenROAD"
     }
 
-    set transform_r [odb::dbTransform]
-    $transform_r setOrient "R${rotation}"
-    set transform_f [odb::dbTransform]
-    if { $flip == "true" } {
-      $transform_f setOrient [odb::dbTransform "MY"]
-    }
-    set transform_final [odb::dbTransform]
-    odb::dbTransform_concat $transform_r $transform_f $transform_final
+    set transform [odb::dbTransform $rotation]
 
     set inst [[ord::get_db_block] findInst $name]
     if { $inst == "NULL" } {
@@ -275,16 +268,11 @@ if { [sc_cfg_exists constraint component] } {
       }
     }
     set master [$inst getMaster]
-    set height [ord::dbu_to_microns [$master getHeight]]
-    set width [ord::dbu_to_microns [$master getWidth]]
-
-    set x_loc [expr { [lindex $location 0] - $width / 2 }]
-    set y_loc [expr { [lindex $location 1] - $height / 2 }]
 
-    set x_loc [expr { round($x_loc / $x_grid) * $x_grid }]
-    set y_loc [expr { round($y_loc / $y_grid) * $y_grid }]
+    set x_loc [expr { round([lindex $location 0] / $x_grid) * $x_grid }]
+    set y_loc [expr { round([lindex $location 1] / $y_grid) * $y_grid }]
 
-    $inst setOrient [$transform_final getOrient]
+    $inst setOrient [$rotation getOrient]
     $inst setLocation [ord::microns_to_dbu $x_loc] [ord::microns_to_dbu $y_loc]
     $inst setPlacementStatus FIRM
   }
@@ -302,8 +290,10 @@ if { $do_automatic_pins } {
 # since we get an error otherwise.
 if { [sc_design_has_unplaced_macros] } {
   if { $openroad_rtlmp_enable == "true" } {
-    set halo_max [expr { max([lindex $openroad_mpl_macro_place_halo 0], \
-                             [lindex $openroad_mpl_macro_place_halo 1]) }]
+    set halo_max [expr {
+      max([lindex $openroad_mpl_macro_place_halo 0],
+        [lindex $openroad_mpl_macro_place_halo 1])
+    }]
 
     set rtlmp_args []
     if { $openroad_rtlmp_min_instances != "" } {
@@ -370,9 +360,11 @@ if { [sc_cfg_tool_task_exists {file} ifp_tapcell] } {
 # Power Network
 ###########################
 
-if { $openroad_pdn_enable == "true" && \
-     [sc_cfg_tool_task_exists {file} pdn_config] && \
-     [llength [sc_cfg_tool_task_get {file} pdn_config]] > 0 } {
+if {
+  $openroad_pdn_enable == "true" &&
+  [sc_cfg_tool_task_exists {file} pdn_config] &&
+  [llength [sc_cfg_tool_task_get {file} pdn_config]] > 0
+} {
   set pdn_files []
   foreach pdnconfig [sc_cfg_tool_task_get {file} pdn_config] {
     if { [lsearch -exact $pdn_files $pdnconfig] != -1 } {

siliconcompiler/tools/openroad/scripts/sc_metrics.tcl

@@ -59,8 +59,10 @@ if { [sc_cfg_tool_task_check_in_list unconstrained var reports] } {
     > reports/timing/unconstrained.topN.rpt
 }
 
-if { [sc_cfg_tool_task_check_in_list clock_skew var reports] && \
-     [llength [all_clocks]] > 0 } {
+if {
+  [sc_cfg_tool_task_check_in_list clock_skew var reports] &&
+  [llength [all_clocks]] > 0
+} {
   puts "$PREFIX clock_skew"
   report_clock_skew -setup -digits 4 > reports/timing/skew.setup.rpt
   sc_display_report reports/timing/skew.setup.rpt

siliconcompiler/tools/openroad/scripts/sc_physyn.tcl

@@ -1,4 +1,3 @@
-
 # while (not good enough):
 #   global placement
 #   estimate parasitics

siliconcompiler/tools/openroad/scripts/sc_procs.tcl

@@ -19,8 +19,10 @@ proc sc_global_placement_density {} {
   # User specified adjustment
   if { $openroad_gpl_uniform_placement_adjustment > 0.0 } {
     set or_uniform_adjusted_density \
-      [expr { $or_uniform_density + ((1.0 - $or_uniform_density) * \
-              $openroad_gpl_uniform_placement_adjustment) + $or_adjust_density_adder }]
+      [expr {
+        $or_uniform_density + ((1.0 - $or_uniform_density) *
+          $openroad_gpl_uniform_placement_adjustment) + $or_adjust_density_adder
+      }]
     if { $or_uniform_adjusted_density > 1.00 } {
       utl::warn FLW 1 "Adjusted density exceeds 1.00 ([format %0.3f $or_uniform_adjusted_density]),\
         reverting to use ($openroad_gpl_place_density) for global placement"
@@ -56,8 +58,10 @@ proc sc_global_placement { args } {
   global openroad_gpl_padding
 
   set openroad_gpl_args []
-  if { $openroad_gpl_routability_driven == "true" && \
-       ![info exists flags(-disable_routability_driven)] } {
+  if {
+    $openroad_gpl_routability_driven == "true" &&
+    ![info exists flags(-disable_routability_driven)]
+  } {
     lappend openroad_gpl_args "-routability_driven"
   }
   if { $openroad_gpl_timing_driven == "true" } {
@@ -235,8 +239,10 @@ proc sc_design_has_unplaced_pads {} {
 
 proc sc_design_has_placeable_ios {} {
   foreach bterm [[ord::get_db_block] getBTerms] {
-    if { [$bterm getFirstPinPlacementStatus] != "FIXED" &&
-         [$bterm getFirstPinPlacementStatus] != "LOCKED" } {
+    if {
+      [$bterm getFirstPinPlacementStatus] != "FIXED" &&
+      [$bterm getFirstPinPlacementStatus] != "LOCKED"
+    } {
       return true
     }
   }
@@ -421,3 +427,29 @@ proc count_logic_depth {} {
   # Subtract 1 to account for initial launch
   return [expr { $count - 1 }]
 }
+
+###########################
+# Translate schema rotation
+###########################
+
+proc sc_convert_rotation { rot } {
+  if { [string match "MZ*" $rot] } {
+    utl::error FLW 1 "Z mirroring is not supported in OpenROAD"
+  }
+
+  switch $rot {
+    "R0" { return "R0" }
+    "R90" { return "R90" }
+    "R180" { return "R180" }
+    "R270" { return "R270" }
+    "MX" { return "MX" }
+    "MX_R90" { return "MXR90" }
+    "MX_R180" { return "MY" }
+    "MX_R270" { return "MYR90" }
+    "MY" { return "MY" }
+    "MY_R90" { return "MYR90" }
+    "MY_R180" { return "MX" }
+    "MY_R270" { return "MXR90" }
+    default { utl::error FLW 1 "$rot not recognized" }
+  }
+}

siliconcompiler/tools/openroad/scripts/sc_rcx.tcl

@@ -9,7 +9,7 @@ source ./sc_manifest.tcl > /dev/null
 ###############################
 
 proc sc_get_layer_name { name } {
-  if { [ string is integer $name ] } {
+  if { [string is integer $name] } {
     set layer [[ord::get_db_tech] findRoutingLayer $name]
     if { $layer == "NULL" } {
       utl::error FLW 1 "$name is not a valid routing layer."
@@ -23,18 +23,18 @@ proc sc_get_layer_name { name } {
 # Schema Adapter
 ###############################
 
-set sc_tool   openroad
-set sc_step   [sc_cfg_get arg step]
-set sc_index  [sc_cfg_get arg index]
-set sc_flow   [sc_cfg_get option flow]
-set sc_task   [sc_cfg_get flowgraph $sc_flow $sc_step $sc_index task]
+set sc_tool openroad
+set sc_step [sc_cfg_get arg step]
+set sc_index [sc_cfg_get arg index]
+set sc_flow [sc_cfg_get option flow]
+set sc_task [sc_cfg_get flowgraph $sc_flow $sc_step $sc_index task]
 
 set sc_refdir [sc_cfg_tool_task_get refdir]
 
 # Design
-set sc_design     [sc_top]
-set sc_pdk        [sc_cfg_get option pdk]
-set sc_stackup    [sc_cfg_get option stackup]
+set sc_design [sc_top]
+set sc_pdk [sc_cfg_get option pdk]
+set sc_stackup [sc_cfg_get option stackup]
 
 # Library
 set sc_libtype [lindex [sc_cfg_tool_task_get {var} libtype] 0]

siliconcompiler/tools/openroad/scripts/sc_route.tcl

@@ -71,10 +71,14 @@ global_route -guide_file "./route.guide" \
 ######################
 
 estimate_parasitics -global_routing
-if { $openroad_ant_check == "true" && \
-     [check_antennas -report_file "reports/${sc_design}_antenna.rpt"] != 0 } {
-  if { $openroad_ant_repair == "true" && \
-       [llength [sc_cfg_get library $sc_mainlib asic cells antenna]] != 0 } {
+if {
+  $openroad_ant_check == "true" &&
+  [check_antennas -report_file "reports/${sc_design}_antenna.rpt"] != 0
+} {
+  if {
+    $openroad_ant_repair == "true" &&
+    [llength [sc_cfg_get library $sc_mainlib asic cells antenna]] != 0
+  } {
     set sc_antenna [lindex [sc_cfg_get library $sc_mainlib asic cells antenna] 0]
 
     # Remove filler cells before attempting to repair antennas

siliconcompiler/tools/openroad/scripts/sc_screenshot.tcl

@@ -14,8 +14,10 @@ sc_save_image "screenshot" "outputs/${sc_design}.png" $sc_resolution
 
 gui::restore_display_controls
 
-if { [sc_cfg_tool_task_exists {var} include_report_images] &&
-     [lindex [sc_cfg_tool_task_get {var} include_report_images] 0]
-     == "true" } {
+if {
+  [sc_cfg_tool_task_exists {var} include_report_images] &&
+  [lindex [sc_cfg_tool_task_get {var} include_report_images] 0]
+  == "true"
+} {
   source -echo "${sc_refdir}/sc_write_images.tcl"
 }

siliconcompiler/tools/openroad/scripts/sc_write_images.tcl

@@ -156,12 +156,13 @@ proc sc_image_estimated_routing_congestion {} {
   sc_image_setup_default
 
   suppress_message GRT 10
-  catch { \
+  catch {
     sc_image_heatmap "Estimated Congestion (RUDY)" \
       "RUDY" \
       "estimated_routing_congestion.png" \
       "estimated routing congestion" \
-      0 } err
+      0
+  } err
   unsuppress_message GRT 10
 }
 
@@ -271,30 +272,31 @@ proc sc_image_optimizer {} {
   gui::set_display_controls "Instances/*" visible true
   gui::set_display_controls "Instances/Physical/*" visible false
 
-  set hold_count       [select -name "hold*" -type Inst -highlight 0]       ;# green
-  set input_count      [select -name "input*" -type Inst -highlight 1]      ;# yellow
-  set output_count     [select -name "output*" -type Inst -highlight 1]
-  set repeater_count   [select -name "repeater*" -type Inst -highlight 3]   ;# magenta
-  set fanout_count     [select -name "fanout*" -type Inst -highlight 3]
-  set load_slew_count  [select -name "load_slew*" -type Inst -highlight 3]
-  set max_cap_count    [select -name "max_cap*" -type Inst -highlight 3]
+  set hold_count [select -name "hold*" -type Inst -highlight 0] ;# green
+  set input_count [select -name "input*" -type Inst -highlight 1] ;# yellow
+  set output_count [select -name "output*" -type Inst -highlight 1]
+  set repeater_count [select -name "repeater*" -type Inst -highlight 3] ;# magenta
+  set fanout_count [select -name "fanout*" -type Inst -highlight 3]
+  set load_slew_count [select -name "load_slew*" -type Inst -highlight 3]
+  set max_cap_count [select -name "max_cap*" -type Inst -highlight 3]
   set max_length_count [select -name "max_length*" -type Inst -highlight 3]
-  set wire_count       [select -name "wire*" -type Inst -highlight 3]
-  set rebuffer_count   [select -name "rebuffer*" -type Inst -highlight 4]   ;# red
-  set split_count      [select -name "split*" -type Inst -highlight 5]      ;# dark green
-
-  set select_count [expr { \
-    $hold_count + \
-    $input_count + \
-    $output_count + \
-    $repeater_count + \
-    $fanout_count + \
-    $load_slew_count + \
-    $max_cap_count + \
-    $max_length_count + \
-    $wire_count + \
-    $rebuffer_count + \
-    $split_count }]
+  set wire_count [select -name "wire*" -type Inst -highlight 3]
+  set rebuffer_count [select -name "rebuffer*" -type Inst -highlight 4] ;# red
+  set split_count [select -name "split*" -type Inst -highlight 5] ;# dark green
+
+  set select_count [expr {
+    $hold_count +
+    $input_count +
+    $output_count +
+    $repeater_count +
+    $fanout_count +
+    $load_slew_count +
+    $max_cap_count +
+    $max_length_count +
+    $wire_count +
+    $rebuffer_count +
+    $split_count
+  }]
 
   if { $select_count == 0 } {
     # Nothing selected

siliconcompiler/tools/opensta/scripts/sc_procs.tcl

@@ -1,4 +1,3 @@
-
 ###########################
 # Count the logic depth of the critical path
 ###########################

siliconcompiler/tools/verilator/compile.py

@@ -8,9 +8,6 @@ def setup(chip):
     Compiles Verilog and C/C++ sources into an executable. In addition to the
     standard RTL inputs, this task reads C/C++ sources from :keypath:`input,
     hll, c`.  Outputs an executable in ``outputs/<design>.vexe``.
-
-    This task supports using the :keypath:`option, trace` parameter to enable
-    Verilator's ``--trace`` flag.
     '''
 
     # Generic tool setup.
@@ -69,7 +66,7 @@ def setup(chip):
              "if true, enables trace generation.",
              field='help')
     chip.set('tool', tool, 'task', task, 'var', 'trace_type',
-             "specifies type of wave file to create when [option, trace] is set. Valid options are "
+             "specifies type of wave file to create when [trace] is set. Valid options are "
              "'vcd' or 'fst'. Defaults to 'vcd'.",
              field='help')
 

siliconcompiler/tools/verilator/verilator.py

@@ -14,8 +14,7 @@ exist, through the following keypaths:
     * :keypath:`option, idir`
 
 For all tasks, this driver runs Verilator using the ``-sv`` switch to enable
-parsing a subset of SystemVerilog features. All tasks also support using
-:keypath:`option, relax` to make warnings nonfatal.
+parsing a subset of SystemVerilog features.
 
 Documentation: https://verilator.org/guide/latest
 

siliconcompiler/tools/vivado/scripts/sc_run.tcl

@@ -1,4 +1,3 @@
-
 ###############################
 # Reading SC Schema
 ###############################
@@ -15,13 +14,13 @@ if { [sc_cfg_exists input fpga xdc] } {
 } else {
     set sc_constraint ""
 }
-set sc_tool       "vivado"
-set sc_partname   [sc_cfg_get fpga partname]
-set sc_step       [sc_cfg_get arg step]
-set sc_index      [sc_cfg_get arg index]
-set sc_flow       [sc_cfg_get option flow]
-set sc_task       [sc_cfg_get flowgraph $sc_flow $sc_step $sc_index task]
-set sc_refdir     [sc_cfg_tool_task_get refdir]
+set sc_tool "vivado"
+set sc_partname [sc_cfg_get fpga partname]
+set sc_step [sc_cfg_get arg step]
+set sc_index [sc_cfg_get arg index]
+set sc_flow [sc_cfg_get option flow]
+set sc_task [sc_cfg_get flowgraph $sc_flow $sc_step $sc_index task]
+set sc_refdir [sc_cfg_tool_task_get refdir]
 
 source $sc_refdir/sc_$sc_task.tcl
 

siliconcompiler/tools/vivado/vivado.py

@@ -2,7 +2,7 @@
 Vivado is an FPGA programming tool suite from Xilinx used to
 program Xilinx devices.
 
-Documentation: https://www.xilinx.com/products/design-tools/vivado.html
+Documentation: https://www.amd.com/en/products/software/adaptive-socs-and-fpgas/vivado.html
 '''
 
 import json

siliconcompiler/tools/vpr/place.py

@@ -31,6 +31,9 @@ def setup(chip, clobber=True):
     chip.add('tool', tool, 'task', task, 'output', design + '.net', step=step, index=index)
     chip.add('tool', tool, 'task', task, 'output', design + '.place', step=step, index=index)
 
+    chip.set('tool', tool, 'task', task, 'var', 'placement', 'component placement constraints',
+             field='help')
+
 
 def runtime_options(chip):
     '''Command line options to vpr for the place step
@@ -75,12 +78,13 @@ def pre_process(chip):
 
     step = chip.get('arg', 'step')
     index = chip.get('arg', 'index')
+    tool, task = get_tool_task(chip, step, index)
 
     part_name = chip.get('fpga', 'partname')
 
     # If the user explicitly provides an XML constraints file, give that
     # priority over other constraints input types:
-    if 'vpr_pins' in chip.getkeys('input', 'constraint'):
+    if chip.valid('input', 'constraint', 'vpr_pins'):
         constraint_file = vpr.find_single_file(chip, 'input', 'constraint', 'vpr_pins',
                                                step=step, index=index,
                                                file_not_found_msg="VPR constraints file not found")
@@ -88,7 +92,7 @@ def pre_process(chip):
         if (constraint_file is not None):
             shutil.copy2(constraint_file, vpr.auto_constraints())
 
-    elif 'pcf' in chip.getkeys('input', 'constraint'):
+    elif chip.valid('input', 'constraint', 'pcf'):
         constraint_file = vpr.find_single_file(chip, 'input', 'constraint', 'pcf',
                                                step=step, index=index,
                                                file_not_found_msg="PCF constraints file not found")
@@ -111,11 +115,13 @@ def pre_process(chip):
         generate_vpr_constraints_xml_file(all_place_constraints, vpr.auto_constraints())
 
     else:
-        all_component_constraints = chip.getkeys('constraint', 'component')
+        all_component_constraints = chip.get('tool', tool, 'task', task, 'var', 'placement',
+                                             step=step, index=index)
+
         all_place_constraints = {}
-        for component in all_component_constraints:
-            place_constraint = chip.get('constraint', 'component', component, 'placement',
-                                        step=step, index=index)
+        for constraint in all_component_constraints:
+            component, *place_constraint = constraint.split(",")
+            place_constraint = tuple([int(loc) for loc in place_constraint])
             chip.logger.info(f'Place constraint for {component} at {place_constraint}')
             all_place_constraints[component] = place_constraint
 
@@ -123,6 +129,14 @@ def pre_process(chip):
             generate_vpr_constraints_xml_file(all_place_constraints, vpr.auto_constraints())
 
 
+def add_placement_constraint(chip, component, location, step=None, index=None):
+    tool = 'vpr'
+    task = 'place'
+
+    constraint = f"{component},{','.join([str(loc) for loc in location])}"
+
+    chip.add('tool', tool, 'task', task, 'var', 'placement', constraint, step=step, index=index)
+
 ################################
 # Post_process (post executable)
 ################################

siliconcompiler/tools/vpr/vpr.py

@@ -134,7 +134,7 @@ def runtime_options(chip):
                 'vpr_clock model must be set to ideal, route, or dedicated_clock_network',
                 chip=chip)
 
-    if 'sdc' in chip.getkeys('input', 'constraint'):
+    if chip.valid('input', 'constraint', 'sdc'):
         sdc_file = find_single_file(chip, 'input', 'constraint', 'sdc',
                                     step=step, index=index,
                                     file_not_found_msg="SDC file not found")

siliconcompiler/tools/xdm/__init__.py

@@ -0,0 +1,28 @@
+'''
+Xyce XDM netlist converter, used to convert PSPICE and HSPICE netists into Xyce format.
+
+Sources: https://github.com/Xyce/XDM
+
+Installation: https://github.com/Xyce/XDM
+
+Status: SC integration WIP
+'''
+from siliconcompiler.tools._common import get_tool_task
+
+
+def setup(chip):
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    tool, task = get_tool_task(chip, step, index)
+
+    chip.set('tool', tool, 'exe', 'xdm_bdl')
+    chip.set('tool', tool, 'vswitch', '-h')
+    chip.set('tool', tool, 'version', '>=v2.7.0', clobber=False)
+
+
+################################
+# Version Check
+################################
+def parse_version(stdout):
+    line = stdout.splitlines()[5]
+    return line.split()[1]

siliconcompiler/tools/xdm/convert.py

@@ -0,0 +1,71 @@
+from siliconcompiler.tools._common import input_provides, get_tool_task
+from siliconcompiler.tools.xdm import setup as tool_setup
+import os
+import shutil
+
+
+def setup(chip):
+    tool_setup(chip)
+
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    tool, task = get_tool_task(chip, step, index)
+
+    design = chip.top()
+
+    if f'{design}.cir' in input_provides(chip, step, index):
+        chip.add('tool', tool, 'task', task, 'input', f'{design}.cir',
+                 step=step, index=index)
+    else:
+        chip.add('tool', tool, 'task', task, 'require', 'input,netlist,spice',
+                 step=step, index=index)
+
+    chip.add('tool', tool, 'task', task, 'output', f'{design}.xyce', step=step, index=index)
+
+    chip.add('tool', tool, 'task', task, 'option', '--auto',
+             step=step, index=index)
+    chip.add('tool', tool, 'task', task, 'option', '--source_file_format hspice',
+             step=step, index=index)
+    chip.add('tool', tool, 'task', task, 'option', f'--dir_out outputs/{design}.xyce',
+             step=step, index=index)
+
+    chip.set('tool', 'xdm', 'task', 'convert', 'var', 'rename', 'true',
+             step=step, index=index, clobber=False)
+    chip.set('tool', 'xdm', 'task', 'convert', 'var', 'rename',
+             'true/false: indicate whether to rename the output file to match the '
+             'naming scheme for siliconcompiler', field='help')
+
+
+def runtime_options(chip):
+    return __get_input_file(chip)
+
+
+def __get_input_file(chip):
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    design = chip.top()
+
+    if f'{design}.cir' in input_provides(chip, step, index):
+        return [f'inputs/{design}.cir']
+
+    return chip.find_files('input', 'netlist', 'spice',
+                           step=step, index=index)
+
+
+def post_process(chip):
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+
+    if chip.get('tool', 'xdm', 'task', 'convert', 'var', 'rename',
+                step=step, index=index) == ['false']:
+        return
+
+    inputfile = __get_input_file(chip)[0]
+
+    outdir = f'outputs/{chip.top()}.xyce'
+
+    inputfile_base = os.path.basename(inputfile)
+    outputfile_base = f'{chip.top()}.cir'
+
+    if inputfile_base != outputfile_base:
+        shutil.move(os.path.join(outdir, inputfile_base), os.path.join(outdir, outputfile_base))