siliconcompiler 0.27.1__py3-none-any.whl → 0.28.1__py3-none-any.whl

siliconcompiler/schema/schema_obj.py

@@ -608,7 +608,7 @@ class Schema:
 
         See :meth:`~siliconcompiler.core.Chip.getkeys` for detailed documentation.
         """
-        cfg = self.__search(*keypath, job=job)
+        cfg = self.__search(*keypath, job=job, use_default=False)
         keys = list(cfg.keys())
 
         if 'default' in keys:
@@ -946,7 +946,7 @@ class Schema:
 
         return None
 
-    def __search(self, *keypath, insert_defaults=False, job=None):
+    def __search(self, *keypath, insert_defaults=False, use_default=True, job=None):
         if job is not None:
             cfg = self.cfg['history'][job]
         else:
@@ -965,8 +965,10 @@ class Schema:
                 if insert_defaults:
                     cfg[key] = copy.deepcopy(cfg['default'])
                     cfg = cfg[key]
-                else:
+                elif use_default:
                     cfg = cfg['default']
+                else:
+                    raise ValueError(f'Invalid keypath {keypath}: unexpected key: {key}')
             else:
                 raise ValueError(f'Invalid keypath {keypath}: unexpected key: {key}')
 

siliconcompiler/sphinx_ext/dynamicgen.py

@@ -197,7 +197,7 @@ class DynamicGen(SphinxDirective):
             chips = self.configure_chip_for_docs(module)
         except Exception as e:
             print("Failed:", e)
-            return None
+            # raise e
 
         if not chips:
             return None
@@ -274,7 +274,7 @@ class DynamicGen(SphinxDirective):
         directory.'''
         modules = []
         for importer, modname, _ in pkgutil.iter_modules([module_dir]):
-            module = importer.find_module(modname).load_module(modname)
+            module = importer.find_spec(modname).loader.load_module(modname)
             modules.append((module, modname))
 
         return modules
@@ -399,7 +399,7 @@ class DynamicGen(SphinxDirective):
         if docs_chip and docs_configured:
             return docs_chip
 
-        return self._handle_setup(module)
+        return self._handle_setup(chip, module)
 
     def get_ref_prefix(self):
         return self.REF_PREFIX
@@ -635,7 +635,7 @@ class ToolGen(DynamicGen):
         if toolmodule:
             return chip
         else:
-            return self._handle_setup(module)
+            return self._handle_setup(chip, module)
 
     def display_config(self, chip, modname):
         '''Display config under `eda, <modname>` in a single table.'''
@@ -726,7 +726,7 @@ class ToolGen(DynamicGen):
             s += p
 
         try:
-            task_setup()
+            task_setup(chip)
 
             config = build_section("Configuration", self.get_configuration_ref_key(toolname,
                                                                                    taskname))
@@ -738,8 +738,7 @@ class ToolGen(DynamicGen):
                                       [toolname, taskname, 'params'],
                                       s)
         except Exception as e:
-            print('Failed to document task, Chip object probably not configured correctly.')
-            print(e)
+            print(f'Failed to document task, Chip object probably not configured correctly: {e}')
             return None
 
         return s
@@ -791,6 +790,15 @@ class ToolGen(DynamicGen):
         self._document_free_params(cfg, 'var', key_path + ['var'], reference_prefix, s)
         self._document_free_params(cfg, 'file', key_path + ['file'], reference_prefix, s)
 
+    def _handle_setup(self, chip, module):
+        setup = self.get_setup_method(module)
+        if not setup:
+            return None
+
+        setup(chip)
+
+        return chip
+
 
 class TargetGen(DynamicGen):
     PATH = 'targets'
@@ -816,20 +824,23 @@ class TargetGen(DynamicGen):
     def display_config(self, chip, modname):
         sections = []
 
-        flow_section = self.build_module_list(chip, 'Flows', 'flows', modname, FlowGen.REF_PREFIX)
-        if flow_section is not None:
-            sections.append(flow_section)
-
-        pdk_section = self.build_module_list(chip, 'PDK', 'pdks', modname, PDKGen.REF_PREFIX)
+        pdk_section = self.build_module_list(
+            chip, 'Included PDK', 'pdks', modname, PDKGen.REF_PREFIX)
         if pdk_section is not None:
             sections.append(pdk_section)
 
-        libs_section = self.build_module_list(chip, 'Libraries', 'libs', modname, LibGen.REF_PREFIX)
+        libs_section = self.build_module_list(
+            chip, 'Included libraries', 'libs', modname, LibGen.REF_PREFIX)
         if libs_section is not None:
             sections.append(libs_section)
 
-        checklist_section = self.build_module_list(chip, 'Checklists', 'checklists', modname,
-                                                   ChecklistGen.REF_PREFIX)
+        flow_section = self.build_module_list(
+            chip, 'Included flows', 'flows', modname, FlowGen.REF_PREFIX)
+        if flow_section is not None:
+            sections.append(flow_section)
+
+        checklist_section = self.build_module_list(
+            chip, 'Included checklists', 'checklists', modname, ChecklistGen.REF_PREFIX)
         if checklist_section is not None:
             sections.append(checklist_section)
 
@@ -847,6 +858,15 @@ class TargetGen(DynamicGen):
 
         return sections
 
+    def _handle_setup(self, chip, module):
+        setup = self.get_setup_method(module)
+        if not setup:
+            return None
+
+        setup(chip)
+
+        return chip
+
 
 class AppGen(DynamicGen):
     PATH = 'apps'

siliconcompiler/sphinx_ext/schemagen.py

@@ -77,7 +77,9 @@ class SchemaGen(SphinxDirective):
                 if key == 'default':
                     for n in self.process_schema(schema['default'], parents=parents):
                         sections.append(n)
-                elif key not in ('history', 'library'):
+                else:
+                    if not parents and key in ('history', 'library'):
+                        continue
                     section_key = 'param-' + '-'.join(parents + [key])
                     section = build_section_with_target(key, section_key, self.state.document)
                     for n in self.process_schema(schema[key], parents=parents + [key]):
@@ -165,6 +167,7 @@ class CategoryGroupTable(SphinxDirective):
             "record": "Compilation history tracking",
             "package": "Packaging manifest",
             "datasheet": "Design interface specifications",
+            "schematic": "Schematic specifications",
 
             # Nothing to document
             "library": "",

siliconcompiler/targets/ihp130_demo.py

@@ -0,0 +1,68 @@
+import siliconcompiler
+from siliconcompiler.flows import asicflow, asictopflow, signoffflow, synflow
+from siliconcompiler.checklists import oh_tapeout
+from lambdapdk import ihp130
+from lambdapdk.ihp130.libs import sg13g2_stdcell
+
+
+####################################################
+# Target Setup
+####################################################
+def setup(chip, syn_np=1, floorplan_np=1, physyn_np=1, place_np=1, cts_np=1, route_np=1,
+          timing_np=1):
+    '''
+    IHP130 Demo Target
+    '''
+
+    asic_flow_args = {
+        "syn_np": syn_np,
+        "floorplan_np": floorplan_np,
+        "physyn_np": physyn_np,
+        "place_np": place_np,
+        "cts_np": cts_np,
+        "route_np": route_np
+    }
+    # 1. Load PDK, flow, libs
+    chip.use(ihp130)
+    chip.use(sg13g2_stdcell)
+    chip.use(asicflow, **asic_flow_args)
+    chip.use(synflow, syn_np=syn_np, timing_np=timing_np)
+    chip.use(asictopflow)
+    chip.use(signoffflow)
+    chip.use(oh_tapeout)
+
+    # 2. Set default targets
+    chip.set('option', 'flow', 'asicflow', clobber=False)
+    chip.set('option', 'pdk', 'ihp130', clobber=False)
+    chip.set('option', 'stackup', '5M2TL', clobber=False)
+
+    # 3. Set project specific design choices
+    chip.set('asic', 'logiclib', 'sg13g2_stdcell', clobber=False)
+
+    # 4. get project specific design choices
+    chip.set('asic', 'delaymodel', 'nldm', clobber=False)
+    chip.set('constraint', 'density', 40, clobber=False)
+    chip.set('constraint', 'coremargin', 4.8, clobber=False)
+
+    # 5. Timing corners
+    chip.set('constraint', 'timing', 'slow', 'libcorner', 'slow', clobber=False)
+    chip.set('constraint', 'timing', 'slow', 'pexcorner', 'typical', clobber=False)
+    chip.set('constraint', 'timing', 'slow', 'mode', 'func', clobber=False)
+    chip.set('constraint', 'timing', 'slow', 'check', ['setup', 'hold'], clobber=False)
+
+    chip.set('constraint', 'timing', 'fast', 'libcorner', 'fast', clobber=False)
+    chip.set('constraint', 'timing', 'fast', 'pexcorner', 'typical', clobber=False)
+    chip.set('constraint', 'timing', 'fast', 'mode', 'func', clobber=False)
+    chip.set('constraint', 'timing', 'fast', 'check', ['setup', 'hold'], clobber=False)
+
+    chip.set('constraint', 'timing', 'typical', 'libcorner', 'typ', clobber=False)
+    chip.set('constraint', 'timing', 'typical', 'pexcorner', 'typical', clobber=False)
+    chip.set('constraint', 'timing', 'typical', 'mode', 'func', clobber=False)
+    chip.set('constraint', 'timing', 'typical', 'check', ['power'], clobber=False)
+
+
+#########################
+if __name__ == "__main__":
+    target = siliconcompiler.Chip('<target>')
+    setup(target)
+    target.write_manifest('ihp130_demo.json')

siliconcompiler/tools/_common/tcl/sc_pin_constraints.tcl

@@ -3,12 +3,11 @@ proc sc_collect_pin_constraints { \
     ordered_pins_arg \
     sc_side_layer_func \
     { print_func puts } } {
-
     upvar 1 $placement_pins_arg placement_pins
     upvar 1 $ordered_pins_arg ordered_pins
 
     set pin_order [dict create]
-    set placement_pins [list ]
+    set placement_pins [list]
 
     dict for {name params} [sc_cfg_get constraint pin] {
         set order [dict get $params order]

siliconcompiler/tools/builtin/concatenate.py

@@ -4,6 +4,22 @@ from siliconcompiler import sc_open, SiliconCompilerError
 from siliconcompiler import utils
 from siliconcompiler.tools._common import input_provides, input_file_node_name, get_tool_task
 from siliconcompiler import flowgraph
+from siliconcompiler import scheduler
+
+
+def make_docs(chip):
+    from siliconcompiler.flows._common import _make_docs
+    _make_docs(chip)
+    chip.set('option', 'flow', 'asicflow')
+
+    for step, index in flowgraph._get_flowgraph_entry_nodes(chip, 'asicflow'):
+        scheduler._setup_node(chip, step, index)
+
+    chip.set('arg', 'step', 'combine')
+    chip.set('arg', 'index', '0')
+    setup(chip)
+
+    return chip
 
 
 def setup(chip):

siliconcompiler/tools/klayout/klayout.py

@@ -82,6 +82,7 @@ def setup(chip, mode="batch"):
 
     chip.set('tool', tool, 'task', task, 'refdir', refdir, step=step, index=index,
              package='siliconcompiler', clobber=clobber)
+    chip.set('tool', tool, 'task', task, 'threads', 1, step=step, index=index, clobber=clobber)
 
     if chip.get('option', 'nodisplay'):
         # Tells QT to use the offscreen platform if nodisplay is used

siliconcompiler/tools/magic/sc_drc.tcl

@@ -15,13 +15,13 @@
 
 source ./sc_manifest.tcl
 
-set sc_step    [sc_cfg_get arg step]
-set sc_index   [sc_cfg_get arg index]
-set sc_task    $sc_step
+set sc_step [sc_cfg_get arg step]
+set sc_index [sc_cfg_get arg index]
+set sc_task $sc_step
 
-set sc_design    [sc_top]
+set sc_design [sc_top]
 set sc_macrolibs [sc_get_asic_libraries macro]
-set sc_stackup   [sc_cfg_get option stackup]
+set sc_stackup [sc_cfg_get option stackup]
 
 if { [sc_cfg_tool_task_exists var exclude] } {
     set sc_exclude [sc_cfg_tool_task_get var exclude]

siliconcompiler/tools/magic/sc_extspice.tcl

@@ -1,8 +1,8 @@
 source ./sc_manifest.tcl
 
-set sc_step    [sc_cfg_get arg step]
-set sc_index   [sc_cfg_get arg index]
-set sc_task    $sc_step
+set sc_step [sc_cfg_get arg step]
+set sc_index [sc_cfg_get arg index]
+set sc_task $sc_step
 
 set sc_design [sc_top]
 set sc_logiclibs [sc_get_asic_libraries logic]

siliconcompiler/tools/magic/sc_magic.tcl

@@ -36,8 +36,8 @@ if { $sc_pdk == "skywater130" } {
     cif istyle sky130(vendor)
 }
 
-set mydir      [file dirname [file normalize [info script]]]
-set sc_step    [sc_cfg_get arg step]
+set mydir [file dirname [file normalize [info script]]]
+set sc_step [sc_cfg_get arg step]
 
 if { [catch { source "$mydir/sc_${sc_step}.tcl" } err] } {
     puts $err

siliconcompiler/tools/netgen/sc_lvs.tcl

@@ -1,8 +1,8 @@
 source ./sc_manifest.tcl
 
-set sc_step    [sc_cfg_get arg step]
-set sc_index   [sc_cfg_get arg index]
-set sc_task    $sc_step
+set sc_step [sc_cfg_get arg step]
+set sc_index [sc_cfg_get arg index]
+set sc_task $sc_step
 
 set sc_design [sc_top]
 set sc_macrolibs [sc_get_asic_libraries macro]

siliconcompiler/tools/openroad/scripts/sc_apr.tcl

@@ -19,7 +19,7 @@ proc sc_get_layer_name { name } {
   if { [string length $name] == 0 } {
     return ""
   }
-  if { [ string is integer $name ] } {
+  if { [string is integer $name] } {
     set layer [[ord::get_db_tech] findRoutingLayer $name]
     if { $layer == "NULL" } {
       utl::error FLW 1 "$name is not a valid routing layer."
@@ -35,8 +35,10 @@ proc has_tie_cell { type } {
   upvar sc_tool sc_tool
 
   set library_vars [sc_cfg_get library $sc_mainlib option {var}]
-  return [expr { [dict exists $library_vars openroad_tie${type}_cell] && \
-                 [dict exists $library_vars openroad_tie${type}_port] }]
+  return [expr {
+    [dict exists $library_vars openroad_tie${type}_cell] &&
+    [dict exists $library_vars openroad_tie${type}_port]
+  }]
 }
 
 proc get_tie_cell { type } {
@@ -54,46 +56,46 @@ proc get_tie_cell { type } {
 # Schema Adapter
 ###############################
 
-set sc_tool   openroad
-set sc_step   [sc_cfg_get arg step]
-set sc_index  [sc_cfg_get arg index]
-set sc_flow   [sc_cfg_get option flow]
-set sc_task   [sc_cfg_get flowgraph $sc_flow $sc_step $sc_index task]
+set sc_tool openroad
+set sc_step [sc_cfg_get arg step]
+set sc_index [sc_cfg_get arg index]
+set sc_flow [sc_cfg_get option flow]
+set sc_task [sc_cfg_get flowgraph $sc_flow $sc_step $sc_index task]
 
-set sc_refdir [sc_cfg_tool_task_get refdir ]
+set sc_refdir [sc_cfg_tool_task_get refdir]
 
 # Design
-set sc_design     [sc_top]
-set sc_optmode    [sc_cfg_get option optmode]
-set sc_pdk        [sc_cfg_get option pdk]
-set sc_stackup    [sc_cfg_get option stackup]
+set sc_design [sc_top]
+set sc_optmode [sc_cfg_get option optmode]
+set sc_pdk [sc_cfg_get option pdk]
+set sc_stackup [sc_cfg_get option stackup]
 
 # APR Parameters
-set sc_targetlibs  [sc_get_asic_libraries logic]
-set sc_mainlib     [lindex $sc_targetlibs 0]
-set sc_delaymodel  [sc_cfg_get asic delaymodel]
-set sc_pdk_vars    [sc_cfg_get pdk $sc_pdk {var} $sc_tool]
-set sc_hpinmetal   [dict get $sc_pdk_vars pin_layer_horizontal $sc_stackup]
-set sc_vpinmetal   [dict get $sc_pdk_vars pin_layer_vertical $sc_stackup]
-set sc_rc_signal   [lindex [dict get $sc_pdk_vars rclayer_signal $sc_stackup] 0]
-set sc_rc_clk      [lindex [dict get $sc_pdk_vars rclayer_clock $sc_stackup] 0]
-set sc_minmetal    [sc_cfg_get pdk $sc_pdk minlayer $sc_stackup]
-set sc_maxmetal    [sc_cfg_get pdk $sc_pdk maxlayer $sc_stackup]
+set sc_targetlibs [sc_get_asic_libraries logic]
+set sc_mainlib [lindex $sc_targetlibs 0]
+set sc_delaymodel [sc_cfg_get asic delaymodel]
+set sc_pdk_vars [sc_cfg_get pdk $sc_pdk {var} $sc_tool]
+set sc_hpinmetal [dict get $sc_pdk_vars pin_layer_horizontal $sc_stackup]
+set sc_vpinmetal [dict get $sc_pdk_vars pin_layer_vertical $sc_stackup]
+set sc_rc_signal [lindex [dict get $sc_pdk_vars rclayer_signal $sc_stackup] 0]
+set sc_rc_clk [lindex [dict get $sc_pdk_vars rclayer_clock $sc_stackup] 0]
+set sc_minmetal [sc_cfg_get pdk $sc_pdk minlayer $sc_stackup]
+set sc_maxmetal [sc_cfg_get pdk $sc_pdk maxlayer $sc_stackup]
 set sc_aspectratio [sc_cfg_get constraint aspectratio]
-set sc_density     [sc_cfg_get constraint density]
-set sc_scenarios   [dict keys [sc_cfg_get constraint timing]]
+set sc_density [sc_cfg_get constraint density]
+set sc_scenarios [dict keys [sc_cfg_get constraint timing]]
 
 # Library
 set sc_libtype [sc_cfg_get library $sc_mainlib asic libarch]
 # TODO: handle multiple sites properly
-set sc_site         [lindex [sc_cfg_get library $sc_mainlib asic site $sc_libtype] 0]
-set sc_filler       [sc_cfg_get library $sc_mainlib asic cells filler]
-set sc_dontuse      [sc_cfg_get library $sc_mainlib asic cells dontuse]
-set sc_clkbuf       [lindex [sc_cfg_tool_task_get {var} cts_clock_buffer] 0]
-set sc_filler       [sc_cfg_get library $sc_mainlib asic cells filler]
-set sc_tap          [sc_cfg_get library $sc_mainlib asic cells tap]
-set sc_endcap       [sc_cfg_get library $sc_mainlib asic cells endcap]
-set sc_pex_corners  [sc_cfg_tool_task_get {var} pex_corners]
+set sc_site [lindex [sc_cfg_get library $sc_mainlib asic site $sc_libtype] 0]
+set sc_filler [sc_cfg_get library $sc_mainlib asic cells filler]
+set sc_dontuse [sc_cfg_get library $sc_mainlib asic cells dontuse]
+set sc_clkbuf [lindex [sc_cfg_tool_task_get {var} cts_clock_buffer] 0]
+set sc_filler [sc_cfg_get library $sc_mainlib asic cells filler]
+set sc_tap [sc_cfg_get library $sc_mainlib asic cells tap]
+set sc_endcap [sc_cfg_get library $sc_mainlib asic cells endcap]
+set sc_pex_corners [sc_cfg_tool_task_get {var} pex_corners]
 set sc_power_corner [lindex [sc_cfg_tool_task_get {var} power_corner] 0]
 
 # PDK Design Rules
@@ -394,7 +396,7 @@ if { $sc_task != "floorplan" } {
 
   # Adjust routing track density
   foreach layer [[ord::get_db_tech] getLayers] {
-    if { [ $layer getRoutingLevel ] == 0 } {
+    if { [$layer getRoutingLevel] == 0 } {
       continue
     }
 

siliconcompiler/tools/openroad/scripts/sc_cts.tcl

@@ -4,7 +4,6 @@
 #######################################
 
 if { [llength [all_clocks]] > 0 } {
-
   # Clone clock tree inverters next to register loads
   # so cts does not try to buffer the inverted clocks.
   repair_clock_inverters

siliconcompiler/tools/openroad/scripts/sc_dfm.tcl

@@ -9,8 +9,10 @@ foreach obstruction [[ord::get_db_block] getObstructions] {
 }
 utl::info FLW 1 "Deleted $removed_obs routing obstructions"
 
-if { $openroad_fin_add_fill == "true" && \
-     [sc_cfg_exists pdk $sc_pdk aprtech openroad $sc_stackup $sc_libtype fill] } {
+if {
+  $openroad_fin_add_fill == "true" &&
+  [sc_cfg_exists pdk $sc_pdk aprtech openroad $sc_stackup $sc_libtype fill]
+} {
   set sc_fillrules \
     [lindex [sc_cfg_get pdk $sc_pdk aprtech openroad $sc_stackup $sc_libtype fill] 0]
   density_fill -rules $sc_fillrules

siliconcompiler/tools/openroad/scripts/sc_export.tcl

@@ -3,8 +3,10 @@
 ###########################
 
 set lef_args []
-if { [lindex [sc_cfg_tool_task_get {var} ord_abstract_lef_bloat_layers] 0] \
-      == "true" } {
+if {
+  [lindex [sc_cfg_tool_task_get {var} ord_abstract_lef_bloat_layers] 0]
+  == "true"
+} {
   lappend lef_args "-bloat_occupied_layers"
 } else {
   lappend lef_args \