qiskit 1.3.0__cp39-abi3-win32.whl

qiskit/transpiler/passes/scheduling/scheduling/asap.py

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+# This code is part of Qiskit.
+#
+# (C) Copyright IBM 2020.
+#
+# This code is licensed under the Apache License, Version 2.0. You may
+# obtain a copy of this license in the LICENSE.txt file in the root directory
+# of this source tree or at http://www.apache.org/licenses/LICENSE-2.0.
+#
+# Any modifications or derivative works of this code must retain this
+# copyright notice, and modified files need to carry a notice indicating
+# that they have been altered from the originals.
+
+"""ASAP Scheduling."""
+from qiskit.circuit import Measure
+from qiskit.transpiler.exceptions import TranspilerError
+
+from qiskit.transpiler.passes.scheduling.scheduling.base_scheduler import BaseScheduler
+
+
+class ASAPScheduleAnalysis(BaseScheduler):
+    """ASAP Scheduling pass, which schedules the start time of instructions as early as possible.
+
+    See the :ref:`scheduling_stage` section in the :mod:`qiskit.transpiler`
+    module documentation for the detailed behavior of the control flow
+    operation, i.e. ``c_if``.
+    """
+
+    def run(self, dag):
+        """Run the ASAPSchedule pass on `dag`.
+
+        Args:
+            dag (DAGCircuit): DAG to schedule.
+
+        Returns:
+            DAGCircuit: A scheduled DAG.
+
+        Raises:
+            TranspilerError: if the circuit is not mapped on physical qubits.
+            TranspilerError: if conditional bit is added to non-supported instruction.
+        """
+        if len(dag.qregs) != 1 or dag.qregs.get("q", None) is None:
+            raise TranspilerError("ASAP schedule runs on physical circuits only")
+
+        conditional_latency = self.property_set.get("conditional_latency", 0)
+        clbit_write_latency = self.property_set.get("clbit_write_latency", 0)
+
+        node_start_time = {}
+        idle_after = {q: 0 for q in dag.qubits + dag.clbits}
+        for node in dag.topological_op_nodes():
+            op_duration = self._get_node_duration(node, dag)
+
+            # compute t0, t1: instruction interval, note that
+            # t0: start time of instruction
+            # t1: end time of instruction
+            if isinstance(node.op, self.CONDITIONAL_SUPPORTED):
+                t0q = max(idle_after[q] for q in node.qargs)
+                if node.op.condition_bits:
+                    # conditional is bit tricky due to conditional_latency
+                    t0c = max(idle_after[bit] for bit in node.op.condition_bits)
+                    if t0q > t0c:
+                        # This is situation something like below
+                        #
+                        #           |t0q
+                        # Q ▒▒▒▒▒▒▒▒▒░░
+                        # C ▒▒▒░░░░░░░░
+                        #     |t0c
+                        #
+                        # In this case, you can insert readout access before tq0
+                        #
+                        #           |t0q
+                        # Q ▒▒▒▒▒▒▒▒▒▒▒
+                        # C ▒▒▒░░░▒▒░░░
+                        #         |t0q - conditional_latency
+                        #
+                        t0c = max(t0q - conditional_latency, t0c)
+                    t1c = t0c + conditional_latency
+                    for bit in node.op.condition_bits:
+                        # Lock clbit until state is read
+                        idle_after[bit] = t1c
+                    # It starts after register read access
+                    t0 = max(t0q, t1c)
+                else:
+                    t0 = t0q
+                t1 = t0 + op_duration
+            else:
+                if node.op.condition_bits:
+                    raise TranspilerError(
+                        f"Conditional instruction {node.op.name} is not supported in ASAP scheduler."
+                    )
+
+                if isinstance(node.op, Measure):
+                    # measure instruction handling is bit tricky due to clbit_write_latency
+                    t0q = max(idle_after[q] for q in node.qargs)
+                    t0c = max(idle_after[c] for c in node.cargs)
+                    # Assume following case (t0c > t0q)
+                    #
+                    #       |t0q
+                    # Q ▒▒▒▒░░░░░░░░░░░░
+                    # C ▒▒▒▒▒▒▒▒░░░░░░░░
+                    #           |t0c
+                    #
+                    # In this case, there is no actual clbit access until clbit_write_latency.
+                    # The node t0 can be push backward by this amount.
+                    #
+                    #         |t0q' = t0c - clbit_write_latency
+                    # Q ▒▒▒▒░░▒▒▒▒▒▒▒▒▒▒
+                    # C ▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒
+                    #           |t0c' = t0c
+                    #
+                    # rather than naively doing
+                    #
+                    #           |t0q' = t0c
+                    # Q ▒▒▒▒░░░░▒▒▒▒▒▒▒▒
+                    # C ▒▒▒▒▒▒▒▒░░░▒▒▒▒▒
+                    #              |t0c' = t0c + clbit_write_latency
+                    #
+                    t0 = max(t0q, t0c - clbit_write_latency)
+                    t1 = t0 + op_duration
+                    for clbit in node.cargs:
+                        idle_after[clbit] = t1
+                else:
+                    # It happens to be directives such as barrier
+                    t0 = max(idle_after[bit] for bit in node.qargs + node.cargs)
+                    t1 = t0 + op_duration
+
+            for bit in node.qargs:
+                idle_after[bit] = t1
+
+            node_start_time[node] = t0
+
+        self.property_set["node_start_time"] = node_start_time

qiskit/transpiler/passes/scheduling/scheduling/base_scheduler.py

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+# This code is part of Qiskit.
+#
+# (C) Copyright IBM 2020.
+#
+# This code is licensed under the Apache License, Version 2.0. You may
+# obtain a copy of this license in the LICENSE.txt file in the root directory
+# of this source tree or at http://www.apache.org/licenses/LICENSE-2.0.
+#
+# Any modifications or derivative works of this code must retain this
+# copyright notice, and modified files need to carry a notice indicating
+# that they have been altered from the originals.
+
+"""Base circuit scheduling pass."""
+
+import warnings
+
+from qiskit.circuit import Delay, Gate
+from qiskit.circuit.parameterexpression import ParameterExpression
+from qiskit.dagcircuit import DAGOpNode, DAGCircuit
+from qiskit.transpiler.basepasses import AnalysisPass
+from qiskit.transpiler.exceptions import TranspilerError
+from qiskit.transpiler.instruction_durations import InstructionDurations
+from qiskit.transpiler.passes.scheduling.time_unit_conversion import TimeUnitConversion
+from qiskit.transpiler.target import Target
+
+
+class BaseScheduler(AnalysisPass):
+    """Base scheduler pass."""
+
+    CONDITIONAL_SUPPORTED = (Gate, Delay)
+
+    def __init__(self, durations: InstructionDurations = None, target: Target = None):
+        """Scheduler initializer.
+
+        Args:
+            durations: Durations of instructions to be used in scheduling
+            target: The :class:`~.Target` representing the target backend, if both
+                  ``durations`` and this are specified then this argument will take
+                  precedence and ``durations`` will be ignored.
+
+        """
+        super().__init__()
+        self.durations = durations
+        if target is not None:
+            self.durations = target.durations()
+
+        # Ensure op node durations are attached and in consistent unit
+        self.requires.append(TimeUnitConversion(inst_durations=durations, target=target))
+
+        # Initialize timeslot
+        if "node_start_time" in self.property_set:
+            warnings.warn(
+                "This circuit has been already scheduled. "
+                "The output of previous scheduling pass will be overridden.",
+                UserWarning,
+            )
+        self.property_set["node_start_time"] = {}
+
+    @staticmethod
+    def _get_node_duration(
+        node: DAGOpNode,
+        dag: DAGCircuit,
+    ) -> int:
+        """A helper method to get duration from node or calibration."""
+        indices = [dag.find_bit(qarg).index for qarg in node.qargs]
+
+        if dag._has_calibration_for(node):
+            # If node has calibration, this value should be the highest priority
+            cal_key = tuple(indices), tuple(float(p) for p in node.op.params)
+            with warnings.catch_warnings():
+                warnings.simplefilter(action="ignore", category=DeprecationWarning)
+                # `schedule.duration` emits pulse deprecation warnings which we don't want
+                # to see here
+                duration = dag._calibrations_prop[node.op.name][cal_key].duration
+
+            # Note that node duration is updated (but this is analysis pass)
+            op = node.op.to_mutable()
+            op.duration = duration
+            dag.substitute_node(node, op, propagate_condition=False)
+        else:
+            duration = node.duration
+
+        if isinstance(duration, ParameterExpression):
+            raise TranspilerError(
+                f"Parameterized duration ({duration}) "
+                f"of {node.op.name} on qubits {indices} is not bounded."
+            )
+        if duration is None:
+            raise TranspilerError(f"Duration of {node.op.name} on qubits {indices} is not found.")
+
+        return duration
+
+    def run(self, dag: DAGCircuit):
+        raise NotImplementedError

qiskit/transpiler/passes/scheduling/scheduling/set_io_latency.py

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+# This code is part of Qiskit.
+#
+# (C) Copyright IBM 2022.
+#
+# This code is licensed under the Apache License, Version 2.0. You may
+# obtain a copy of this license in the LICENSE.txt file in the root directory
+# of this source tree or at http://www.apache.org/licenses/LICENSE-2.0.
+#
+# Any modifications or derivative works of this code must retain this
+# copyright notice, and modified files need to carry a notice indicating
+# that they have been altered from the originals.
+"""Set classical IO latency information to circuit."""
+
+from qiskit.transpiler.basepasses import AnalysisPass
+from qiskit.dagcircuit import DAGCircuit
+
+
+class SetIOLatency(AnalysisPass):
+    """Set IOLatency information to the input circuit.
+
+    The ``clbit_write_latency`` and ``conditional_latency`` are added to
+    the property set of pass manager. This information can be shared among the passes
+    that perform scheduling on instructions acting on classical registers.
+
+    Once these latencies are added to the property set, this information
+    is also copied to the output circuit object as protected attributes,
+    so that it can be utilized outside the transpilation,
+    for example, the timeline visualization can use latency to accurately show
+    time occupation by instructions on the classical registers.
+    """
+
+    def __init__(
+        self,
+        clbit_write_latency: int = 0,
+        conditional_latency: int = 0,
+    ):
+        """Create pass with latency information.
+
+        Args:
+            clbit_write_latency: A control flow constraints. Because standard superconducting
+                quantum processor implement dispersive QND readout, the actual data transfer
+                to the clbit happens after the round-trip stimulus signal is buffered
+                and discriminated into quantum state.
+                The interval ``[t0, t0 + clbit_write_latency]`` is regarded as idle time
+                for clbits associated with the measure instruction.
+                This defaults to 0 dt which is identical to Qiskit Pulse scheduler.
+            conditional_latency: A control flow constraints. This value represents
+                a latency of reading a classical register for the conditional operation.
+                The gate operation occurs after this latency. This appears as a delay
+                in front of the DAGOpNode of the gate.
+                This defaults to 0 dt.
+        """
+        super().__init__()
+        self._conditional_latency = conditional_latency
+        self._clbit_write_latency = clbit_write_latency
+
+    def run(self, dag: DAGCircuit):
+        """Add IO latency information.
+
+        Args:
+            dag: Input DAG circuit.
+        """
+        self.property_set["conditional_latency"] = self._conditional_latency
+        self.property_set["clbit_write_latency"] = self._clbit_write_latency

qiskit/transpiler/passes/scheduling/time_unit_conversion.py

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+# This code is part of Qiskit.
+#
+# (C) Copyright IBM 2021, 2024.
+#
+# This code is licensed under the Apache License, Version 2.0. You may
+# obtain a copy of this license in the LICENSE.txt file in the root directory
+# of this source tree or at http://www.apache.org/licenses/LICENSE-2.0.
+#
+# Any modifications or derivative works of this code must retain this
+# copyright notice, and modified files need to carry a notice indicating
+# that they have been altered from the originals.
+
+"""Unify time unit in circuit for scheduling and following passes."""
+from typing import Set
+import warnings
+
+from qiskit.circuit import Delay
+from qiskit.dagcircuit import DAGCircuit
+from qiskit.transpiler.basepasses import TransformationPass
+from qiskit.transpiler.exceptions import TranspilerError
+from qiskit.transpiler.instruction_durations import InstructionDurations
+from qiskit.transpiler.target import Target
+
+
+class TimeUnitConversion(TransformationPass):
+    """Choose a time unit to be used in the following time-aware passes,
+    and make all circuit time units consistent with that.
+
+    This pass will add a :attr:`.Instruction.duration` metadata to each op whose duration is known
+    which will be used by subsequent scheduling passes for scheduling.
+
+    If ``dt`` (in seconds) is known to transpiler, the unit ``'dt'`` is chosen. Otherwise,
+    the unit to be selected depends on what units are used in delays and instruction durations:
+
+    * ``'s'``: if they are all in SI units.
+    * ``'dt'``: if they are all in the unit ``'dt'``.
+    * raise error: if they are a mix of SI units and ``'dt'``.
+    """
+
+    def __init__(self, inst_durations: InstructionDurations = None, target: Target = None):
+        """TimeUnitAnalysis initializer.
+
+        Args:
+            inst_durations (InstructionDurations): A dictionary of durations of instructions.
+            target: The :class:`~.Target` representing the target backend, if both
+                  ``inst_durations`` and ``target`` are specified then this argument will take
+                  precedence and ``inst_durations`` will be ignored.
+
+
+        """
+        super().__init__()
+        self.inst_durations = inst_durations or InstructionDurations()
+        if target is not None:
+            self.inst_durations = target.durations()
+        self._durations_provided = inst_durations is not None or target is not None
+
+    def run(self, dag: DAGCircuit):
+        """Run the TimeUnitAnalysis pass on `dag`.
+
+        Args:
+            dag (DAGCircuit): DAG to be checked.
+
+        Returns:
+            DAGCircuit: DAG with consistent timing and op nodes annotated with duration.
+
+        Raises:
+            TranspilerError: if the units are not unifiable
+        """
+
+        inst_durations = self._update_inst_durations(dag)
+
+        # Choose unit
+        if inst_durations.dt is not None:
+            time_unit = "dt"
+        else:
+            # Check what units are used in delays and other instructions: dt or SI or mixed
+            units_delay = self._units_used_in_delays(dag)
+            if self._unified(units_delay) == "mixed":
+                raise TranspilerError(
+                    "Fail to unify time units in delays. SI units "
+                    "and dt unit must not be mixed when dt is not supplied."
+                )
+            units_other = inst_durations.units_used()
+            if self._unified(units_other) == "mixed":
+                raise TranspilerError(
+                    "Fail to unify time units in instruction_durations. SI units "
+                    "and dt unit must not be mixed when dt is not supplied."
+                )
+
+            unified_unit = self._unified(units_delay | units_other)
+            if unified_unit == "SI":
+                time_unit = "s"
+            elif unified_unit == "dt":
+                time_unit = "dt"
+            else:
+                raise TranspilerError(
+                    "Fail to unify time units. SI units "
+                    "and dt unit must not be mixed when dt is not supplied."
+                )
+
+        # Make units consistent
+        for node in dag.op_nodes():
+            try:
+                duration = inst_durations.get(
+                    node.op, [dag.find_bit(qarg).index for qarg in node.qargs], unit=time_unit
+                )
+            except TranspilerError:
+                continue
+            op = node.op.to_mutable()
+            op.duration = duration
+            op.unit = time_unit
+            dag.substitute_node(node, op, propagate_condition=False)
+
+        self.property_set["time_unit"] = time_unit
+        return dag
+
+    def _update_inst_durations(self, dag):
+        """Update instruction durations with circuit information. If the dag contains gate
+        calibrations and no instruction durations were provided through the target or as a
+        standalone input, the circuit calibration durations will be used.
+        The priority order for instruction durations is: target > standalone > circuit.
+        """
+        circ_durations = InstructionDurations()
+
+        if dag._calibrations_prop:
+            cal_durations = []
+            with warnings.catch_warnings():
+                warnings.simplefilter(action="ignore", category=DeprecationWarning)
+                # `schedule.duration` emits pulse deprecation warnings which we don't want
+                # to see here
+                for gate, gate_cals in dag._calibrations_prop.items():
+                    for (qubits, parameters), schedule in gate_cals.items():
+                        cal_durations.append((gate, qubits, parameters, schedule.duration))
+            circ_durations.update(cal_durations, circ_durations.dt)
+
+        if self._durations_provided:
+            circ_durations.update(self.inst_durations, getattr(self.inst_durations, "dt", None))
+
+        return circ_durations
+
+    @staticmethod
+    def _units_used_in_delays(dag: DAGCircuit) -> Set[str]:
+        units_used = set()
+        for node in dag.op_nodes(op=Delay):
+            units_used.add(node.op.unit)
+        return units_used
+
+    @staticmethod
+    def _unified(unit_set: Set[str]) -> str:
+        if not unit_set:
+            return "dt"
+
+        if len(unit_set) == 1 and "dt" in unit_set:
+            return "dt"
+
+        all_si = True
+        for unit in unit_set:
+            if not unit.endswith("s"):
+                all_si = False
+                break
+
+        if all_si:
+            return "SI"
+
+        return "mixed"

qiskit/transpiler/passes/synthesis/__init__.py

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+# This code is part of Qiskit.
+#
+# (C) Copyright IBM 2017, 2020.
+#
+# This code is licensed under the Apache License, Version 2.0. You may
+# obtain a copy of this license in the LICENSE.txt file in the root directory
+# of this source tree or at http://www.apache.org/licenses/LICENSE-2.0.
+#
+# Any modifications or derivative works of this code must retain this
+# copyright notice, and modified files need to carry a notice indicating
+# that they have been altered from the originals.
+
+"""Module containing transpiler synthesis passes."""
+
+from .unitary_synthesis import UnitarySynthesis
+from .plugin import high_level_synthesis_plugin_names, unitary_synthesis_plugin_names
+from .linear_functions_synthesis import LinearFunctionsToPermutations
+from .high_level_synthesis import HighLevelSynthesis, HLSConfig
+from .solovay_kitaev_synthesis import SolovayKitaev, SolovayKitaevSynthesis
+from .aqc_plugin import AQCSynthesisPlugin

qiskit/transpiler/passes/synthesis/aqc_plugin.py

@@ -0,0 +1,153 @@
+# This code is part of Qiskit.
+#
+# (C) Copyright IBM 2021, 2023.
+#
+# This code is licensed under the Apache License, Version 2.0. You may
+# obtain a copy of this license in the LICENSE.txt file in the root directory
+# of this source tree or at http://www.apache.org/licenses/LICENSE-2.0.
+#
+# Any modifications or derivative works of this code must retain this
+# copyright notice, and modified files need to carry a notice indicating
+# that they have been altered from the originals.
+"""
+==============================================================================
+AQC Synthesis Plugin (in :mod:`qiskit.transpiler.passes.synthesis.aqc_plugin`)
+==============================================================================
+
+.. autosummary::
+   :toctree: ../stubs/
+
+   AQCSynthesisPlugin
+"""
+from functools import partial
+import math
+
+from qiskit.converters import circuit_to_dag
+from qiskit.transpiler.passes.synthesis.plugin import UnitarySynthesisPlugin
+
+
+class AQCSynthesisPlugin(UnitarySynthesisPlugin):
+    """
+    An AQC-based Qiskit unitary synthesis plugin.
+
+    This plugin is invoked by :func:`~.compiler.transpile` when the ``unitary_synthesis_method``
+    parameter is set to ``"aqc"``.
+
+    This plugin supports customization and additional parameters can be passed to the plugin
+    by passing a dictionary as the ``unitary_synthesis_plugin_config`` parameter of
+    the :func:`~qiskit.compiler.transpile` function.
+
+    Supported parameters in the dictionary:
+
+    network_layout (str)
+        Type of network geometry, one of {``"sequ"``, ``"spin"``, ``"cart"``, ``"cyclic_spin"``,
+        ``"cyclic_line"``}. Default value is ``"spin"``.
+
+    connectivity_type (str)
+        type of inter-qubit connectivity, {``"full"``, ``"line"``, ``"star"``}.  Default value
+        is ``"full"``.
+
+    depth (int)
+        depth of the CNOT-network, i.e. the number of layers, where each layer consists of a
+        single CNOT-block.
+
+    optimizer (:class:`~.Minimizer`)
+        An implementation of the ``Minimizer`` protocol to be used in the optimization process.
+
+    seed (int)
+        A random seed.
+
+    initial_point (:class:`~numpy.ndarray`)
+        Initial values of angles/parameters to start the optimization process from.
+    """
+
+    @property
+    def max_qubits(self):
+        """Maximum number of supported qubits is ``14``."""
+        return 14
+
+    @property
+    def min_qubits(self):
+        """Minimum number of supported qubits is ``3``."""
+        return 3
+
+    @property
+    def supports_natural_direction(self):
+        """The plugin does not support natural direction,
+        it assumes bidirectional two qubit gates."""
+        return False
+
+    @property
+    def supports_pulse_optimize(self):
+        """The plugin does not support optimization of pulses."""
+        return False
+
+    @property
+    def supports_gate_lengths(self):
+        """The plugin does not support gate lengths."""
+        return False
+
+    @property
+    def supports_gate_errors(self):
+        """The plugin does not support gate errors."""
+        return False
+
+    @property
+    def supported_bases(self):
+        """The plugin does not support bases for synthesis."""
+        return None
+
+    @property
+    def supports_basis_gates(self):
+        """The plugin does not support basis gates and by default it synthesizes a circuit using
+        ``["rx", "ry", "rz", "cx"]`` gate basis."""
+        return False
+
+    @property
+    def supports_coupling_map(self):
+        """The plugin does not support coupling maps."""
+        return False
+
+    def run(self, unitary, **options):
+
+        # Runtime imports to avoid the overhead of these imports for
+        # plugin discovery and only use them if the plugin is run/used
+        from scipy.optimize import minimize
+        from qiskit.synthesis.unitary.aqc import AQC
+        from qiskit.synthesis.unitary.aqc.cnot_structures import make_cnot_network
+        from qiskit.synthesis.unitary.aqc.cnot_unit_circuit import CNOTUnitCircuit
+        from qiskit.synthesis.unitary.aqc.fast_gradient.fast_gradient import FastCNOTUnitObjective
+
+        num_qubits = round(math.log2(unitary.shape[0]))
+
+        config = options.get("config") or {}
+
+        network_layout = config.get("network_layout", "spin")
+        connectivity_type = config.get("connectivity_type", "full")
+        depth = config.get("depth", 0)
+
+        cnots = make_cnot_network(
+            num_qubits=num_qubits,
+            network_layout=network_layout,
+            connectivity_type=connectivity_type,
+            depth=depth,
+        )
+
+        default_optimizer = partial(minimize, args=(), method="L-BFGS-B", options={"maxiter": 1000})
+        optimizer = config.get("optimizer", default_optimizer)
+        seed = config.get("seed")
+        aqc = AQC(optimizer, seed)
+
+        approximate_circuit = CNOTUnitCircuit(num_qubits=num_qubits, cnots=cnots)
+        approximating_objective = FastCNOTUnitObjective(num_qubits=num_qubits, cnots=cnots)
+
+        initial_point = config.get("initial_point")
+        aqc.compile_unitary(
+            target_matrix=unitary,
+            approximate_circuit=approximate_circuit,
+            approximating_objective=approximating_objective,
+            initial_point=initial_point,
+        )
+
+        dag_circuit = circuit_to_dag(approximate_circuit)
+        return dag_circuit