lambdapdk 0.1.56__py3-none-any.whl → 0.2.0rc2__py3-none-any.whl

lambdapdk/ihp130/__init__.py

@@ -1,23 +1,18 @@
+from pathlib import Path
 
-import os
-import siliconcompiler
-from lambdapdk import register_data_source
+from lambdapdk import LambdaPDK, _LambdaPath
 
 
 pdk_rev = '0854e9bcd558b68c573149038b4c95706314e2f1'
 
 
-def register_ihp130_data_source(chip):
-    chip.register_source(
-        'ihp130',
-        path='git+https://github.com/IHP-GmbH/IHP-Open-PDK',
-        ref=pdk_rev)
+class _IHP130Path(_LambdaPath):
+    def __init__(self):
+        super().__init__()
+        self.set_dataroot("ihp130", "git+https://github.com/IHP-GmbH/IHP-Open-PDK", pdk_rev)
 
 
-####################################################
-# PDK Setup
-####################################################
-def setup():
+class IHP130PDK(LambdaPDK, _IHP130Path):
     '''
     130nm BiCMOS Open Source PDK, dedicated for Analog/Digital, Mixed Signal and RF Design
 
@@ -38,110 +33,80 @@ def setup():
 
     * https://github.com/IHP-GmbH/IHP-Open-PDK
     '''
-
-    foundry = 'Leibniz-Institut für innovative Mikroelektronik'
-    process = 'ihp130'
-    stackup = '5M2TL'
-
-    node = 130
-    # TODO: dummy numbers, only matter for cost estimation
-    wafersize = 300
-    hscribe = 0.1
-    vscribe = 0.1
-    edgemargin = 2
-
-    lpdkdir = os.path.join('lambdapdk', 'ihp130', 'base')
-
-    pdk = siliconcompiler.PDK(process, package='ihp130')
-    register_ihp130_data_source(pdk)
-    register_data_source(pdk)
-
-    # process name
-    pdk.set('pdk', process, 'foundry', foundry)
-    pdk.set('pdk', process, 'node', node)
-    pdk.set('pdk', process, 'version', pdk_rev)
-    pdk.set('pdk', process, 'stackup', stackup)
-    pdk.set('pdk', process, 'wafersize', wafersize)
-    pdk.set('pdk', process, 'edgemargin', edgemargin)
-    pdk.set('pdk', process, 'scribe', (hscribe, vscribe))
-
-    # APR Setup
-    # TODO: remove libtype
-    for tool in ('openroad', 'klayout', 'magic'):
-        # Add unithd for backwards compatibility
-        pdk.set('pdk', process, 'aprtech', tool, stackup, '9t', 'lef',
-                'ihp-sg13g2/libs.ref/sg13g2_stdcell/lef/sg13g2_tech.lef')
-
-    pdk.set('pdk', process, 'minlayer', stackup, 'Metal2')
-    pdk.set('pdk', process, 'maxlayer', stackup, 'Metal5')
-
-    # DRC Runsets
-#     pdk.set('pdk', process, 'drc', 'runset', 'magic', stackup, 'basic',
-#             pdkdir + '/setup/magic/sky130A.tech')
-
-    # LVS Runsets
-#     pdk.set('pdk', process, 'lvs', 'runset', 'netgen', stackup, 'basic',
-#             pdkdir + '/setup/netgen/lvs_setup.tcl')
-
-    # Layer map and display file
-    pdk.set('pdk', process, 'layermap', 'klayout', 'def', 'klayout', stackup,
-            'ihp-sg13g2/libs.tech/klayout/tech/sg13g2.lyt')
-    pdk.set('pdk', process, 'display', 'klayout', stackup,
-            'ihp-sg13g2/libs.tech/klayout/tech/sg13g2.lyp')
-
-    pdk.set('pdk', process, 'layermap', 'klayout', 'def', 'gds', stackup,
-            'ihp-sg13g2/libs.tech/klayout/tech/sg13g2.map')
-
-    # Openroad global routing grid derating
-    openroad_layer_adjustments = {
-        'Metal1': 0.25,
-        'Metal2': 0.25,
-        'Metal3': 0.25,
-        'Metal4': 0.25,
-        'Metal5': 0.25,
-        'TopMetal1': 0.00,
-        'TopMetal2': 0.00,
-    }
-    for layer, adj in openroad_layer_adjustments.items():
-        pdk.set('pdk', process, 'var', 'openroad', f'{layer}_adjustment', stackup, str(adj))
-
-    pdk.set('pdk', process, 'var', 'openroad', 'rclayer_signal', stackup, 'Metal2')
-    pdk.set('pdk', process, 'var', 'openroad', 'rclayer_clock', stackup, 'Metal5')
-
-    pdk.set('pdk', process, 'var', 'openroad', 'pin_layer_vertical', stackup, 'Metal2')
-    pdk.set('pdk', process, 'var', 'openroad', 'pin_layer_horizontal', stackup, 'Metal3')
-
-    # PEX
-    for corner in ["typical"]:
-        pdk.set('pdk', process, 'pexmodel', 'openroad', stackup, corner,
-                lpdkdir + '/pex/openroad/' + corner + '.tcl', package='lambdapdk')
-        pdk.set('pdk', process, 'pexmodel', 'openroad-openrcx', stackup, corner,
-                lpdkdir + '/pex/openroad/' + corner + '.rules', package='lambdapdk')
-
-    # DRC
-    drcs = {
-        "maximal": 'ihp-sg13g2/libs.tech/klayout/tech/drc/sg13g2_maximal.lydrc',
-        "minimal": 'ihp-sg13g2/libs.tech/klayout/tech/drc/sg13g2_minimal.lydrc'
-    }
-    for drc, runset in drcs.items():
-        pdk.set('pdk', process, 'drc', 'runset', 'klayout', stackup, drc, runset)
-
-        key = f'drc_params:{drc}'
-        pdk.add('pdk', process, 'var', 'klayout', stackup, key, 'in_gds=<input>')
-        pdk.add('pdk', process, 'var', 'klayout', stackup, key, 'cell=<topcell>')
-        pdk.add('pdk', process, 'var', 'klayout', stackup, key, 'report_file=<report>')
-
-    # Documentation
-    pdk.set('pdk', process, 'doc', 'overview',
-            'ihp-sg13g2/libs.doc/doc/SG13G2_os_process_spec.pdf')
-    pdk.set('pdk', process, 'doc', 'drc_rules',
-            'ihp-sg13g2/libs.doc/doc/SG13G2_os_layout_rules.pdf')
-
-    return pdk
-
-
-#########################
-if __name__ == "__main__":
-    pdk = setup()
-    pdk.write_manifest(f'{pdk.top()}.json')
-    pdk.check_filepaths()
+    def __init__(self):
+        super().__init__()
+        self.set_name("ihp130")
+
+        self.set_foundry("Leibniz-Institut für innovative Mikroelektronik")
+        self.set_version(pdk_rev)
+        self.set_node(130)
+        self.set_stackup("5M2TL")
+
+        pdk_path = Path("lambdapdk", "ihp130", "base")
+
+        # Docs
+        with self.active_dataroot("ihp130"):
+            self.add_doc("quickstart", "ihp-sg13g2/libs.doc/doc/SG13G2_os_process_spec.pdf")
+            self.add_doc("signoff", "ihp-sg13g2/libs.doc/doc/SG13G2_os_layout_rules.pdf")
+
+        with self.active_dataroot("ihp130"):
+            # APR Setup
+            with self.active_fileset("views.lef"):
+                self.add_file("ihp-sg13g2/libs.ref/sg13g2_stdcell/lef/sg13g2_tech.lef")
+                for tool in ('openroad', 'klayout', 'magic'):
+                    self.add_aprtechfileset(tool)
+
+            with self.active_fileset("layermap"):
+                self.add_file("ihp-sg13g2/libs.tech/klayout/tech/sg13g2.map", filetype="layermap")
+
+        self.set_aprroutinglayers(min="Metal2", max="Metal5")
+
+        # Klayout setup
+        with self.active_dataroot("ihp130"):
+            with self.active_fileset("klayout.techmap"):
+                self.add_file("ihp-sg13g2/libs.tech/klayout/tech/sg13g2.lyt", filetype="layermap")
+                self.add_file("ihp-sg13g2/libs.tech/klayout/tech/sg13g2.lyp", filetype="display")
+                self.add_layermapfileset("klayout", "def", "klayout")
+                self.add_displayfileset("klayout")
+            self.add_layermapfileset("klayout", "def", "gds", fileset="layermap")
+
+        # OpenROAD setup
+        self.set_openroad_rclayers(signal="Metal2", clock="Metal5")
+        self.add_openroad_pinlayers(vertical="Metal2", horizontal="Metal3")
+
+        # Openroad global routing grid derating
+        openroad_layer_adjustments = {
+            'Metal1': 0.25,
+            'Metal2': 0.25,
+            'Metal3': 0.25,
+            'Metal4': 0.25,
+            'Metal5': 0.25,
+            'TopMetal1': 0.00,
+            'TopMetal2': 0.00
+        }
+        for layer, adj in openroad_layer_adjustments.items():
+            self.set_openroad_globalroutingderating(layer, adj)
+
+        # PEX
+        with self.active_dataroot("lambdapdk"):
+            with self.active_fileset("openroad.pex"):
+                self.add_file(pdk_path / "pex" / "openroad" / "typical.tcl", filetype="tcl")
+                self.add_file(pdk_path / "pex" / "openroad" / "typical.rules", filetype="openrcx")
+
+                self.add_pexmodelfileset("openroad", "typical")
+                self.add_pexmodelfileset("openroad-openrcx", "typical")
+
+        # DRC
+        drcs = {
+            "maximal": 'ihp-sg13g2/libs.tech/klayout/tech/drc/sg13g2_maximal.lydrc',
+            "minimal": 'ihp-sg13g2/libs.tech/klayout/tech/drc/sg13g2_minimal.lydrc'
+        }
+        with self.active_dataroot("ihp130"):
+            for drc, runset in drcs.items():
+                with self.active_fileset(f"klayout.drc.{drc}"):
+                    self.add_file(runset, filetype="drc")
+                    self.add_runsetfileset("drc", "klayout", drc)
+
+                self.add_klayout_drcparam(drc, "in_gds=<input>")
+                self.add_klayout_drcparam(drc, "cell=<topcell>")
+                self.add_klayout_drcparam(drc, "report_file=<report>")

lambdapdk/ihp130/libs/sg13g2_io.py

@@ -1,57 +1,70 @@
-import os
-import siliconcompiler
-from lambdapdk import register_data_source
-from lambdapdk.ihp130 import register_ihp130_data_source
+from pathlib import Path
 
+from lambdapdk import LambdaLibrary
+from lambdapdk.ihp130 import IHP130PDK, _IHP130Path
 
-def setup():
+
+class _IHP130_IOLibrary(LambdaLibrary, _IHP130Path):
     '''
     IHP 130 IO Cells
     '''
-    libdir = "lambdapdk/ihp130/libs/sg13g2_io"
+    def __init__(self, voltage):
+        super().__init__()
+        self.set_name(f"sg13g2_io_{voltage}")
+
+        path_base = Path("lambdapdk", "ihp130", "libs", "sg13g2_io")
 
-    lib = siliconcompiler.Library('sg13g2_io', package='ihp130')
-    register_ihp130_data_source(lib)
-    register_data_source(lib)
+        self.add_asic_pdk(IHP130PDK())
 
-    # pdk
-    lib.set('option', 'pdk', 'ihp130')
+        with self.active_dataroot("ihp130"):
+            if voltage == "1p2V":
+                for corner_name, filename in [
+                        ('slow', 'sg13g2_io_slow_1p08V_3p0V_125C.lib'),
+                        ('typical', 'sg13g2_io_typ_1p2V_3p3V_25C.lib'),
+                        ('fast', 'sg13g2_io_fast_1p32V_3p6V_m40C.lib')]:
+                    with self.active_fileset(f"models.timing.{corner_name}.nldm"):
+                        self.add_file(f"ihp-sg13g2/libs.ref/sg13g2_io/lib/{filename}")
+                        self.add_asic_libcornerfileset(corner_name, "nldm")
+            else:
+                for corner_name, filename in [
+                        ('slow', 'sg13g2_io_slow_1p35V_3p0V_125C.lib'),
+                        ('typical', 'sg13g2_io_typ_1p5V_3p3V_25C.lib'),
+                        ('fast', 'sg13g2_io_fast_1p65V_3p6V_m40C.lib')]:
+                    with self.active_fileset(f"models.timing.{corner_name}.nldm"):
+                        self.add_file(f"ihp-sg13g2/libs.ref/sg13g2_io/lib/{filename}")
+                        self.add_asic_libcornerfileset(corner_name, "nldm")
 
-    lib.set('output', 'slow', 'nldm',
-            'ihp-sg13g2/libs.ref/sg13g2_io/lib/sg13g2_io_slow_1p08V_3p0V_125C.lib')
-    lib.set('output', 'typical', 'nldm',
-            'ihp-sg13g2/libs.ref/sg13g2_io/lib/sg13g2_io_typ_1p5V_3p3V_25C.lib')
-    lib.set('output', 'fast', 'nldm',
-            'ihp-sg13g2/libs.ref/sg13g2_io/lib/sg13g2_io_fast_1p32V_3p6V_m40C.lib')
+            with self.active_fileset("models.spice"):
+                self.add_file("ihp-sg13g2/libs.ref/sg13g2_io/spice/sg13g2_io.spi", filetype="spice")
 
-    for corner in ('slow', 'typical', 'fast'):
-        lib.set('output', corner, 'spice',
-                'ihp-sg13g2/libs.ref/sg13g2_io/spice/sg13g2_io.spi')
+        with self.active_dataroot("ihp130"):
+            with self.active_fileset("models.physical"):
+                self.add_file("ihp-sg13g2/libs.ref/sg13g2_io/lef/sg13g2_io.lef")
+                self.add_file("ihp-sg13g2/libs.ref/sg13g2_io/gds/sg13g2_io.gds")
+                self.add_asic_aprfileset()
 
-    lib.set('output', '5M2TL', 'lef', 'ihp-sg13g2/libs.ref/sg13g2_io/lef/sg13g2_io.lef')
-    lib.set('output', '5M2TL', 'cdl', 'ihp-sg13g2/libs.ref/sg13g2_io/cdl/sg13g2_io.cdl')
-    lib.add('output', '5M2TL', 'gds', 'ihp-sg13g2/libs.ref/sg13g2_io/gds/sg13g2_io.gds')
+            with self.active_fileset("models.lvs"):
+                self.add_file("ihp-sg13g2/libs.ref/sg13g2_io/cdl/sg13g2_io.cdl")
+                self.add_asic_aprfileset()
 
-    lib.set('asic', 'cells', 'filler', ['sg13g2_Filler200',
-                                        'sg13g2_Filler400',
-                                        'sg13g2_Filler1000',
-                                        'sg13g2_Filler2000',
-                                        'sg13g2_Filler4000',
-                                        'sg13g2_Filler10000'])
+        self.add_asic_celllist('filler', ['sg13g2_Filler200',
+                                          'sg13g2_Filler400',
+                                          'sg13g2_Filler1000',
+                                          'sg13g2_Filler2000',
+                                          'sg13g2_Filler4000',
+                                          'sg13g2_Filler10000'])
 
-    lib.set('output', 'blackbox', 'verilog',
-            os.path.join(libdir, 'blackbox', 'sg13g2_io.v'), package='lambdapdk')
+        with self.active_dataroot("lambdapdk"):
+            with self.active_fileset("models.blackbox"):
+                self.add_file(path_base / "blackbox" / "sg13g2_io.v")
+            self.add_yosys_blackbox_fileset("models.blackbox")
 
-    lambda_lib = siliconcompiler.Library('lambdalib_sg13g2_io', package='lambdapdk')
-    register_data_source(lambda_lib)
-    lambda_lib.add('option', 'ydir', os.path.join(libdir, 'lambda'))
-    lambda_lib.use(lib)
-    lambda_lib.set('asic', 'macrolib', lib.design)
 
-    return [lib, lambda_lib]
+class IHP130_IO_1p2(_IHP130_IOLibrary):
+    def __init__(self):
+        super().__init__("1p2")
 
 
-#########################
-if __name__ == "__main__":
-    for lib in setup(siliconcompiler.Chip('<lib>')):
-        lib.write_manifest(f'{lib.top()}.json')
+class IHP130_IO_1p5(_IHP130_IOLibrary):
+    def __init__(self):
+        super().__init__("1p5")

lambdapdk/ihp130/libs/sg13g2_sram.py

@@ -1,52 +1,94 @@
-from siliconcompiler import Chip, Library
-from lambdapdk import register_data_source
-from lambdapdk.ihp130 import register_ihp130_data_source
-
-
-def setup():
-    libs = []
-    stackup = '5M2TL'
-
-    for config in ('1024x64', '2048x64', '256x48', '256x64', '512x64', '64x64'):
-        mem_name = f'RM_IHPSG13_1P_{config}_c2_bm_bist'
-        lib = Library(mem_name, package='ihp130')
-        register_ihp130_data_source(lib)
-        register_data_source(lib)
-        path_base = 'ihp-sg13g2/libs.ref/sg13g2_sram'
-        lib.add('output', stackup, 'lef', f'{path_base}/lef/{mem_name}.lef')
-        lib.add('output', stackup, 'gds', f'{path_base}/gds/{mem_name}.gds')
-        lib.add('output', stackup, 'cdl', f'{path_base}/cdl/{mem_name}.cdl')
-
-        lib.add('output', 'typ', 'nldm', f'{path_base}/lib/{mem_name}_typ_1p20V_25C.lib')
-        lib.add('output', 'slow', 'nldm', f'{path_base}/lib/{mem_name}_slow_1p08V_125C.lib')
-        lib.add('output', 'fast', 'nldm', f'{path_base}/lib/{mem_name}_fast_1p32V_m55C.lib')
-
-        lib.add('output', 'rtl', 'verilog', f'{path_base}/verilog/{mem_name}.v')
-        lib.add('output', 'rtl', 'verilog',
-                f'{path_base}/verilog/RM_IHPSG13_1P_core_behavioral_bm_bist.v')
-
-        lib.set('option', 'file', 'openroad_pdngen',
-                'lambdapdk/ihp130/libs/sg13g2_sram/apr/openroad/pdngen.tcl',
-                package='lambdapdk')
-        lib.set('option', 'file', 'openroad_global_connect',
-                'lambdapdk/ihp130/libs/sg13g2_sram/apr/openroad/global_connect.tcl',
-                package='lambdapdk')
-
-        libs.append(lib)
-
-    lambda_lib = Library('lambdalib_sg13g2_sram', package='lambdapdk')
-    register_data_source(lambda_lib)
-    lambda_lib.add('option', 'ydir', 'lambdapdk/ihp130/libs/sg13g2_sram/lambda')
-    for lib in libs:
-        lambda_lib.use(lib)
-        lambda_lib.add('asic', 'macrolib', lib.design)
-
-    libs.append(lambda_lib)
-
-    return libs
-
-
-#########################
-if __name__ == "__main__":
-    for lib in setup(Chip('<lib>')):
-        lib.write_manifest(f'{lib.top()}.json')
+from pathlib import Path
+
+from lambdalib import LambalibTechLibrary
+from lambdapdk import LambdaLibrary, _LambdaPath
+from lambdapdk.ihp130 import IHP130PDK, _IHP130Path
+
+
+class _IHP130SRAMLibrary(LambdaLibrary, _IHP130Path):
+    def __init__(self, config):
+        super().__init__()
+        self.set_name(f'RM_IHPSG13_1P_{config}_c2_bm_bist')
+
+        self.add_asic_pdk(IHP130PDK())
+
+        path_base = Path("lambdapdk", "ihp130", "libs", "sg13g2_sram")
+
+        with self.active_dataroot("ihp130"):
+            with self.active_fileset("models.physical"):
+                self.add_file(f"ihp-sg13g2/libs.ref/sg13g2_sram/lef/{self.name}.lef")
+                self.add_file(f"ihp-sg13g2/libs.ref/sg13g2_sram/gds/{self.name}.gds")
+                self.add_asic_aprfileset()
+
+            with self.active_fileset("models.lvs"):
+                self.add_file(f"ihp-sg13g2/libs.ref/sg13g2_sram/cdl/{self.name}.cdl")
+                self.add_asic_aprfileset()
+
+            for corner_name, filename in [
+                    ('slow', f'{self.name}_slow_1p08V_125C.lib'),
+                    ('typical', f'{self.name}_typ_1p20V_25C.lib'),
+                    ('fast', f'{self.name}_fast_1p32V_m55C.lib')]:
+                with self.active_fileset(f"models.timing.nldm.{corner_name}"):
+                    self.add_file(f"ihp-sg13g2/libs.ref/sg13g2_sram/lib/{filename}")
+                    self.add_asic_libcornerfileset(corner_name, "nldm")
+
+            with self.active_fileset("rtl"):
+                self.add_file(f"ihp-sg13g2/libs.ref/sg13g2_sram/verilog/{self.name}.v")
+                self.add_file("ihp-sg13g2/libs.ref/sg13g2_sram/verilog/"
+                              "RM_IHPSG13_1P_core_behavioral_bm_bist.v")
+
+        with self.active_dataroot("lambdapdk"):
+            self.add_openroad_power_grid_file(path_base / "apr" / "openroad" / "pdngen.tcl")
+            self.add_openroad_global_connect_file(
+                path_base / "apr" / "openroad" / "global_connect.tcl")
+
+
+class IHP130_SRAM_1024x64(_IHP130SRAMLibrary):
+    def __init__(self):
+        super().__init__("1024x64")
+
+
+class IHP130_SRAM_2048x64(_IHP130SRAMLibrary):
+    def __init__(self):
+        super().__init__("2048x64")
+
+
+class IHP130_SRAM_256x48(_IHP130SRAMLibrary):
+    def __init__(self):
+        super().__init__("256x48")
+
+
+class IHP130_SRAM_256x64(_IHP130SRAMLibrary):
+    def __init__(self):
+        super().__init__("256x64")
+
+
+class IHP130_SRAM_512x64(_IHP130SRAMLibrary):
+    def __init__(self):
+        super().__init__("512x64")
+
+
+class IHP130_SRAM_64x64(_IHP130SRAMLibrary):
+    def __init__(self):
+        super().__init__("64x64")
+
+
+class IHP130Lambdalib_SinglePort(LambalibTechLibrary, _LambdaPath):
+    def __init__(self):
+        super().__init__("la_spram", [
+            IHP130_SRAM_1024x64,
+            IHP130_SRAM_2048x64,
+            IHP130_SRAM_256x48,
+            IHP130_SRAM_256x64,
+            IHP130_SRAM_512x64,
+            IHP130_SRAM_64x64])
+        self.set_name("ihp130_la_spram")
+
+        # version
+        self.set_version("v1")
+
+        lib_path = Path("lambdapdk", "ihp130", "libs", "sg13g2_sram")
+
+        with self.active_dataroot("lambdapdk"):
+            with self.active_fileset("rtl"):
+                self.add_file(lib_path / "lambda" / "la_spram.v")