lambdapdk 0.1.56__py3-none-any.whl → 0.2.0rc2__py3-none-any.whl

lambdapdk/__init__.py

@@ -1,101 +1,291 @@
 import os.path
-import siliconcompiler.package as sc_package
+from siliconcompiler.pathschema import PathSchema
 
+from siliconcompiler.package import PythonPathResolver
 
-__version__ = "0.1.56"
+from siliconcompiler.tools.klayout import KLayoutPDK
+from siliconcompiler.tools.openroad import OpenROADPDK
 
+from siliconcompiler.tools.yosys import YosysStdCellLibrary
+from siliconcompiler.tools.openroad import OpenROADStdCellLibrary
+from siliconcompiler.tools.bambu import BambuStdCellLibrary
+from siliconcompiler.tools.klayout import KLayoutLibrary
 
-def register_data_source(chip):
-    sc_package.register_python_data_source(
-        chip,
-        "lambdapdk",
-        "lambdapdk",
-        "https://github.com/siliconcompiler/lambdapdk/archive/refs/tags/",
-        alternative_ref=f"v{__version__}",
-        python_module_path_append=".."
-    )
+__version__ = "0.2.0-rc2"
 
 
-def setup_libs():
-    '''
-    Returns a list of libraries in lambdapdk
-    '''
+class _LambdaPath(PathSchema):
+    def __init__(self):
+        super().__init__()
+        PythonPathResolver.set_dataroot(
+            self,
+            "lambdapdk",
+            "lambdapdk",
+            "https://github.com/siliconcompiler/lambdapdk/archive/refs/tags/",
+            alternative_ref=f"v{__version__}",
+            python_module_path_append="..")
 
-    from lambdapdk.asap7.libs import asap7sc7p5t, fakeram7, fakeio7, fakekit7
-    from lambdapdk.freepdk45.libs import nangate45, fakeram45
-    from lambdapdk.sky130.libs import sky130sc, sky130io, sky130sram
-    from lambdapdk.gf180.libs import gf180mcu, gf180io, gf180sram
-    from lambdapdk.ihp130.libs import sg13g2_stdcell, sg13g2_sram, sg13g2_io
-    from lambdapdk.interposer.libs import bumps as interposer_bumps
-
-    all_libs = []
-    for lib_mod in [
-            asap7sc7p5t, fakeram7, fakeio7, fakekit7,
-            nangate45, fakeram45,
-            sky130sc, sky130io, sky130sram,
-            gf180mcu, gf180io, gf180sram,
-            sg13g2_stdcell, sg13g2_sram, sg13g2_io,
-            interposer_bumps]:
-        libs = lib_mod.setup()
-        if not isinstance(libs, (list, tuple)):
-            libs = [libs]
-        for lib in libs:
-            all_libs.append(lib)
-
-    return all_libs
-
-
-def setup_pdks():
-    '''
-    Returns a list of pdks in lambdapdk
-    '''
 
-    from lambdapdk import asap7, freepdk45, sky130, gf180, ihp130, interposer
+class LambdaPDK(KLayoutPDK, OpenROADPDK, _LambdaPath):
+    def __init__(self):
+        super().__init__()
 
-    all_pdks = []
-    for pdk_mod in [asap7, freepdk45, sky130, gf180, ihp130, interposer]:
-        pdks = pdk_mod.setup()
-        if not isinstance(pdks, (list, tuple)):
-            pdks = [pdks]
-        for pdk in pdks:
-            all_pdks.append(pdk)
 
-    return all_pdks
+class LambdaLibrary(YosysStdCellLibrary,
+                    OpenROADStdCellLibrary,
+                    KLayoutLibrary,
+                    BambuStdCellLibrary,
+                    _LambdaPath):
+    def __init__(self):
+        super().__init__()
 
 
-def setup():
+def get_pdks():
     '''
-    Returns a list of all pdks and libraries in lambdapdk
+    Returns a list of pdks in lambdapdk
     '''
 
-    return [
-        *setup_pdks(),
-        *setup_libs()
-    ]
-
-
-def get_pdks():
+    from lambdapdk.asap7 import ASAP7PDK
+    from lambdapdk.freepdk45 import FreePDK45PDK
+    from lambdapdk.sky130 import Sky130PDK
+    from lambdapdk.gf180 import GF180_3LM_1TM_6K_7t, \
+        GF180_3LM_1TM_6K_9t, \
+        GF180_3LM_1TM_9K_7t, \
+        GF180_3LM_1TM_9K_9t, \
+        GF180_3LM_1TM_11K_7t, \
+        GF180_3LM_1TM_11K_9t, \
+        GF180_3LM_1TM_30K_7t, \
+        GF180_3LM_1TM_30K_9t, \
+        GF180_4LM_1TM_6K_7t, \
+        GF180_4LM_1TM_6K_9t, \
+        GF180_4LM_1TM_9K_7t, \
+        GF180_4LM_1TM_9K_9t, \
+        GF180_4LM_1TM_11K_7t, \
+        GF180_4LM_1TM_11K_9t, \
+        GF180_4LM_1TM_30K_7t, \
+        GF180_4LM_1TM_30K_9t, \
+        GF180_5LM_1TM_9K_7t, \
+        GF180_5LM_1TM_9K_9t, \
+        GF180_5LM_1TM_11K_7t, \
+        GF180_5LM_1TM_11K_9t, \
+        GF180_6LM_1TM_9K_7t, \
+        GF180_6LM_1TM_9K_9t
+    from lambdapdk.ihp130 import IHP130PDK
+    from lambdapdk.interposer import Interposer_3ML_0400, \
+        Interposer_3ML_0800, \
+        Interposer_3ML_2000, \
+        Interposer_3ML_0400_2000, \
+        Interposer_4ML_0400, \
+        Interposer_4ML_0800, \
+        Interposer_4ML_2000, \
+        Interposer_4ML_0400_2000, \
+        Interposer_5ML_0400, \
+        Interposer_5ML_0800, \
+        Interposer_5ML_2000, \
+        Interposer_5ML_0400_2000
+
+    return set([
+        ASAP7PDK(),
+        FreePDK45PDK(),
+        Sky130PDK(),
+        IHP130PDK(),
+        GF180_3LM_1TM_6K_7t(),
+        GF180_3LM_1TM_6K_9t(),
+        GF180_3LM_1TM_9K_7t(),
+        GF180_3LM_1TM_9K_9t(),
+        GF180_3LM_1TM_11K_7t(),
+        GF180_3LM_1TM_11K_9t(),
+        GF180_3LM_1TM_30K_7t(),
+        GF180_3LM_1TM_30K_9t(),
+        GF180_4LM_1TM_6K_7t(),
+        GF180_4LM_1TM_6K_9t(),
+        GF180_4LM_1TM_9K_7t(),
+        GF180_4LM_1TM_9K_9t(),
+        GF180_4LM_1TM_11K_7t(),
+        GF180_4LM_1TM_11K_9t(),
+        GF180_4LM_1TM_30K_7t(),
+        GF180_4LM_1TM_30K_9t(),
+        GF180_5LM_1TM_9K_7t(),
+        GF180_5LM_1TM_9K_9t(),
+        GF180_5LM_1TM_11K_7t(),
+        GF180_5LM_1TM_11K_9t(),
+        GF180_6LM_1TM_9K_7t(),
+        GF180_6LM_1TM_9K_9t(),
+        Interposer_3ML_0400(),
+        Interposer_3ML_0800(),
+        Interposer_3ML_2000(),
+        Interposer_3ML_0400_2000(),
+        Interposer_4ML_0400(),
+        Interposer_4ML_0800(),
+        Interposer_4ML_2000(),
+        Interposer_4ML_0400_2000(),
+        Interposer_5ML_0400(),
+        Interposer_5ML_0800(),
+        Interposer_5ML_2000(),
+        Interposer_5ML_0400_2000()
+    ])
+
+
+def get_pdk_names():
     '''
-    Returns a list of pdk names in lambdapdk
+    Returns a list of pdks in lambdapdk
     '''
 
-    all_pdks = []
-    for pdk in setup_pdks():
-        all_pdks.append(pdk.design)
-
-    return set(all_pdks)
+    return set([pdk.name for pdk in get_pdks()])
 
 
 def get_libs():
     '''
-    Returns a list of libraries names in lambdapdk
+    Returns a list of libraries in lambdapdk
     '''
 
-    all_libs = []
-    for lib in setup_libs():
-        all_libs.append(lib.design)
+    from lambdapdk.asap7.libs.asap7sc7p5t import ASAP7SC7p5RVT, ASAP7SC7p5SLVT, ASAP7SC7p5LVT
+    from lambdapdk.asap7.libs.fakeio7 import FakeIO7Library
+    from lambdapdk.asap7.libs.fakekit7 import FakeKit7Library
+    from lambdapdk.asap7.libs.fakeram7 import \
+        FakeRAM7_dp_64x32, \
+        FakeRAM7_sp_64x32, \
+        FakeRAM7_dp_128x32, \
+        FakeRAM7_sp_128x32, \
+        FakeRAM7_dp_256x32, \
+        FakeRAM7_sp_256x32, \
+        FakeRAM7_dp_256x64, \
+        FakeRAM7_sp_256x64, \
+        FakeRAM7_dp_512x32, \
+        FakeRAM7_sp_512x32, \
+        FakeRAM7_dp_512x64, \
+        FakeRAM7_sp_512x64, \
+        FakeRAM7_dp_512x128, \
+        FakeRAM7_sp_512x128, \
+        FakeRAM7_dp_1024x32, \
+        FakeRAM7_sp_1024x32, \
+        FakeRAM7_dp_1024x64, \
+        FakeRAM7_sp_1024x64, \
+        FakeRAM7_dp_2048x32, \
+        FakeRAM7_sp_2048x32, \
+        FakeRAM7_dp_2048x64, \
+        FakeRAM7_sp_2048x64, \
+        FakeRAM7_dp_4096x32, \
+        FakeRAM7_sp_4096x32, \
+        FakeRAM7_dp_4096x64, \
+        FakeRAM7_sp_4096x64, \
+        FakeRAM7_dp_8192x32, \
+        FakeRAM7_sp_8192x32, \
+        FakeRAM7_dp_8192x64, \
+        FakeRAM7_sp_8192x64, \
+        FakeRAM7Lambdalib_SinglePort, \
+        FakeRAM7Lambdalib_DoublePort
+    from lambdapdk.freepdk45.libs.nangate45 import Nangate45
+    from lambdapdk.freepdk45.libs.fakeram45 import \
+        FakeRAM45_64x32, \
+        FakeRAM45_128x32, \
+        FakeRAM45_256x32, \
+        FakeRAM45_256x64, \
+        FakeRAM45_512x32, \
+        FakeRAM45_512x64, \
+        FakeRAM45Lambdalib_SinglePort
+    from lambdapdk.gf180.libs.gf180io import GF180_IO_3LM, GF180_IO_4LM, GF180_IO_5LM
+    from lambdapdk.gf180.libs.gf180mcu import GF180_MCU_7T_3LMLibrary, \
+        GF180_MCU_7T_4LMLibrary, \
+        GF180_MCU_7T_5LMLibrary, \
+        GF180_MCU_7T_6LMLibrary, \
+        GF180_MCU_9T_3LMLibrary, \
+        GF180_MCU_9T_4LMLibrary, \
+        GF180_MCU_9T_5LMLibrary, \
+        GF180_MCU_9T_6LMLibrary
+    from lambdapdk.gf180.libs.gf180sram import GF180_SRAM_64x8, \
+        GF180_SRAM_128x8, \
+        GF180_SRAM_256x8, \
+        GF180_SRAM_512x8, \
+        GF180Lambdalib_SinglePort
+    from lambdapdk.ihp130.libs.sg13g2_io import IHP130_IO_1p2, IHP130_IO_1p5
+    from lambdapdk.ihp130.libs.sg13g2_sram import \
+        IHP130_SRAM_1024x64, IHP130_SRAM_2048x64, \
+        IHP130_SRAM_256x48, IHP130_SRAM_256x64, \
+        IHP130_SRAM_512x64, IHP130_SRAM_64x64, \
+        IHP130Lambdalib_SinglePort
+    from lambdapdk.ihp130.libs.sg13g2_stdcell import IHP130StdCell_1p2, IHP130StdCell_1p5
+    from lambdapdk.interposer.libs.bumps import BumpLibrary
+    from lambdapdk.sky130.libs.sky130io import Sky130_IOLibrary
+    from lambdapdk.sky130.libs.sky130sc import Sky130_SCHDLibrary, Sky130_SCHDLLLibrary
+    from lambdapdk.sky130.libs.sky130sram import Sky130_SRAM_64x256, Sky130Lambdalib_SinglePort
+
+    return set([
+        ASAP7SC7p5RVT(), ASAP7SC7p5SLVT(), ASAP7SC7p5LVT(),
+        FakeIO7Library(), FakeKit7Library(),
+        FakeRAM7_dp_64x32(),
+        FakeRAM7_sp_64x32(),
+        FakeRAM7_dp_128x32(),
+        FakeRAM7_sp_128x32(),
+        FakeRAM7_dp_256x32(),
+        FakeRAM7_sp_256x32(),
+        FakeRAM7_dp_256x64(),
+        FakeRAM7_sp_256x64(),
+        FakeRAM7_dp_512x32(),
+        FakeRAM7_sp_512x32(),
+        FakeRAM7_dp_512x64(),
+        FakeRAM7_sp_512x64(),
+        FakeRAM7_dp_512x128(),
+        FakeRAM7_sp_512x128(),
+        FakeRAM7_dp_1024x32(),
+        FakeRAM7_sp_1024x32(),
+        FakeRAM7_dp_1024x64(),
+        FakeRAM7_sp_1024x64(),
+        FakeRAM7_dp_2048x32(),
+        FakeRAM7_sp_2048x32(),
+        FakeRAM7_dp_2048x64(),
+        FakeRAM7_sp_2048x64(),
+        FakeRAM7_dp_4096x32(),
+        FakeRAM7_sp_4096x32(),
+        FakeRAM7_dp_4096x64(),
+        FakeRAM7_sp_4096x64(),
+        FakeRAM7_dp_8192x32(),
+        FakeRAM7_sp_8192x32(),
+        FakeRAM7_dp_8192x64(),
+        FakeRAM7_sp_8192x64(),
+        FakeRAM7Lambdalib_SinglePort(),
+        FakeRAM7Lambdalib_DoublePort(),
+        Nangate45(),
+        FakeRAM45_64x32(),
+        FakeRAM45_128x32(),
+        FakeRAM45_256x32(),
+        FakeRAM45_256x64(),
+        FakeRAM45_512x32(),
+        FakeRAM45_512x64(),
+        FakeRAM45Lambdalib_SinglePort(),
+        GF180_IO_3LM(), GF180_IO_4LM(), GF180_IO_5LM(),
+        GF180_MCU_7T_3LMLibrary(),
+        GF180_MCU_7T_4LMLibrary(),
+        GF180_MCU_7T_5LMLibrary(),
+        GF180_MCU_7T_6LMLibrary(),
+        GF180_MCU_9T_3LMLibrary(),
+        GF180_MCU_9T_4LMLibrary(),
+        GF180_MCU_9T_5LMLibrary(),
+        GF180_MCU_9T_6LMLibrary(),
+        GF180_SRAM_64x8(),
+        GF180_SRAM_128x8(),
+        GF180_SRAM_256x8(),
+        GF180_SRAM_512x8(),
+        GF180Lambdalib_SinglePort(),
+        IHP130_IO_1p2(), IHP130_IO_1p5(),
+        IHP130_SRAM_1024x64(), IHP130_SRAM_2048x64(),
+        IHP130_SRAM_256x48(), IHP130_SRAM_256x64(),
+        IHP130_SRAM_512x64(), IHP130_SRAM_64x64(),
+        IHP130Lambdalib_SinglePort(),
+        IHP130StdCell_1p2(), IHP130StdCell_1p5(),
+        BumpLibrary(),
+        Sky130_IOLibrary(),
+        Sky130_SCHDLibrary(), Sky130_SCHDLLLibrary(),
+        Sky130_SRAM_64x256(), Sky130Lambdalib_SinglePort()
+    ])
+
+
+def get_lib_names():
+    '''
+    Returns a list of libraries names in lambdapdk
+    '''
 
-    return set(all_libs)
+    return set([lib.name for lib in get_libs()])
 
 
 def get_docs_codeurl(file=None):
@@ -118,44 +308,3 @@ def get_docs_codeurl(file=None):
             return None
 
     return f"{base_url}/{file}"
-
-
-def get_docs_pdks():
-    from lambdapdk import asap7, freepdk45, sky130, gf180, ihp130, interposer
-
-    return [
-        (asap7, "asap7"),
-        (freepdk45, "freepdk45"),
-        (sky130, "skywater130"),
-        (gf180, "gf180"),
-        (ihp130, "ihp130"),
-        (interposer, "interposer")
-    ]
-
-
-def get_docs_libraries():
-    from lambdapdk.asap7.libs import asap7sc7p5t, fakeram7, fakeio7, fakekit7
-    from lambdapdk.freepdk45.libs import nangate45, fakeram45
-    from lambdapdk.sky130.libs import sky130sc, sky130io, sky130sram
-    from lambdapdk.gf180.libs import gf180mcu, gf180io, gf180sram
-    from lambdapdk.ihp130.libs import sg13g2_stdcell, sg13g2_sram, sg13g2_io
-    from lambdapdk.interposer.libs import bumps as interposer_bumps
-
-    return [
-        (asap7sc7p5t, "asap7sc7p5t"),
-        (fakeram7, "fakeram7"),
-        (fakeio7, "fakeio7"),
-        (fakekit7, "fakekit7"),
-        (nangate45, "nangate45"),
-        (fakeram45, "fakeram45"),
-        (sky130sc, "sky130sc"),
-        (sky130io, "sky130io"),
-        (sky130sram, "sky130sram"),
-        (gf180mcu, "gf180mcu"),
-        (gf180io, "gf180io"),
-        (gf180sram, "gf180sram"),
-        (sg13g2_stdcell, "sg13g2_stdcell"),
-        (sg13g2_sram, "sg13g2_sram"),
-        (sg13g2_io, "sg13g2_io"),
-        (interposer_bumps, "interposer_bumps")
-    ]

lambdapdk/asap7/__init__.py

@@ -1,12 +1,9 @@
-import os
-import siliconcompiler
-from lambdapdk import register_data_source
+from pathlib import Path
 
+from lambdapdk import LambdaPDK
 
-####################################################
-# PDK Setup
-####################################################
-def setup():
+
+class ASAP7PDK(LambdaPDK):
     '''
     The asap7 PDK was developed at ASU in collaboration with ARM Research.
     With funding from the DARPA IDEA program, the PDK was released
@@ -43,92 +40,72 @@ def setup():
        Work in progress (not ready for use)
     '''
 
-    foundry = 'virtual'
-    process = 'asap7'
-    node = 7
-    rev = 'r1p7'
-    stackup = '10M'
-    wafersize = 300
-    libtype = '7p5t'
-    pdkdir = os.path.join('lambdapdk', 'asap7', 'base')
-
-    pdk = siliconcompiler.PDK(process, package='lambdapdk')
-    register_data_source(pdk)
-
-    # process name
-    pdk.set('pdk', process, 'foundry', foundry)
-    pdk.set('pdk', process, 'node', node)
-    pdk.set('pdk', process, 'wafersize', wafersize)
-    pdk.set('pdk', process, 'version', rev)
-    pdk.set('pdk', process, 'stackup', stackup)
-
-    # APR tech file
-    for tool in ('openroad', 'klayout', 'magic'):
-        pdk.set('pdk', process, 'aprtech', tool, stackup, libtype, 'lef',
-                pdkdir + '/apr/asap7_tech.lef')
-
-    pdk.set('pdk', process, 'minlayer', stackup, 'M2')
-    pdk.set('pdk', process, 'maxlayer', stackup, 'M7')
-
-    # Device models
-    pdk.set('pdk', process, 'devmodel', 'xyce', 'hspice', stackup,
-            pdkdir + '/spice/hspice/7nm.lib')
-
-    # Klayout setup file
-    pdk.set('pdk', process, 'layermap', 'klayout', 'def', 'klayout', stackup,
-            pdkdir + '/setup/klayout/asap7.lyt')
-    pdk.set('pdk', process, 'layermap', 'klayout', 'def', 'gds', stackup,
-            pdkdir + '/apr/asap7.layermap')
-
-    pdk.set('pdk', process, 'display', 'klayout', stackup,
-            pdkdir + '/setup/klayout/asap7.lyp')
-
-    # Openroad global routing grid derating
-    openroad_layer_adjustments = {
-        'M1': 0.25,
-        'M2': 0.25,
-        'M3': 0.25,
-        'M4': 0.25,
-        'M5': 0.25,
-        'M6': 0.25,
-        'M7': 0.25,
-        'M8': 0.25,
-        'M9': 0.25,
-        'Pad': 1.0
-    }
-    for layer, adj in openroad_layer_adjustments.items():
-        pdk.set('pdk', process, 'var', 'openroad', f'{layer}_adjustment', stackup, str(adj))
-
-    pdk.set('pdk', process, 'var', 'openroad', 'rclayer_signal', stackup, 'M3')
-    pdk.set('pdk', process, 'var', 'openroad', 'rclayer_clock', stackup, 'M3')
-
-    pdk.set('pdk', process, 'var', 'openroad', 'pin_layer_vertical', stackup, 'M5')
-    pdk.set('pdk', process, 'var', 'openroad', 'pin_layer_horizontal', stackup, 'M4')
-
-    # PEX
-    pdk.set('pdk', process, 'pexmodel', 'openroad', stackup, 'typical',
-            pdkdir + '/pex/openroad/typical.tcl')
-    pdk.set('pdk', process, 'pexmodel', 'openroad-openrcx', stackup, 'typical',
-            pdkdir + '/pex/openroad/typical.rules')
-
-    # Relaxed routing rules
-    pdk.set('pdk', process, 'file', 'openroad', 'relax_routing_rules', stackup,
-            pdkdir + '/apr/openroad_relaxed_rules.tcl')
-
-    # Hide the DIEAREA layer 235/*.
-    pdk.add('pdk', process, 'var', 'klayout', 'hide_layers', stackup, '235/0')
-    pdk.add('pdk', process, 'var', 'klayout', 'hide_layers', stackup, '235/5')
-    # Hide boundary layer
-    pdk.add('pdk', process, 'var', 'klayout', 'hide_layers', stackup, '100/0')
-    # Hide vt layers
-    pdk.add('pdk', process, 'var', 'klayout', 'hide_layers', stackup, '97/0')
-    pdk.add('pdk', process, 'var', 'klayout', 'hide_layers', stackup, '98/0')
-
-    return pdk
-
-
-#########################
-if __name__ == "__main__":
-    pdk = setup()
-    register_data_source(pdk)
-    pdk.check_filepaths()
+    def __init__(self):
+        super().__init__()
+        self.set_name("asap7")
+
+        pdk_path = Path("lambdapdk", "asap7", "base")
+
+        self.set_foundry("virtual")
+        self.set_version("r1p7")
+        self.set_node(7)
+        self.set_stackup("10M")
+        self.set_wafersize(300)
+        self.set_scribewidth(0.1, 0.1)
+        self.set_edgemargin(2)
+        self.set_defectdensity(1.25)
+
+        with self.active_dataroot("lambdapdk"):
+            # APR Setup
+            with self.active_fileset("views.lef"):
+                self.add_file(pdk_path / "apr" / "asap7_tech.lef")
+                for tool in ('openroad', 'klayout', 'magic'):
+                    self.add_aprtechfileset(tool)
+
+            with self.active_fileset("layermap"):
+                self.add_file(pdk_path / "apr" / "asap7.layermap", filetype="layermap")
+
+            with self.active_fileset("models.spice"):
+                self.add_file(pdk_path / "spice" / "hspice" / "7nm.lib", filetype="library")
+                self.add_devmodelfileset("xyce", "spice")
+
+            # Klayout setup
+            with self.active_fileset("klayout.techmap"):
+                self.add_file(pdk_path / "setup" / "klayout" / "asap7.lyt", filetype="layermap")
+                self.add_file(pdk_path / "setup" / "klayout" / "asap7.lyp", filetype="display")
+                self.add_layermapfileset("klayout", "def", "klayout")
+                self.add_displayfileset("klayout")
+            self.add_layermapfileset("klayout", "def", "gds", fileset="layermap")
+
+            self.set_aprroutinglayers(min="M2", max="M7")
+
+            # OpenROAD setup
+            self.set_openroad_rclayers(signal="M3", clock="M3")
+
+            # Openroad global routing grid derating
+            for layer, derate in [
+                    ('M1', 0.25),
+                    ('M2', 0.25),
+                    ('M3', 0.25),
+                    ('M4', 0.25),
+                    ('M5', 0.25),
+                    ('M6', 0.25),
+                    ('M7', 0.25),
+                    ('M8', 0.25),
+                    ('M9', 0.25),
+                    ('Pad', 0.25)]:
+                self.set_openroad_globalroutingderating(layer, derate)
+
+            self.add_openroad_pinlayers(vertical="M5", horizontal="M4")
+
+            with self.active_fileset("openroad.routing"):
+                # Relaxed routing rules
+                self.add_file(pdk_path / "apr" / "openroad_relaxed_rules.tcl", filetype="tcl")
+
+            # PEX
+            with self.active_fileset("openroad.pex"):
+                self.add_file(pdk_path / "pex" / "openroad" / "typical.tcl", filetype="tcl")
+                self.add_file(pdk_path / "pex" / "openroad" / "typical.rules", filetype="openrcx")
+
+                self.add_pexmodelfileset("openroad", "typical")
+                self.add_pexmodelfileset("openroad-openrcx", "typical")