lambdapdk 0.1.56__py3-none-any.whl → 0.2.0rc2__py3-none-any.whl

lambdapdk/gf180/libs/gf180mcu.py

@@ -1,163 +1,209 @@
-import siliconcompiler
-from lambdapdk import register_data_source
-
-
-def setup():
+from pathlib import Path
+
+from lambdapdk import LambdaLibrary
+from lambdapdk.gf180 import GF180_3LM_1TM_6K_7t, \
+    GF180_3LM_1TM_6K_9t, \
+    GF180_3LM_1TM_9K_7t, \
+    GF180_3LM_1TM_9K_9t, \
+    GF180_3LM_1TM_11K_7t, \
+    GF180_3LM_1TM_11K_9t, \
+    GF180_3LM_1TM_30K_7t, \
+    GF180_3LM_1TM_30K_9t, \
+    GF180_4LM_1TM_6K_7t, \
+    GF180_4LM_1TM_6K_9t, \
+    GF180_4LM_1TM_9K_7t, \
+    GF180_4LM_1TM_9K_9t, \
+    GF180_4LM_1TM_11K_7t, \
+    GF180_4LM_1TM_11K_9t, \
+    GF180_4LM_1TM_30K_7t, \
+    GF180_4LM_1TM_30K_9t, \
+    GF180_5LM_1TM_9K_7t, \
+    GF180_5LM_1TM_9K_9t, \
+    GF180_5LM_1TM_11K_7t, \
+    GF180_5LM_1TM_11K_9t, \
+    GF180_6LM_1TM_9K_7t, \
+    GF180_6LM_1TM_9K_9t
+
+
+class _GF180_MCULibrary(LambdaLibrary):
     '''
-    Skywater130 standard cell library.
+    GF180 standard cell library.
     '''
-
-    libs = []
-    for libtype, sites in (("7t", "GF018hv5v_mcu_sc7"),
-                           ("9t", "GF018hv5v_green_sc9")):
-        libname = f'gf180mcu_fd_sc_mcu{libtype}5v0'
-
-        libdir = f"lambdapdk/gf180/libs/{libname}/"
-
-        lib = siliconcompiler.Library(libname, package='lambdapdk')
-        register_data_source(lib)
-
-        # pdk
-        lib.set('option', 'pdk', 'gf180')
-
-        # footprint/type/sites
-        lib.set('asic', 'libarch', libtype)
-        lib.set('asic', 'site', libtype, sites)
-
-        # model files
-        lib.add('output', 'slow', 'nldm',
-                libdir + f'/nldm/gf180mcu_fd_sc_mcu{libtype}5v0__ss_125C_4v50.lib.gz')
-        lib.add('output', 'typical', 'nldm',
-                libdir + f'/nldm/gf180mcu_fd_sc_mcu{libtype}5v0__tt_025C_5v00.lib.gz')
-        lib.add('output', 'fast', 'nldm',
-                libdir + f'/nldm/gf180mcu_fd_sc_mcu{libtype}5v0__ff_n40C_5v50.lib.gz')
-
-        for corner in ('slow', 'typical', 'fast'):
-            lib.add('output', corner, 'spice',
-                    libdir + f'/spice/gf180mcu_fd_sc_mcu{libtype}5v0.spice')
-
-        for stackup in ("3LM_1TM_6K",
-                        "3LM_1TM_9K",
-                        "3LM_1TM_11K",
-                        "3LM_1TM_30K",
-                        "4LM_1TM_6K",
-                        "4LM_1TM_9K",
-                        "4LM_1TM_11K",
-                        "4LM_1TM_30K",
-                        "5LM_1TM_9K",
-                        "5LM_1TM_11K",
-                        "6LM_1TM_9K"):
-            lib.add('output', stackup, 'lef', libdir + f'/lef/gf180mcu_fd_sc_mcu{libtype}5v0.lef')
-            lib.add('output', stackup, 'cdl', libdir + f'/cdl/gf180mcu_fd_sc_mcu{libtype}5v0.cdl')
-            gds_dir = stackup[0:3]
-            if gds_dir == "6LM":
-                gds_dir = "5LM"
-            lib.add('output', stackup, 'gds',
-                    libdir + f'/gds/{gds_dir}/gf180mcu_fd_sc_mcu{libtype}5v0.gds.gz')
+    def __init__(self, libtype, stackup):
+        super().__init__()
+        self.set_name(f"gf180mcu_fd_sc_mcu{libtype}5v0_{stackup}")
+
+        if libtype == "7t":
+            if stackup == "3LM":
+                self.add_asic_pdk(GF180_3LM_1TM_6K_7t(), default=False)
+                self.add_asic_pdk(GF180_3LM_1TM_9K_7t(), default=False)
+                self.add_asic_pdk(GF180_3LM_1TM_11K_7t(), default=False)
+                self.add_asic_pdk(GF180_3LM_1TM_30K_7t(), default=False)
+            elif stackup == "4LM":
+                self.add_asic_pdk(GF180_4LM_1TM_6K_7t(), default=False)
+                self.add_asic_pdk(GF180_4LM_1TM_9K_7t(), default=False)
+                self.add_asic_pdk(GF180_4LM_1TM_11K_7t(), default=False)
+                self.add_asic_pdk(GF180_4LM_1TM_30K_7t(), default=False)
+            elif stackup == "5LM":
+                self.add_asic_pdk(GF180_5LM_1TM_9K_7t(), default=False)
+                self.add_asic_pdk(GF180_5LM_1TM_11K_7t(), default=False)
+            elif stackup == "6LM":
+                self.add_asic_pdk(GF180_6LM_1TM_9K_7t())
+            else:
+                raise ValueError(f"{stackup} is not supported")
+
+            self.add_asic_site("GF018hv5v_mcu_sc7")
+        elif libtype == "9t":
+            if stackup == "3LM":
+                self.add_asic_pdk(GF180_3LM_1TM_6K_9t(), default=False)
+                self.add_asic_pdk(GF180_3LM_1TM_9K_9t(), default=False)
+                self.add_asic_pdk(GF180_3LM_1TM_11K_9t(), default=False)
+                self.add_asic_pdk(GF180_3LM_1TM_30K_9t(), default=False)
+            elif stackup == "4LM":
+                self.add_asic_pdk(GF180_4LM_1TM_6K_9t(), default=False)
+                self.add_asic_pdk(GF180_4LM_1TM_9K_9t(), default=False)
+                self.add_asic_pdk(GF180_4LM_1TM_11K_9t(), default=False)
+                self.add_asic_pdk(GF180_4LM_1TM_30K_9t(), default=False)
+            elif stackup == "5LM":
+                self.add_asic_pdk(GF180_5LM_1TM_9K_9t(), default=False)
+                self.add_asic_pdk(GF180_5LM_1TM_11K_9t(), default=False)
+            elif stackup == "6LM":
+                self.add_asic_pdk(GF180_6LM_1TM_9K_9t())
+            else:
+                raise ValueError(f"{stackup} is not supported")
+
+            self.add_asic_site("GF018hv5v_green_sc9")
+        else:
+            raise ValueError(f"{libtype} is not supported")
+
+        lib_path = Path("lambdapdk", "gf180", "libs", f"gf180mcu_fd_sc_mcu{libtype}5v0")
+
+        with self.active_dataroot("lambdapdk"):
+            for corner_name, filename in [
+                    ('slow', f'gf180mcu_fd_sc_mcu{libtype}5v0__ss_125C_4v50.lib.gz'),
+                    ('typical', f'gf180mcu_fd_sc_mcu{libtype}5v0__tt_025C_5v00.lib.gz'),
+                    ('fast', f'gf180mcu_fd_sc_mcu{libtype}5v0__ff_n40C_5v50.lib.gz')]:
+                with self.active_fileset(f"models.timing.{corner_name}.nldm"):
+                    self.add_file(lib_path / "nldm" / filename)
+                    self.add_asic_libcornerfileset(corner_name, "nldm")
+
+            with self.active_fileset("models.spice"):
+                self.add_file(lib_path / "spice" / f"gf180mcu_fd_sc_mcu{libtype}5v0.spice")
+
+        with self.active_dataroot("lambdapdk"):
+            with self.active_fileset("models.physical"):
+                self.add_file(lib_path / "lef" / f"gf180mcu_fd_sc_mcu{libtype}5v0.lef")
+                gds_dir = stackup[0:3]
+                if gds_dir == "6LM":
+                    gds_dir = "5LM"
+                self.add_file(lib_path / "gds" / gds_dir / f"gf180mcu_fd_sc_mcu{libtype}5v0.gds.gz")
+                self.add_asic_aprfileset()
+
+            with self.active_fileset("models.lvs"):
+                self.add_file(lib_path / "cdl" / f"gf180mcu_fd_sc_mcu{libtype}5v0.cdl")
+                self.add_asic_aprfileset()
 
         # antenna cells
-        lib.add('asic', 'cells', 'antenna', f'gf180mcu_fd_sc_mcu{libtype}5v0__antenna')
+        self.add_asic_celllist('antenna', f'gf180mcu_fd_sc_mcu{libtype}5v0__antenna')
 
         # clock buffers
         for size in (1, 2, 3, 4, 8, 12, 16, 20):
-            lib.add('asic', 'cells', 'clkbuf', f'gf180mcu_fd_sc_mcu{libtype}5v0__clkbuf_{size}')
+            self.add_asic_celllist('clkbuf', f'gf180mcu_fd_sc_mcu{libtype}5v0__clkbuf_{size}')
 
         # hold cells
         for variant in ('a', 'b', 'c', 'd'):
             for size in (1, 2, 4):
-                lib.add('asic', 'cells', 'hold',
-                        f'gf180mcu_fd_sc_mcu{libtype}5v0__dly{variant}_{size}')
+                self.add_asic_celllist(
+                    'hold',
+                    f'gf180mcu_fd_sc_mcu{libtype}5v0__dly{variant}_{size}')
 
         # Decoupling
         for size in (4, 8, 16, 32, 64):
-            lib.add('asic', 'cells', 'decap', f'gf180mcu_fd_sc_mcu{libtype}5v0__fillcap_{size}')
+            self.add_asic_celllist('decap', f'gf180mcu_fd_sc_mcu{libtype}5v0__fillcap_{size}')
 
         # filler
         for size in (1, 2, 4, 8, 16, 32, 64):
-            lib.add('asic', 'cells', 'filler', f'gf180mcu_fd_sc_mcu{libtype}5v0__fill_{size}')
+            self.add_asic_celllist('filler', f'gf180mcu_fd_sc_mcu{libtype}5v0__fill_{size}')
 
         # Tapcell
-        lib.add('asic', 'cells', 'tap', f'gf180mcu_fd_sc_mcu{libtype}5v0__filltie')
+        self.add_asic_celllist('tap', f'gf180mcu_fd_sc_mcu{libtype}5v0__filltie')
 
         # Endcap
-        lib.add('asic', 'cells', 'endcap', f'gf180mcu_fd_sc_mcu{libtype}5v0__endcap')
+        self.add_asic_celllist('endcap', f'gf180mcu_fd_sc_mcu{libtype}5v0__endcap')
 
         # Dont use
-        lib.add('asic', 'cells', 'dontuse', '*_1')
+        self.add_asic_celllist('dontuse', '*_1')
 
         # tie cells
-        lib.add('asic', 'cells', 'tie', [f'gf180mcu_fd_sc_mcu{libtype}5v0__tieh',
-                                         f'gf180mcu_fd_sc_mcu{libtype}5v0__tiel'])
-
-        # Defaults for OpenROAD tool variables
-        lib.set('option', 'var', 'openroad_place_density', '0.50')
-        lib.set('option', 'var', 'openroad_pad_global_place', '0')
-        lib.set('option', 'var', 'openroad_pad_detail_place', '0')
-        lib.set('option', 'var', 'openroad_macro_place_halo', ['15', '15'])
-        lib.set('option', 'var', 'openroad_macro_place_channel', ['30.16', '30.16'])
-
-        # Yosys techmap
-        lib.add('option', 'file', 'yosys_techmap', libdir + '/techmap/yosys/cells_latch.v')
-        lib.add('option', 'file', 'yosys_addermap', libdir + '/techmap/yosys/cells_adders.v')
-        lib.add('option', 'file', 'yosys_tbufmap', libdir + '/techmap/yosys/cells_tristatebuf.v')
-
-        # Openroad specific files
-        lib.set('option', 'file', 'openroad_pdngen',
-                libdir + '/apr/openroad/pdngen.tcl')
-        lib.set('option', 'file', 'openroad_global_connect',
-                libdir + '/apr/openroad/global_connect.tcl')
-        lib.set('option', 'file', 'openroad_tapcells',
-                libdir + '/apr/openroad/tapcell.tcl')
-
-        lib.set('option', 'var', 'openroad_cts_distance_between_buffers', "100")
-
-        lib.set('option', 'var', 'yosys_abc_clock_multiplier', "1000")  # convert from ns -> ps
-
-        cap_table = {  # __buf_4
-            '7t': "0.038pF",
-            '9t': "0.056pF"
-        }
-        lib.set('option', 'var', 'yosys_abc_constraint_load', cap_table[libtype])
-        lib.set('option', 'var', 'yosys_driver_cell', f"gf180mcu_fd_sc_mcu{libtype}5v0__buf_4")
-        lib.set('option', 'var', 'yosys_buffer_cell', f"gf180mcu_fd_sc_mcu{libtype}5v0__buf_4")
-        lib.set('option', 'var', 'yosys_buffer_input', "I")
-        lib.set('option', 'var', 'yosys_buffer_output', "Z")
-        for tool in ('yosys', 'openroad'):
-            lib.set('option', 'var', f'{tool}_tiehigh_cell',
-                    f"gf180mcu_fd_sc_mcu{libtype}5v0__tieh")
-            lib.set('option', 'var', f'{tool}_tiehigh_port', "Z")
-            lib.set('option', 'var', f'{tool}_tielow_cell',
-                    f"gf180mcu_fd_sc_mcu{libtype}5v0__tiel")
-            lib.set('option', 'var', f'{tool}_tielow_port', "ZN")
-
-        # Bambu setup
-        lib.set('option', 'var', 'bambu_clock_multiplier', "1")  # convert from ns -> ns
-
-        libs.append(lib)
-
-        std_lambda_lib = siliconcompiler.Library(f'lambdalib_stdlib_{libname}',
-                                                 package='lambdapdk')
-        register_data_source(std_lambda_lib)
-        std_lambda_lib.add('option', 'ydir', libdir + '/lambda/stdlib')
-        std_lambda_lib.use(lib)
-        std_lambda_lib.set('asic', 'logiclib', lib.design)
-        libs.append(std_lambda_lib)
-        aux_lambda_lib = siliconcompiler.Library(f'lambdalib_auxlib_{libname}',
-                                                 package='lambdapdk')
-        register_data_source(aux_lambda_lib)
-        aux_lambda_lib.add('option', 'ydir', libdir + '/lambda/auxlib')
-        aux_lambda_lib.use(std_lambda_lib)
-        aux_lambda_lib.use(lib)
-        aux_lambda_lib.set('asic', 'logiclib', lib.design)
-        aux_lambda_lib.set('option', 'library', std_lambda_lib.design)
-        libs.append(aux_lambda_lib)
-
-    return libs
-
-
-#########################
-if __name__ == "__main__":
-    libs = setup()
-    for lib in libs:
-        lib.write_manifest(f'{lib.top()}.json')
-        lib.check_filepaths()
+        self.add_asic_celllist('tie', [f'gf180mcu_fd_sc_mcu{libtype}5v0__tieh',
+                                       f'gf180mcu_fd_sc_mcu{libtype}5v0__tiel'])
+
+        # Setup for yosys
+        with self.active_dataroot("lambdapdk"):
+            cap_table = {  # __buf_4
+                '7t': 38,
+                '9t': 56
+            }
+            self.set_yosys_driver_cell(f"gf180mcu_fd_sc_mcu{libtype}5v0__buf_4")
+            self.set_yosys_buffer_cell(f"gf180mcu_fd_sc_mcu{libtype}5v0__buf_4", "I", "Z")
+            self.set_yosys_tielow_cell(f"gf180mcu_fd_sc_mcu{libtype}5v0__tiel", "ZN")
+            self.set_yosys_tiehigh_cell(f"gf180mcu_fd_sc_mcu{libtype}5v0__tieh", "Z")
+            self.set_yosys_abc(1000, cap_table[libtype])
+            self.set_yosys_tristatebuffer_map(
+                lib_path / "techmap" / "yosys" / "cells_tristatebuf.v")
+            self.set_yosys_adder_map(lib_path / "techmap" / "yosys" / "cells_adders.v")
+            self.add_yosys_tech_map(lib_path / "techmap" / "yosys" / "cells_latch.v")
+
+        # Setup for OpenROAD
+        with self.active_dataroot("lambdapdk"):
+            self.set_openroad_placement_density(0.50)
+            self.set_openroad_tielow_cell(f"gf180mcu_fd_sc_mcu{libtype}5v0__tiel", "ZN")
+            self.set_openroad_tiehigh_cell(f"gf180mcu_fd_sc_mcu{libtype}5v0__tieh", "Z")
+            self.set_openroad_macro_placement_halo(15, 15)
+            self.set_openroad_tapcells_file(lib_path / "apr" / "openroad" / "tapcell.tcl")
+            self.add_openroad_global_connect_file(
+                lib_path / "apr" / "openroad" / "global_connect.tcl")
+            self.add_openroad_power_grid_file(lib_path / "apr" / "openroad" / "pdngen.tcl")
+
+        # Setup for bambu
+        self.set_bambu_clock_multiplier(1)
+
+
+class GF180_MCU_7T_3LMLibrary(_GF180_MCULibrary):
+    def __init__(self):
+        super().__init__("7t", "3LM")
+
+
+class GF180_MCU_7T_4LMLibrary(_GF180_MCULibrary):
+    def __init__(self):
+        super().__init__("7t", "4LM")
+
+
+class GF180_MCU_7T_5LMLibrary(_GF180_MCULibrary):
+    def __init__(self):
+        super().__init__("7t", "5LM")
+
+
+class GF180_MCU_7T_6LMLibrary(_GF180_MCULibrary):
+    def __init__(self):
+        super().__init__("7t", "6LM")
+
+
+class GF180_MCU_9T_3LMLibrary(_GF180_MCULibrary):
+    def __init__(self):
+        super().__init__("9t", "3LM")
+
+
+class GF180_MCU_9T_4LMLibrary(_GF180_MCULibrary):
+    def __init__(self):
+        super().__init__("9t", "4LM")
+
+
+class GF180_MCU_9T_5LMLibrary(_GF180_MCULibrary):
+    def __init__(self):
+        super().__init__("9t", "5LM")
+
+
+class GF180_MCU_9T_6LMLibrary(_GF180_MCULibrary):
+    def __init__(self):
+        super().__init__("9t", "6LM")

lambdapdk/gf180/libs/gf180sram.py

@@ -1,63 +1,121 @@
-from siliconcompiler import Chip, Library
-from lambdapdk import register_data_source
-
-
-def setup():
-    libs = []
-
-    for config in ('64x8', '128x8', '256x8', '512x8'):
-        mem_name = f'gf180mcu_fd_ip_sram__sram{config}m8wm1'
-        lib = Library(mem_name, package='lambdapdk')
-        register_data_source(lib)
-
-        path_base = 'lambdapdk/gf180/libs/gf180mcu_fd_ip_sram'
-
-        for stackup in ("3LM_1TM_6K",
-                        "3LM_1TM_9K",
-                        "3LM_1TM_11K",
-                        "3LM_1TM_30K",
-                        "4LM_1TM_6K",
-                        "4LM_1TM_9K",
-                        "4LM_1TM_11K",
-                        "4LM_1TM_30K",
-                        "5LM_1TM_9K",
-                        "5LM_1TM_11K",
-                        "6LM_1TM_9K"):
-            lib.add('output', stackup, 'lef', f'{path_base}/lef/{mem_name}.lef')
-            lib.add('output', stackup, 'gds', f'{path_base}/gds/{mem_name}.gds.gz')
-            lib.add('output', stackup, 'cdl', f'{path_base}/cdl/{mem_name}.cdl')
-
-        lib.add('output', 'slow', 'nldm',
-                f'{path_base}/nldm/{mem_name}__ss_125C_4v50.lib.gz')
-        lib.add('output', 'typical', 'nldm',
-                f'{path_base}/nldm/{mem_name}__tt_025C_5v00.lib.gz')
-        lib.add('output', 'fast', 'nldm',
-                f'{path_base}/nldm/{mem_name}__ff_n40C_5v50.lib.gz')
-
-        for corner in ('slow', 'typical', 'fast'):
-            lib.add('output', corner, 'spice',
-                    f'{path_base}/spice/{mem_name}.spice')
-
-        lib.set('option', 'file', 'openroad_pdngen',
-                f'{path_base}/apr/openroad/pdngen.tcl')
-        lib.set('option', 'file', 'openroad_global_connect',
-                f'{path_base}/apr/openroad/global_connect.tcl')
-
-        libs.append(lib)
-
-    lambda_lib = Library('lambdalib_gf180sram', package='lambdapdk')
-    register_data_source(lambda_lib)
-    lambda_lib.add('option', 'ydir', 'lambdapdk/gf180/libs/gf180mcu_fd_ip_sram/lambda')
-    for lib in libs:
-        lambda_lib.use(lib)
-        lambda_lib.add('asic', 'macrolib', lib.design)
-
-    libs.append(lambda_lib)
-
-    return libs
-
-
-#########################
-if __name__ == "__main__":
-    for lib in setup(Chip('<lib>')):
-        lib.write_manifest(f'{lib.top()}.json')
+from pathlib import Path
+
+from lambdalib import LambalibTechLibrary
+from lambdapdk import LambdaLibrary, _LambdaPath
+from lambdapdk.gf180 import GF180_3LM_1TM_6K_7t, \
+    GF180_3LM_1TM_6K_9t, \
+    GF180_3LM_1TM_9K_7t, \
+    GF180_3LM_1TM_9K_9t, \
+    GF180_3LM_1TM_11K_7t, \
+    GF180_3LM_1TM_11K_9t, \
+    GF180_3LM_1TM_30K_7t, \
+    GF180_3LM_1TM_30K_9t, \
+    GF180_4LM_1TM_6K_7t, \
+    GF180_4LM_1TM_6K_9t, \
+    GF180_4LM_1TM_9K_7t, \
+    GF180_4LM_1TM_9K_9t, \
+    GF180_4LM_1TM_11K_7t, \
+    GF180_4LM_1TM_11K_9t, \
+    GF180_4LM_1TM_30K_7t, \
+    GF180_4LM_1TM_30K_9t, \
+    GF180_5LM_1TM_9K_7t, \
+    GF180_5LM_1TM_9K_9t, \
+    GF180_5LM_1TM_11K_7t, \
+    GF180_5LM_1TM_11K_9t, \
+    GF180_6LM_1TM_9K_7t, \
+    GF180_6LM_1TM_9K_9t
+
+
+class _GF180SRAMLibrary(LambdaLibrary):
+    def __init__(self, config):
+        super().__init__()
+        self.set_name(f"gf180mcu_fd_ip_sram__sram{config}m8wm1")
+
+        self.add_asic_pdk(GF180_3LM_1TM_6K_7t(), default=False)
+        self.add_asic_pdk(GF180_3LM_1TM_6K_9t(), default=False)
+        self.add_asic_pdk(GF180_3LM_1TM_9K_7t(), default=False)
+        self.add_asic_pdk(GF180_3LM_1TM_9K_9t(), default=False)
+        self.add_asic_pdk(GF180_3LM_1TM_11K_7t(), default=False)
+        self.add_asic_pdk(GF180_3LM_1TM_11K_9t(), default=False)
+        self.add_asic_pdk(GF180_3LM_1TM_30K_7t(), default=False)
+        self.add_asic_pdk(GF180_3LM_1TM_30K_9t(), default=False)
+        self.add_asic_pdk(GF180_4LM_1TM_6K_7t(), default=False)
+        self.add_asic_pdk(GF180_4LM_1TM_6K_9t(), default=False)
+        self.add_asic_pdk(GF180_4LM_1TM_9K_7t(), default=False)
+        self.add_asic_pdk(GF180_4LM_1TM_9K_9t(), default=False)
+        self.add_asic_pdk(GF180_4LM_1TM_11K_7t(), default=False)
+        self.add_asic_pdk(GF180_4LM_1TM_11K_9t(), default=False)
+        self.add_asic_pdk(GF180_4LM_1TM_30K_7t(), default=False)
+        self.add_asic_pdk(GF180_4LM_1TM_30K_9t(), default=False)
+        self.add_asic_pdk(GF180_5LM_1TM_9K_7t(), default=False)
+        self.add_asic_pdk(GF180_5LM_1TM_9K_9t(), default=False)
+        self.add_asic_pdk(GF180_5LM_1TM_11K_7t(), default=False)
+        self.add_asic_pdk(GF180_5LM_1TM_11K_9t(), default=False)
+        self.add_asic_pdk(GF180_6LM_1TM_9K_7t(), default=False)
+        self.add_asic_pdk(GF180_6LM_1TM_9K_9t(), default=False)
+
+        path_base = Path("lambdapdk", "gf180", "libs", "gf180mcu_fd_ip_sram")
+
+        with self.active_dataroot("lambdapdk"):
+            with self.active_fileset("models.physical"):
+                self.add_file(path_base / "lef" / f"{self.name}.lef")
+                self.add_file(path_base / "gds" / f"{self.name}.gds.gz")
+                self.add_asic_aprfileset()
+
+            with self.active_fileset("models.lvs"):
+                self.add_file(path_base / "cdl" / f"{self.name}.cdl")
+                self.add_asic_aprfileset()
+
+            for corner_name, filename in [
+                    ('slow', f'{self.name}__ss_125C_4v50.lib.gz'),
+                    ('typical', f'{self.name}__tt_025C_5v00.lib.gz'),
+                    ('fast', f'{self.name}__ff_n40C_5v50.lib.gz')]:
+                with self.active_fileset(f"models.timing.nldm.{corner_name}"):
+                    self.add_file(path_base / "nldm" / filename)
+                    self.add_asic_libcornerfileset(corner_name, "nldm")
+
+            with self.active_fileset("models.spice"):
+                self.add_file(path_base / "spice" / f"{self.name}.spice")
+
+            self.add_openroad_power_grid_file(path_base / "apr" / "openroad" / "pdngen.tcl")
+            self.add_openroad_global_connect_file(
+                path_base / "apr" / "openroad" / "global_connect.tcl")
+
+
+class GF180_SRAM_64x8(_GF180SRAMLibrary):
+    def __init__(self):
+        super().__init__("64x8")
+
+
+class GF180_SRAM_128x8(_GF180SRAMLibrary):
+    def __init__(self):
+        super().__init__("128x8")
+
+
+class GF180_SRAM_256x8(_GF180SRAMLibrary):
+    def __init__(self):
+        super().__init__("256x8")
+
+
+class GF180_SRAM_512x8(_GF180SRAMLibrary):
+    def __init__(self):
+        super().__init__("512x8")
+
+
+class GF180Lambdalib_SinglePort(LambalibTechLibrary, _LambdaPath):
+    def __init__(self):
+        super().__init__("la_spram", [
+            GF180_SRAM_64x8,
+            GF180_SRAM_128x8,
+            GF180_SRAM_256x8,
+            GF180_SRAM_512x8])
+        self.set_name("gf180_la_spram")
+
+        # version
+        self.set_version("v1")
+
+        lib_path = Path("lambdapdk", "gf180", "libs", "gf180mcu_fd_ip_sram")
+
+        with self.active_dataroot("lambdapdk"):
+            with self.active_fileset("rtl"):
+                self.add_file(lib_path / "lambda" / "la_spram.v")