angr 9.2.131__py3-none-manylinux2014_aarch64.whl → 9.2.133__py3-none-manylinux2014_aarch64.whl

angr/storage/memory_mixins/regioned_memory/__init__.py

@@ -8,10 +8,10 @@ from .region_meta_mixin import MemoryRegionMetaMixin
 from .regioned_address_concretization_mixin import RegionedAddressConcretizationMixin
 
 __all__ = (
-    "RegionedMemoryMixin",
-    "RegionCategoryMixin",
-    "StaticFindMixin",
     "AbstractMergerMixin",
     "MemoryRegionMetaMixin",
+    "RegionCategoryMixin",
     "RegionedAddressConcretizationMixin",
+    "RegionedMemoryMixin",
+    "StaticFindMixin",
 )

angr/storage/memory_mixins/regioned_memory/region_data.py

@@ -14,11 +14,11 @@ class AddressWrapper:
     """
 
     __slots__ = (
-        "region",
-        "region_base_addr",
         "address",
-        "is_on_stack",
         "function_address",
+        "is_on_stack",
+        "region",
+        "region_base_addr",
     )
 
     def __init__(self, region: str, region_base_addr: int, address, is_on_stack: bool, function_address: int | None):
@@ -62,8 +62,8 @@ class RegionDescriptor:
     """
 
     __slots__ = (
-        "region_id",
         "base_address",
+        "region_id",
         "related_function_address",
     )
 
@@ -145,7 +145,7 @@ class RegionMap:
         if self.is_stack:
             # Sanity check
             if not region_id.startswith("stack_"):
-                raise SimRegionMapError('Received a non-stack memory ID "%d" in a stack region map' % region_id)
+                raise SimRegionMapError(f'Received a non-stack memory ID "{region_id}" in a stack region map')
 
             # Remove all stack regions that are lower than the one to add
             while True:

angr/storage/memory_mixins/regioned_memory/region_meta_mixin.py

@@ -13,7 +13,7 @@ class Segment:
         self.size = size
 
     def __repr__(self):
-        return "Seg (%s [ %d ])" % (hex(self.offset), self.size)
+        return f"Seg ({hex(self.offset)} [ {self.size} ])"
 
 
 class AbstractLocation:
@@ -120,22 +120,20 @@ class AbstractLocation:
         return False
 
     def __repr__(self):
-        return "(%xh, %d) %s" % (
-            (self.basicblock_key if self.basicblock_key is not None else -1),
-            (self.statement_id if self.statement_id is not None else -1),
-            self._segment_list,
-        )
+        bbl_key = self.basicblock_key if self.basicblock_key is not None else -1
+        stmt_id = self.statement_id if self.statement_id is not None else -1
+        return f"({bbl_key:x}h, {stmt_id}) {self._segment_list}"
 
 
 class MemoryRegionMetaMixin(MemoryMixin):
     __slots__ = (
+        "_alocs",
         "_endness",
         "_id",
-        "_state",
         "_is_stack",
-        "_related_function_addr",
-        "_alocs",
         "_memory",
+        "_related_function_addr",
+        "_state",
     )
 
     def __init__(self, related_function_addr=None, **kwargs):

angr/storage/memory_mixins/regioned_memory/regioned_memory_mixin.py

@@ -95,9 +95,9 @@ class RegionedMemoryMixin(MemoryMixin):
         if isinstance(size, BV) and size.has_annotation_type(RegionAnnotation):
             _l.critical("load(): size %s is a ValueSet. Something is wrong.", size)
             if self.state.scratch.ins_addr is not None:
-                var_name = "invalid_read_%d_%#x" % (next(invalid_read_ctr), self.state.scratch.ins_addr)
+                var_name = f"invalid_read_{next(invalid_read_ctr)}_{self.state.scratch.ins_addr:#x}"
             else:
-                var_name = "invalid_read_%d_None" % next(invalid_read_ctr)
+                var_name = f"invalid_read_{next(invalid_read_ctr)}_None"
 
             return self.state.solver.Unconstrained(var_name, self.state.arch.bits)
 
@@ -127,7 +127,7 @@ class RegionedMemoryMixin(MemoryMixin):
             # address_wrappers is empty - we cannot concretize the address in static mode.
             # ensure val is not None
             val = self.state.solver.Unconstrained(
-                "invalid_read_%d_%d" % (next(invalid_read_ctr), size), size * self.state.arch.byte_width
+                f"invalid_read_{next(invalid_read_ctr)}_{size}", size * self.state.arch.byte_width
             )
 
         return val
@@ -225,7 +225,7 @@ class RegionedMemoryMixin(MemoryMixin):
         if region_id not in region_ids:
             return region_id
         for i in range(2000):
-            new_region_id = region_id + "_%d" % i
+            new_region_id = f"{region_id}_{i}"
             if new_region_id not in region_ids:
                 return new_region_id
         raise SimMemoryError(f"Cannot allocate region ID for function {function_address:#08x} - recursion too deep")

angr/storage/memory_object.py

@@ -21,13 +21,13 @@ class SimMemoryObject:
     """
 
     __slots__ = (
-        "is_bytes",
         "_byte_width",
+        "_concrete_bytes",
         "base",
-        "object",
-        "length",
         "endness",
-        "_concrete_bytes",
+        "is_bytes",
+        "length",
+        "object",
     )
 
     def __init__(self, obj, base, endness, length=None, byte_width=8):

angr/utils/__init__.py

@@ -36,11 +36,11 @@ def looks_like_sql(s: str) -> bool:
 
 
 __all__ = (
-    "timethis",
-    "graph",
     "constants",
     "enums_conv",
-    "lazy_import",
+    "graph",
     "is_pyinstaller",
+    "lazy_import",
     "looks_like_sql",
+    "timethis",
 )

angr/utils/bits.py

@@ -1,5 +1,7 @@
 from __future__ import annotations
 
+import claripy
+
 
 def truncate_bits(value: int, nbits: int) -> int:
     """
@@ -19,3 +21,13 @@ def ffs(x: int) -> int:
 def sign_extend(value: int, bits: int) -> int:
     sign_bit = 1 << (bits - 1)
     return (value & (sign_bit - 1)) - (value & sign_bit)
+
+
+def zeroextend_on_demand(op0: claripy.ast.BV, op1: claripy.ast.BV) -> claripy.ast.BV:
+    """
+    ZeroExtend op1 if the size of op1 is smaller than the size of op0. Otherwise, return op1.
+    """
+
+    if op0.size() > op1.size():
+        return claripy.ZeroExt(op0.size() - op1.size(), op1)
+    return op1

angr/utils/dynamic_dictlist.py

@@ -19,7 +19,7 @@ class DynamicDictList(Generic[VT]):
     https://github.com/angr/angr/pull/3471#issuecomment-1236515950.
     """
 
-    __slots__ = ("list_content", "dict_content", "max_size")
+    __slots__ = ("dict_content", "list_content", "max_size")
 
     def __init__(
         self,

angr/utils/graph.py

@@ -572,7 +572,7 @@ class SCCPlaceholder:
         return isinstance(other, SCCPlaceholder) and other.scc_id == self.scc_id
 
     def __hash__(self):
-        return hash("scc_placeholder_%d" % self.scc_id)
+        return hash(f"scc_placeholder_{self.scc_id}")
 
 
 class GraphUtils:

angr/utils/orderedset.py

@@ -1,8 +1,11 @@
 from __future__ import annotations
+from typing import Generic, TypeVar
 import collections.abc
 
+T = TypeVar("T")
 
-class OrderedSet(collections.abc.MutableSet):
+
+class OrderedSet(Generic[T], collections.abc.MutableSet[T]):
     """
     Adapted from http://code.activestate.com/recipes/576694/
     Originally created by Raymond Hettinger and licensed under MIT.

angr/utils/segment_list.py

@@ -13,7 +13,7 @@ class Segment:
     Representing a memory block. This is not the "Segment" in ELF memory model
     """
 
-    __slots__ = ["start", "end", "sort"]
+    __slots__ = ["end", "sort", "start"]
 
     def __init__(self, start, end, sort):
         """
@@ -56,7 +56,7 @@ class SegmentList:
     blocks or not, and obtain the exact block(segment) that the address belongs to.
     """
 
-    __slots__ = ["_list", "_bytes_occupied"]
+    __slots__ = ["_bytes_occupied", "_list"]
 
     def __init__(self):
         self._list: list[Segment] = []

angr/utils/ssa/__init__.py

@@ -1,6 +1,6 @@
 from __future__ import annotations
 from collections import defaultdict
-from typing import Any
+from typing import Any, Literal, overload
 
 import archinfo
 from ailment import Expression, Block
@@ -14,6 +14,19 @@ from .vvar_uses_collector import VVarUsesCollector
 from .tmp_uses_collector import TmpUsesCollector
 
 
+DEPHI_VVAR_REG_OFFSET = 4096
+
+
+@overload
+def get_reg_offset_base_and_size(
+    reg_offset: int, arch: archinfo.Arch, size: int | None = None, resilient: Literal[True] = True
+) -> tuple[int, int]: ...
+@overload
+def get_reg_offset_base_and_size(
+    reg_offset: int, arch: archinfo.Arch, size: int | None = None, resilient: Literal[False] = False
+) -> tuple[int, int] | None: ...
+
+
 def get_reg_offset_base_and_size(
     reg_offset: int, arch: archinfo.Arch, size: int | None = None, resilient: bool = True
 ) -> tuple[int, int] | None:
@@ -34,9 +47,17 @@ def get_reg_offset_base_and_size(
     return base_reg_and_size
 
 
+@overload
 def get_reg_offset_base(
-    reg_offset: int, arch: archinfo.Arch, size: int | None = None, resilient: bool = True
-) -> int | None:
+    reg_offset: int, arch: archinfo.Arch, size: int | None = None, resilient: Literal[True] = True
+) -> int: ...
+@overload
+def get_reg_offset_base(
+    reg_offset: int, arch: archinfo.Arch, size: int | None = None, resilient: Literal[False] = False
+) -> int | None: ...
+
+
+def get_reg_offset_base(reg_offset, arch, size=None, resilient=True):
     """
     Translate a given register offset into the offset of its full register.
 
@@ -188,16 +209,20 @@ def phi_assignment_get_src(stmt: Statement) -> Phi | None:
     return None
 
 
+def is_dephi_vvar(vvar: VirtualVariable) -> bool:
+    return vvar.varid == DEPHI_VVAR_REG_OFFSET
+
+
 __all__ = (
     "VVarUsesCollector",
+    "get_tmp_deflocs",
+    "get_tmp_uselocs",
     "get_vvar_deflocs",
     "get_vvar_uselocs",
-    "is_const_assignment",
-    "is_phi_assignment",
-    "phi_assignment_get_src",
     "is_const_and_vvar_assignment",
+    "is_const_assignment",
     "is_const_vvar_load_assignment",
     "is_const_vvar_load_dirty_assignment",
-    "get_tmp_uselocs",
-    "get_tmp_deflocs",
+    "is_phi_assignment",
+    "phi_assignment_get_src",
 )

{angr-9.2.131.dist-info → angr-9.2.133.dist-info}/METADATA

@@ -1,6 +1,6 @@
 Metadata-Version: 2.1
 Name: angr
-Version: 9.2.131
+Version: 9.2.133
 Summary: A multi-architecture binary analysis toolkit, with the ability to perform dynamic symbolic execution and various static analyses on binaries
 Home-page: https://github.com/angr/angr
 License: BSD-2-Clause
@@ -16,13 +16,13 @@ Description-Content-Type: text/markdown
 License-File: LICENSE
 Requires-Dist: CppHeaderParser
 Requires-Dist: GitPython
-Requires-Dist: ailment==9.2.131
-Requires-Dist: archinfo==9.2.131
+Requires-Dist: ailment==9.2.133
+Requires-Dist: archinfo==9.2.133
 Requires-Dist: cachetools
 Requires-Dist: capstone==5.0.3
 Requires-Dist: cffi>=1.14.0
-Requires-Dist: claripy==9.2.131
-Requires-Dist: cle==9.2.131
+Requires-Dist: claripy==9.2.133
+Requires-Dist: cle==9.2.133
 Requires-Dist: itanium-demangler
 Requires-Dist: mulpyplexer
 Requires-Dist: nampa
@@ -31,7 +31,7 @@ Requires-Dist: protobuf>=5.28.2
 Requires-Dist: psutil
 Requires-Dist: pycparser>=2.18
 Requires-Dist: pyformlang
-Requires-Dist: pyvex==9.2.131
+Requires-Dist: pyvex==9.2.133
 Requires-Dist: rich>=13.1.0
 Requires-Dist: sortedcontainers
 Requires-Dist: sympy