angr 9.2.131__py3-none-manylinux2014_aarch64.whl → 9.2.133__py3-none-manylinux2014_aarch64.whl

angr/slicer.py

@@ -11,10 +11,10 @@ class SimLightState:
     """
 
     __slots__ = (
-        "temps",
+        "options",
         "regs",
         "stack_offsets",
-        "options",
+        "temps",
     )
 
     def __init__(self, temps=None, regs=None, stack_offsets=None, options=None):
@@ -155,11 +155,8 @@ class SimSlicer:
     def _forward_handler_expr_Get(self, expr, state):
         reg = expr.offset
 
-        if (
-            state.options["mock_sp"]
-            and reg == self._arch.sp_offset
-            or state.options["mock_bp"]
-            and reg == self._arch.bp_offset
+        if (state.options["mock_sp"] and reg == self._arch.sp_offset) or (
+            state.options["mock_bp"] and reg == self._arch.bp_offset
         ):
             return state.regs[reg]
 

angr/state_plugins/__init__.py

@@ -31,56 +31,56 @@ from .debug_variables import SimDebugVariable, SimDebugVariablePlugin
 
 
 __all__ = (
-    "SimStatePlugin",
-    "SimStateLibc",
-    "SimInspector",
-    "NO_OVERRIDE",
-    "BP_BEFORE",
     "BP_AFTER",
+    "BP_BEFORE",
     "BP_BOTH",
     "BP_IPDB",
     "BP_IPYTHON",
+    "GDB",
+    "NO_OVERRIDE",
+    "CallStack",
+    "Concrete",
+    "PTChunk",
+    "PTChunkIterator",
     "PosixDevFS",
     "PosixProcFS",
-    "SimSystemPosix",
-    "SimSolver",
-    "SimLightRegisters",
-    "SimStateLog",
-    "SimStateHistory",
-    "SimStateScratch",
-    "SimStateCGC",
-    "GDB",
-    "SimUCManager",
-    "Unicorn",
     "SimAction",
-    "SimActionExit",
     "SimActionConstraint",
-    "SimActionOperation",
     "SimActionData",
+    "SimActionExit",
     "SimActionObject",
+    "SimActionOperation",
+    "SimDebugVariable",
+    "SimDebugVariablePlugin",
     "SimEvent",
-    "resource_event",
-    "CallStack",
-    "SimStateGlobals",
-    "SimStatePreconstrainer",
-    "SimStateLoopData",
-    "SimRegNameView",
-    "SimMemView",
-    "StructMode",
-    "Stat",
     "SimFilesystem",
-    "SimMount",
-    "SimHostFilesystem",
     "SimHeapBase",
     "SimHeapBrk",
     "SimHeapLibc",
     "SimHeapPTMalloc",
-    "PTChunk",
-    "PTChunkIterator",
-    "Concrete",
-    "SimStateJNIReferences",
+    "SimHostFilesystem",
+    "SimInspector",
     "SimJavaVmClassloader",
+    "SimLightRegisters",
+    "SimMemView",
+    "SimMount",
+    "SimRegNameView",
+    "SimSolver",
+    "SimStateCGC",
+    "SimStateGlobals",
+    "SimStateHistory",
+    "SimStateJNIReferences",
+    "SimStateLibc",
+    "SimStateLog",
+    "SimStateLoopData",
+    "SimStatePlugin",
+    "SimStatePreconstrainer",
+    "SimStateScratch",
     "SimSymbolizer",
-    "SimDebugVariable",
-    "SimDebugVariablePlugin",
+    "SimSystemPosix",
+    "SimUCManager",
+    "Stat",
+    "StructMode",
+    "Unicorn",
+    "resource_event",
 )

angr/state_plugins/callstack.py

@@ -119,14 +119,11 @@ class CallStack(SimStatePlugin):
         :return: A printable representation of the CallStack object
         :rtype: str
         """
-        return "<CallStack (depth %d)>" % len(self)
+        return f"<CallStack (depth {len(self)})>"
 
     def __str__(self):
-        return "Backtrace:\n{}".format(
-            "\n".join(
-                "Frame %d: %#x => %#x, sp = %#x" % (i, f.call_site_addr, f.func_addr, f.stack_ptr)
-                for i, f in enumerate(self)
-            )
+        return "Backtrace:\n" + "\n".join(
+            f"Frame {i}: {f.call_site_addr:#x} => {f.func_addr:#x}, sp = {f.stack_ptr:#x}" for i, f in enumerate(self)
         )
 
     def __eq__(self, other):
@@ -319,13 +316,9 @@ class CallStack(SimStatePlugin):
 
         stack = []
         for i, frame in enumerate(self):
-            s = "%d | %s -> %s, returning to %s" % (
-                i,
-                "None" if frame.call_site_addr is None else f"{frame.call_site_addr:#x}",
-                "None" if frame.func_addr is None else f"{frame.func_addr:#x}",
-                "None" if frame.current_return_target is None else f"{frame.current_return_target:#x}",
+            stack.append(
+                f"{i} | {frame.call_site_addr:#x} -> {frame.func_addr:#x}, returning to {frame.current_return_target:#x}"
             )
-            stack.append(s)
 
         return "\n".join(stack)
 

angr/state_plugins/heap/__init__.py

@@ -6,10 +6,10 @@ from .heap_libc import SimHeapLibc
 from .heap_ptmalloc import SimHeapPTMalloc, PTChunk, PTChunkIterator
 
 __all__ = (
+    "PTChunk",
+    "PTChunkIterator",
     "SimHeapBase",
     "SimHeapBrk",
     "SimHeapLibc",
     "SimHeapPTMalloc",
-    "PTChunk",
-    "PTChunkIterator",
 )

angr/state_plugins/heap/heap_brk.py

@@ -90,10 +90,8 @@ class SimHeapBrk(SimHeapBase):
 
         final_size = size * nmemb
 
-        if (
-            self.state.solver.symbolic(sim_nmemb)
-            or self.state.solver.symbolic(sim_size)
-            and final_size > plugin.max_variable_size
+        if self.state.solver.symbolic(sim_nmemb) or (
+            self.state.solver.symbolic(sim_size) and final_size > plugin.max_variable_size
         ):
             final_size = plugin.max_variable_size
 

angr/state_plugins/heap/heap_ptmalloc.py

@@ -75,7 +75,7 @@ class PTChunk(Chunk):
                 next_chunk.set_prev_freeness(is_free)
             else:
                 self.heap._set_final_freeness(is_free)
-        if (is_free is not None and is_free or self.is_free()) and next_chunk is not None:
+        if ((is_free is not None and is_free) or self.is_free()) and next_chunk is not None:
             self.state.memory.store(next_chunk.base, size, size=self.state.arch.bytes)
 
     def set_prev_freeness(self, is_free):

angr/state_plugins/jni_references.py

@@ -30,8 +30,9 @@ class SimStateJNIReferences(SimStatePlugin):
         if opaque_ref_value in self.global_refs:
             return self.global_refs[opaque_ref_value]
         raise KeyError(
-            "Unknown JNI reference %d. Local references: %s Global references: %s"
-            % (opaque_ref_value, self.local_refs, self.global_refs)
+            f"Unknown JNI reference {opaque_ref_value}. "
+            f"Local references: {self.local_refs} "
+            f"Global references: {self.global_refs}"
         )
 
     def create_new_reference(self, obj, global_ref=False):

angr/state_plugins/scratch.py

@@ -108,7 +108,7 @@ class SimStateScratch(SimStatePlugin):
             v = self.temps[tmp]
             if v is None:
                 raise SimMissingTempError(
-                    "VEX temp variable %d does not exist. This is usually the result of an incorrect slicing." % tmp
+                    f"VEX temp variable {tmp} does not exist. This is usually the result of an incorrect slicing."
                 )
         except IndexError as err:
             raise SimMissingTempError("Accessing a temp that is illegal in this tyenv") from err

angr/state_plugins/sim_action.py

@@ -38,10 +38,7 @@ class SimAction(SimEvent):
         if self.sim_procedure is not None:
             location = f"{self.sim_procedure.display_name}()"
         else:
-            if self.stmt_idx is not None:
-                location = "0x%x:%d" % (self.ins_addr, self.stmt_idx)  # TODO: Revert this!
-            else:
-                location = f"0x{self.bbl_addr:x}"
+            location = f"0x{self.ins_addr:x}:{self.stmt_idx}" if self.stmt_idx is not None else f"0x{self.bbl_addr:x}"
         return f"<{self.__class__.__name__} {location} {self._desc()}>"
 
     def _desc(self):

angr/state_plugins/sim_event.py

@@ -25,7 +25,7 @@ class SimEvent:
         self.arch = state.arch
 
     def __repr__(self):
-        return "<SimEvent %s %d, with fields %s>" % (self.type, self.id, ", ".join(self.objects.keys()))
+        return f"<SimEvent {self.type} {self.id}, with fields {', '.join(self.objects.keys())}>"
 
     def _copy_event(self):
         c = self.__class__.__new__(self.__class__)

angr/state_plugins/solver.py

@@ -112,7 +112,7 @@ def error_converter(f):
 def _concrete_bool(e):
     if isinstance(e, bool):
         return e
-    if isinstance(e, claripy.ast.Base) and e.op == "BoolV" or isinstance(e, SimActionObject) and e.op == "BoolV":
+    if (isinstance(e, claripy.ast.Base) and e.op == "BoolV") or (isinstance(e, SimActionObject) and e.op == "BoolV"):
         return e.args[0]
     return None
 
@@ -302,10 +302,8 @@ class SimSolver(SimStatePlugin):
         elif o.SYMBOLIC in self.state.options and o.COMPOSITE_SOLVER in self.state.options:
             self._stored_solver = claripy.SolverComposite(track=track)
         elif (
-            o.SYMBOLIC in self.state.options
-            and any(opt in self.state.options for opt in o.approximation)
-            or o.HYBRID_SOLVER in self.state.options
-        ):
+            o.SYMBOLIC in self.state.options and any(opt in self.state.options for opt in o.approximation)
+        ) or o.HYBRID_SOLVER in self.state.options:
             self._stored_solver = claripy.SolverHybrid(track=track, approximate_first=approximate_first)
         elif o.SYMBOLIC in self.state.options:
             self._stored_solver = claripy.Solver(track=track)
@@ -856,7 +854,7 @@ class SimSolver(SimStatePlugin):
 
         cast_vals = [self._cast_to(e, v, cast_to) for v in self._eval(e, n, **kwargs)]
         if len(cast_vals) == 0:
-            raise SimUnsatError("Not satisfiable: %s, expected up to %d solutions" % (e.shallow_repr(), n))
+            raise SimUnsatError(f"Not satisfiable: {e.shallow_repr()}, expected up to {n} solutions")
         return cast_vals
 
     @overload
@@ -967,7 +965,7 @@ class SimSolver(SimStatePlugin):
         """
         r = self.eval_upto(e, n + 1, cast_to, **kwargs)
         if len(r) > n:
-            raise SimValueError("Concretized %d values (must be at most %d) in eval_atmost" % (len(r), n))
+            raise SimValueError(f"Concretized {len(r)} values (must be at most {n}) in eval_atmost")
         return r
 
     @overload
@@ -1002,7 +1000,7 @@ class SimSolver(SimStatePlugin):
         """
         r = self.eval_upto(e, n, cast_to, **kwargs)
         if len(r) != n:
-            raise SimValueError("Concretized %d values (must be at least %d) in eval_atleast" % (len(r), n))
+            raise SimValueError(f"Concretized {len(r)} values (must be at least {n}) in eval_atleast")
         return r
 
     @overload
@@ -1038,7 +1036,7 @@ class SimSolver(SimStatePlugin):
         """
         r = self.eval_upto(e, n + 1, cast_to, **kwargs)
         if len(r) != n:
-            raise SimValueError("Concretized %d values (must be exactly %d) in eval_exact" % (len(r), n))
+            raise SimValueError(f"Concretized {len(r)} values (must be exactly {n}) in eval_exact")
         return r
 
     min_int = min

angr/state_plugins/uc_manager.py

@@ -48,7 +48,7 @@ class SimUCManager(SimStatePlugin):
         dst_uc_alloc_depth = self._uc_alloc_depth[dst_addr_ast]
         if dst_uc_alloc_depth > self._max_alloc_depth:
             raise SimUCManagerAllocationError(
-                "Current allocation depth %d is greater than the cap (%d)" % (dst_uc_alloc_depth, self._max_alloc_depth)
+                f"Current allocation depth {dst_uc_alloc_depth} is greater than the cap ({self._max_alloc_depth})"
             )
 
         abs_addr = self._region_base + self._pos

angr/state_plugins/view.py

@@ -90,8 +90,8 @@ class SimRegNameView(SimStatePlugin):
         if self.state.arch.name in ("X86", "AMD64"):
             return (
                 list(self.state.arch.registers.keys())
-                + ["st%d" % n for n in range(8)]
-                + ["tag%d" % n for n in range(8)]
+                + [f"st{n}" for n in range(8)]
+                + [f"tag{n}" for n in range(8)]
                 + ["flags", "eflags", "rflags"]
             )
         if is_arm_arch(self.state.arch):

angr/storage/__init__.py

@@ -9,7 +9,7 @@ from .memory_mixins import DefaultMemory
 
 __all__ = (
     "DUMMY_SYMBOLIC_READ_VALUE",
+    "DefaultMemory",
     "SimFile",
     "SimMemoryObject",
-    "DefaultMemory",
 )

angr/storage/file.py

@@ -109,7 +109,7 @@ class SimFileBase(SimStatePlugin):
                     yield "?"
 
         nice_name = "".join(generate())
-        return "file_%d_%s" % (next(file_counter), nice_name)
+        return f"file_{next(file_counter)}_{nice_name}"
 
     def concretize(self, **kwargs):
         """
@@ -250,7 +250,7 @@ class SimFile(SimFileBase, DefaultMemory):  # TODO: pick a better base class omg
         if type(self._size) is int:
             self._size = claripy.BVV(self._size, state.arch.bits)
         elif len(self._size) != state.arch.bits:
-            raise TypeError("SimFile size must be a bitvector of size %d (arch.bits)" % state.arch.bits)
+            raise TypeError(f"SimFile size must be a bitvector of size {state.arch.bits} (arch.bits)")
 
     @property
     def size(self):
@@ -379,7 +379,7 @@ class SimFileStream(SimFile):
         if type(self.pos) is int:
             self.pos = claripy.BVV(self.pos, state.arch.bits)
         elif len(self.pos) != state.arch.bits:
-            raise TypeError("SimFileStream position must be a bitvector of size %d (arch.bits)" % state.arch.bits)
+            raise TypeError(f"SimFileStream position must be a bitvector of size {state.arch.bits} (arch.bits)")
 
     def read(self, pos, size, **kwargs):
         no_stream = kwargs.pop("no_stream", False)
@@ -509,9 +509,9 @@ class SimPackets(SimFileBase):
         if pos is None:
             pos = len(self.content)
         if pos < 0:
-            raise SimFileError("SimPacket.read(%d): Negative packet number?" % pos)
+            raise SimFileError(f"SimPacket.read({pos}): Negative packet number?")
         if pos > len(self.content):
-            raise SimFileError("SimPacket.read(%d): Packet number is past frontier of %d?" % (pos, len(self.content)))
+            raise SimFileError(f"SimPacket.read({pos}): Packet number is past frontier of {len(self.content)}?")
         if pos != len(self.content):
             _, realsize = self.content[pos]
             self.state.add_constraints(realsize <= size)  # assert that the packet fits within the read request
@@ -533,7 +533,7 @@ class SimPackets(SimFileBase):
         # if short reads are enabled, replace size with a symbol
         if short_reads is True or (short_reads is None and sim_options.SHORT_READS in self.state.options):
             size = self.state.solver.BVS(
-                "packetsize_%d_%s" % (len(self.content), self.ident),
+                f"packetsize_{len(self.content)}_{self.ident}",
                 self.state.arch.bits,
                 key=("file", self.ident, "packetsize", len(self.content)),
             )
@@ -561,7 +561,7 @@ class SimPackets(SimFileBase):
 
         # generate the packet data and return it
         data = self.state.solver.BVS(
-            "packet_%d_%s" % (len(self.content), self.ident),
+            f"packet_{len(self.content)}_{self.ident}",
             max_size * self.state.arch.byte_width,
             key=("file", self.ident, "packet", len(self.content)),
         )
@@ -601,9 +601,9 @@ class SimPackets(SimFileBase):
         if pos is None:
             pos = len(self.content)
         if pos < 0:
-            raise SimFileError("SimPacket.write(%d): Negative packet number?" % pos)
+            raise SimFileError(f"SimPacket.write({pos}): Negative packet number?")
         if pos > len(self.content):
-            raise SimFileError("SimPacket.write(%d): Packet number is past frontier of %d?" % (pos, len(self.content)))
+            raise SimFileError(f"SimPacket.write({pos}): Packet number is past frontier of {len(self.content)}?")
         if pos != len(self.content):
             realdata, realsize = self.content[pos]
             maxlen = max(len(realdata), len(data))
@@ -1171,7 +1171,7 @@ class SimPacketsSlots(SimFileBase):
             self.read_sizes.pop(0)
 
         data = self.state.solver.BVS(
-            "packet_%d_%s" % (len(self.read_data), self.ident),
+            f"packet_{len(self.read_data)}_{self.ident}",
             real_size * self.state.arch.byte_width,
             key=("file", self.ident, "packet", len(self.read_data)),
         )

angr/storage/memory_mixins/__init__.py

@@ -249,69 +249,69 @@ SimState.register_default("javavm_memory", JavaVmMemory)
 
 
 __all__ = (
+    "AbstractMemory",
+    "AbstractMergerMixin",
     "ActionsMixinHigh",
     "ActionsMixinLow",
     "AddressConcretizationMixin",
-    "DataNormalizationMixin",
-    "InspectMixinHigh",
+    "ClemoryBackerMixin",
+    "ConcreteBackerMixin",
     "ConditionalMixin",
     "ConvenientMappingsMixin",
+    "CooperationBase",
+    "DataNormalizationMixin",
     "DefaultFillerMixin",
-    "SpecialFillerMixin",
-    "ExplicitFillerMixin",
+    "DefaultListPagesMemory",
+    "DefaultMemory",
+    "DictBackerMixin",
     "DirtyAddrsMixin",
+    "ExplicitFillerMixin",
+    "FastMemory",
     "HexDumperMixin",
+    "HistoryTrackingMixin",
+    "ISPOMixin",
+    "InspectMixinHigh",
+    "JavaVmMemory",
+    "JavaVmMemoryMixin",
+    "KeyValueMemory",
+    "KeyValueMemoryMixin",
     "LabelMergerMixin",
-    "MultiValueMergerMixin",
-    "NameResolutionMixin",
-    "SimplificationMixin",
-    "SimpleInterfaceMixin",
-    "SizeNormalizationMixin",
-    "SizeConcretizationMixin",
-    "SmartFindMixin",
-    "SymbolicMergerMixin",
-    "TopMergerMixin",
-    "UnderconstrainedMixin",
-    "UnwrapperMixin",
-    "ClemoryBackerMixin",
-    "ConcreteBackerMixin",
-    "DictBackerMixin",
-    "PagedMemoryMixin",
+    "LabeledMemory",
+    "ListPage",
     "ListPagesMixin",
-    "UltraPagesMixin",
     "ListPagesWithLabelsMixin",
+    "MVListPage",
     "MVListPagesMixin",
     "MVListPagesWithLabelsMixin",
-    "PrivilegedPagingMixin",
-    "StackAllocationMixin",
-    "PagedMemoryMultiValueMixin",
-    "CooperationBase",
     "MemoryObjectMixin",
-    "ISPOMixin",
-    "RefcountMixin",
-    "PermissionsMixin",
-    "HistoryTrackingMixin",
+    "MemoryRegionMetaMixin",
+    "MultiValueMergerMixin",
+    "MultiValuedMemory",
+    "NameResolutionMixin",
     "PageBase",
     "PageType",
-    "ListPage",
-    "MVListPage",
-    "UltraPage",
-    "SlottedMemoryMixin",
-    "RegionedMemoryMixin",
+    "PagedMemoryMixin",
+    "PagedMemoryMultiValueMixin",
+    "PermissionsMixin",
+    "PrivilegedPagingMixin",
+    "RefcountMixin",
     "RegionCategoryMixin",
-    "StaticFindMixin",
-    "AbstractMergerMixin",
-    "MemoryRegionMetaMixin",
     "RegionedAddressConcretizationMixin",
-    "KeyValueMemoryMixin",
-    "JavaVmMemoryMixin",
-    "DefaultMemory",
-    "DefaultListPagesMemory",
-    "FastMemory",
-    "AbstractMemory",
     "RegionedMemory",
-    "LabeledMemory",
-    "MultiValuedMemory",
-    "KeyValueMemory",
-    "JavaVmMemory",
+    "RegionedMemoryMixin",
+    "SimpleInterfaceMixin",
+    "SimplificationMixin",
+    "SizeConcretizationMixin",
+    "SizeNormalizationMixin",
+    "SlottedMemoryMixin",
+    "SmartFindMixin",
+    "SpecialFillerMixin",
+    "StackAllocationMixin",
+    "StaticFindMixin",
+    "SymbolicMergerMixin",
+    "TopMergerMixin",
+    "UltraPage",
+    "UltraPagesMixin",
+    "UnderconstrainedMixin",
+    "UnwrapperMixin",
 )

angr/storage/memory_mixins/default_filler_mixin.py

@@ -30,9 +30,7 @@ class DefaultFillerMixin(MemoryMixin):
             type(addr) is int
             and self.category == "mem"
             and options.ZERO_FILL_UNCONSTRAINED_MEMORY in self.state.options
-            or self.category == "reg"
-            and options.ZERO_FILL_UNCONSTRAINED_REGISTERS in self.state.options
-        ):
+        ) or (self.category == "reg" and options.ZERO_FILL_UNCONSTRAINED_REGISTERS in self.state.options):
             return claripy.BVV(0, bits)
 
         if self.category == "reg" and type(addr) is int and addr == self.state.arch.ip_offset:

angr/storage/memory_mixins/javavm_memory_mixin.py

@@ -192,7 +192,7 @@ class JavaVmMemoryMixin(MemoryMixin):
             self.state.add_constraints(constraint_on_start_idx)
 
     def _store_array_element_on_heap(self, array, idx, value, value_type, store_condition=None):
-        heap_elem_id = "%s[%d]" % (array.id, idx)
+        heap_elem_id = f"{array.id}[{idx}]"
         l.debug("Set %s to %s with condition %s", heap_elem_id, value, store_condition)
         if store_condition is not None:
             current_value = self._load_array_element_from_heap(array, idx)
@@ -267,7 +267,7 @@ class JavaVmMemoryMixin(MemoryMixin):
 
     def _load_array_element_from_heap(self, array: SimSootValue_ArrayBaseRef, idx):
         # try to load the element
-        heap_elem_id = "%s[%d]" % (array.id, idx)
+        heap_elem_id = f"{array.id}[{idx}]"
         value = self.heap.load(heap_elem_id, none_if_missing=True)
         # if it's not available, initialize it
         if value is None:

angr/storage/memory_mixins/name_resolution_mixin.py

@@ -5,8 +5,8 @@ from archinfo.arch_arm import is_arm_arch
 
 from angr.storage.memory_mixins.memory_mixin import MemoryMixin
 
-stn_map = {"st%d" % n: n for n in range(8)}
-tag_map = {"tag%d" % n: n for n in range(8)}
+stn_map = {f"st{n}": n for n in range(8)}
+tag_map = {f"tag{n}": n for n in range(8)}
 
 
 class NameResolutionMixin(MemoryMixin):

angr/storage/memory_mixins/paged_memory/paged_memory_mixin.py

@@ -107,9 +107,7 @@ class PagedMemoryMixin(
                     permissions = perms
                     break
 
-        return dict(
-            memory=self, memory_id="%s_%d" % (self.id, pageno), permissions=permissions, **self._extra_page_kwargs
-        )
+        return dict(memory=self, memory_id=f"{self.id}_{pageno}", permissions=permissions, **self._extra_page_kwargs)
 
     def _divide_addr(self, addr: int) -> tuple[int, int]:
         return divmod(addr, self.page_size)

angr/storage/memory_mixins/paged_memory/pages/__init__.py

@@ -34,14 +34,14 @@ from .ultra_page import UltraPage
 
 __all__ = (
     "CooperationBase",
-    "MemoryObjectMixin",
-    "ISPOMixin",
-    "RefcountMixin",
-    "PermissionsMixin",
     "HistoryTrackingMixin",
-    "PageBase",
-    "PageType",
+    "ISPOMixin",
     "ListPage",
     "MVListPage",
+    "MemoryObjectMixin",
+    "PageBase",
+    "PageType",
+    "PermissionsMixin",
+    "RefcountMixin",
     "UltraPage",
 )

angr/storage/memory_mixins/paged_memory/pages/list_page.py

@@ -263,7 +263,7 @@ class ListPage(MemoryObjectMixin, PageBase):
         for c in candidates:
             s_contains = self._contains(c, page_addr)
             o_contains = other._contains(c, page_addr)
-            if not s_contains and o_contains or s_contains and not o_contains:
+            if (not s_contains and o_contains) or (s_contains and not o_contains):
                 differences.add(c)
             else:
                 if self.content[c] is None:

angr/storage/memory_mixins/paged_memory/pages/multi_values.py

@@ -20,8 +20,8 @@ class MultiValues(Generic[MVType]):
     """
 
     __slots__ = (
-        "_values",
         "_single_value",
+        "_values",
     )
 
     _single_value: MVType | None

angr/storage/memory_mixins/paged_memory/pages/mv_list_page.py

@@ -330,7 +330,7 @@ class MVListPage(
         for c in candidates:
             s_contains = self._contains(c, page_addr)
             o_contains = other._contains(c, page_addr)
-            if not s_contains and o_contains or s_contains and not o_contains:
+            if (not s_contains and o_contains) or (s_contains and not o_contains):
                 differences.add(c)
             else:
                 if self.content[c] is None and self.sinkhole is not None:

angr/storage/memory_mixins/paged_memory/pages/ultra_page.py

@@ -430,10 +430,8 @@ class UltraPage(MemoryObjectMixin, PageBase):
             return None
         else:
             obj = self.symbolic_data[place]
-            if (
-                obj.includes(start + page_addr)
-                or memory is not None
-                and obj.includes(start + page_addr + (1 << memory.state.arch.bits))
+            if obj.includes(start + page_addr) or (
+                memory is not None and obj.includes(start + page_addr + (1 << memory.state.arch.bits))
             ):
                 return obj
             return None