angr 9.2.131__py3-none-manylinux2014_aarch64.whl → 9.2.133__py3-none-manylinux2014_aarch64.whl

angr/annocfg.py

@@ -1,6 +1,7 @@
 from __future__ import annotations
 from collections import defaultdict
 import logging
+from typing import Literal
 
 import networkx
 
@@ -30,7 +31,7 @@ class AnnotatedCFG:
         self._cfg = None
         self._target = None
 
-        self._run_statement_whitelist: dict[int, list[int] | bool] = defaultdict(list)
+        self._run_statement_whitelist: dict[int, list[int] | Literal[True]] = defaultdict(list)
         self._exit_taken = defaultdict(list)
         self._addr_to_run = {}
         self._addr_to_last_stmt_id = {}
@@ -76,6 +77,7 @@ class AnnotatedCFG:
 
     def get_addr(self, run):
         if isinstance(run, CFGNode):
+            assert isinstance(run.addr, int)
             return run.addr
         if type(run) is int:
             return run
@@ -87,17 +89,18 @@ class AnnotatedCFG:
 
     def add_statements_to_whitelist(self, block, stmt_ids):
         addr = self.get_addr(block)
-        if type(stmt_ids) is bool:
+        if stmt_ids is True:
             if type(self._run_statement_whitelist[addr]) is list and self._run_statement_whitelist[addr]:
                 raise Exception("WTF")
             self._run_statement_whitelist[addr] = stmt_ids
         elif -1 in stmt_ids:
             self._run_statement_whitelist[addr] = True
         else:
-            self._run_statement_whitelist[addr].extend(stmt_ids)
-            self._run_statement_whitelist[addr] = sorted(
-                set(self._run_statement_whitelist[addr]), key=lambda v: v if type(v) is int else float("inf")
-            )
+            whitelist_lst = self._run_statement_whitelist[addr]
+            assert whitelist_lst is not True
+            whitelist = set(whitelist_lst)
+            whitelist.update(stmt_ids)
+            self._run_statement_whitelist[addr] = sorted(whitelist)
 
     def add_exit_to_whitelist(self, run_from, run_to):
         addr_from = self.get_addr(run_from)
@@ -135,17 +138,18 @@ class AnnotatedCFG:
             return self._addr_to_run[addr]
         return None
 
-    def get_whitelisted_statements(self, addr):
+    def get_whitelisted_statements(self, addr) -> list[int] | None:
         """
         :returns: True if all statements are whitelisted
         """
         if addr in self._run_statement_whitelist:
-            if self._run_statement_whitelist[addr] is True:
+            whitelist = self._run_statement_whitelist[addr]
+            if whitelist is True:
                 return None  # This is the default value used to say
                 # we execute all statements in this basic block. A
                 # little weird...
 
-            return self._run_statement_whitelist[addr]
+            return whitelist
 
         return []
 
@@ -166,12 +170,12 @@ class AnnotatedCFG:
             return self._addr_to_last_stmt_id[addr]
         if addr in self._run_statement_whitelist:
             # is the default exit there? it equals to a negative number (-2 by default) so `max()` won't work.
-            if self._run_statement_whitelist[addr] is True or (
-                isinstance(self._run_statement_whitelist[addr], list)
-                and DEFAULT_STATEMENT in self._run_statement_whitelist[addr]
+            whitelist = self._run_statement_whitelist[addr]
+            if whitelist is True or (
+                isinstance(self._run_statement_whitelist[addr], list) and DEFAULT_STATEMENT in whitelist
             ):
                 return DEFAULT_STATEMENT
-            return max(self._run_statement_whitelist[addr], key=lambda v: v if type(v) is int else float("inf"))
+            return max(whitelist, key=lambda v: v if type(v) is int else float("inf"))
         return None
 
     def get_loops(self):
@@ -224,8 +228,8 @@ class AnnotatedCFG:
         statements = vex_block.statements
         whitelist = self.get_whitelisted_statements(irsb_addr)
         for i in range(len(statements)):
-            line = "+" if whitelist is True or i in whitelist else "-"
-            line += "[% 3d] " % i
+            line = "+" if whitelist is None or i in whitelist else "-"
+            line += f"[{i: 3d}] "
             # We cannot get data returned by pp(). WTF?
             print(line, end="")
             statements[i].pp()
@@ -301,6 +305,7 @@ class AnnotatedCFG:
 
     def _detect_loops(self):
         temp_graph = networkx.DiGraph()
+        assert self._cfg is not None
         for source, target_list in self._cfg._edge_map.items():
             for target in target_list:
                 temp_graph.add_edge(source, target)

angr/blade.py

@@ -144,13 +144,13 @@ class Blade:
                 else:
                     stmt_str = str(stmt)
 
-                block_str += "%02s %02d | %s\n" % ("+" if i in included_stmts else " ", i, stmt_str)
+                block_str += f"{'+' if i in included_stmts else ' '} {i:02d} | {stmt_str}\n"
 
             block_str += " + " if default_exit_included else "   "
             if isinstance(block.next, pyvex.IRExpr.Const):
                 block_str += f"Next: {block.next.con.value:#x}\n"
             elif isinstance(block.next, pyvex.IRExpr.RdTmp):
-                block_str += "Next: t%d\n" % block.next.tmp
+                block_str += f"Next: t{block.next.tmp}\n"
             else:
                 block_str += f"Next: {block.next!s}\n"
 

angr/block.py

@@ -13,12 +13,9 @@ except ImportError:
 
 from .protos import primitives_pb2 as pb2
 from .serializable import Serializable
-from .engines.vex import VEXLifter
 
 l = logging.getLogger(name=__name__)
 
-DEFAULT_VEX_ENGINE = VEXLifter(None)  # this is only used when Block is not initialized with a project
-
 
 class DisassemblerBlock:
     """
@@ -26,7 +23,7 @@ class DisassemblerBlock:
     instructions
     """
 
-    __slots__ = ["addr", "insns", "thumb", "arch"]
+    __slots__ = ["addr", "arch", "insns", "thumb"]
 
     def __init__(self, addr, insns, thumb, arch):
         self.addr = addr
@@ -38,7 +35,7 @@ class DisassemblerBlock:
         print(str(self))
 
     def __str__(self):
-        return "\n".join(map(str, self.insns))
+        return "\n".join(str(x) for x in self.insns)
 
     def __repr__(self):
         return f"<DisassemblerBlock for {self.addr:#x}>"
@@ -125,25 +122,25 @@ class Block(Serializable):
     BLOCK_MAX_SIZE = 4096
 
     __slots__ = [
-        "_project",
         "_bytes",
-        "_vex",
-        "thumb",
-        "_disassembly",
         "_capstone",
-        "addr",
-        "size",
-        "arch",
-        "_instructions",
-        "_instruction_addrs",
-        "_opt_level",
-        "_vex_nostmt",
         "_collect_data_refs",
-        "_strict_block_end",
-        "_cross_insn_opt",
-        "_load_from_ro_regions",
         "_const_prop",
+        "_cross_insn_opt",
+        "_disassembly",
         "_initial_regs",
+        "_instruction_addrs",
+        "_instructions",
+        "_load_from_ro_regions",
+        "_opt_level",
+        "_project",
+        "_strict_block_end",
+        "_vex",
+        "_vex_nostmt",
+        "addr",
+        "arch",
+        "size",
+        "thumb",
     ]
 
     def __init__(
@@ -280,7 +277,7 @@ class Block(Serializable):
             self.size = vex_block.size
 
     def __repr__(self):
-        return "<Block for %#x, %d bytes>" % (self.addr, self.size)
+        return f"<Block for {self.addr:#x}, {self.size} bytes>"
 
     def __getstate__(self):
         return {k: getattr(self, k) for k in self.__slots__ if k not in {"_capstone", "_disassembly", "_project"}}
@@ -326,8 +323,6 @@ class Block(Serializable):
 
     @property
     def _vex_engine(self):
-        if self._project is None:
-            return DEFAULT_VEX_ENGINE
         return self._project.factory.default_engine
 
     @property
@@ -436,7 +431,7 @@ class Block(Serializable):
         return self._bytes
 
     @property
-    def instructions(self):
+    def instructions(self) -> int:
         if not self._instructions and self._vex is None:
             # initialize from VEX
             _ = self.vex
@@ -457,7 +452,7 @@ class Block(Serializable):
 
     @classmethod
     def _get_cmsg(cls):
-        return pb2.Block()
+        return pb2.Block()  # pylint: disable=no-member
 
     def serialize_to_cmessage(self):
         obj = self._get_cmsg()
@@ -490,7 +485,7 @@ class SootBlock:
     @property
     def _soot_engine(self):
         if self._project is None:
-            raise Exception("SHIIIIIIIT")
+            assert False, "This should be unreachable"
         return self._project.factory.default_engine
 
     @property

angr/calling_conventions.py

@@ -229,7 +229,7 @@ class SimFunctionArgument:
     :ivar bool is_fp:  Whether loads from this location should return a floating point bitvector
     """
 
-    def __init__(self, size, is_fp=False):
+    def __init__(self, size: int, is_fp: bool = False):
         self.size = size
         self.is_fp = is_fp
 
@@ -243,12 +243,12 @@ class SimFunctionArgument:
         if not isinstance(value, claripy.ast.Base) and self.size is None:
             raise TypeError("Only claripy objects may be stored through SimFunctionArgument when size is not provided")
         if self.size is not None and isinstance(value, claripy.ast.Base) and self.size * arch.byte_width < value.length:
-            raise TypeError("%s doesn't fit in an argument of size %d" % (value, self.size))
+            raise TypeError(f"{value} doesn't fit in an argument of size {self.size}")
         if isinstance(value, int):
             value = claripy.BVV(value, self.size * arch.byte_width)
         if isinstance(value, float):
             if self.size not in (4, 8):
-                raise ValueError("What do I do with a float %d bytes long" % self.size)
+                raise ValueError(f"What do I do with a float {self.size} bytes long")
             value = claripy.FPV(value, claripy.FSORT_FLOAT if self.size == 4 else claripy.FSORT_DOUBLE)
         return value.raw_to_bv()
 
@@ -468,7 +468,7 @@ class SimArrayArg(SimFunctionArgument):
 
     def set_value(self, state, value, **kwargs):
         if len(value) != len(self.locs):
-            raise TypeError("Expected %d elements, got %d" % (len(self.locs), len(value)))
+            raise TypeError(f"Expected {len(self.locs)} elements, got {len(value)}")
         for subvalue, setter in zip(value, self.locs):
             setter.set_value(state, subvalue, **kwargs)
 
@@ -505,10 +505,10 @@ class ArgSession:
     """
 
     __slots__ = (
+        "both_iter",
         "cc",
         "fp_iter",
         "int_iter",
-        "both_iter",
     )
 
     def __init__(self, cc):
@@ -1027,7 +1027,7 @@ class SimCC:
                 raise TypeError(f"Type mismatch: Expected {ty}, got {type(arg)} (i.e. struct)")
             if type(arg) is not SimStructValue:
                 if len(arg) != len(ty.fields):
-                    raise TypeError("Wrong number of fields in struct, expected %d got %d" % (len(ty.fields), len(arg)))
+                    raise TypeError(f"Wrong number of fields in struct, expected {len(ty.fields)} got {len(arg)}")
                 arg = SimStructValue(ty, arg)
             return SimStructValue(
                 ty, [SimCC._standardize_value(arg[field], ty.fields[field], state, alloc) for field in ty.fields]
@@ -1063,7 +1063,7 @@ class SimCC:
                 if len(arg) != ty.size:
                     if arg.concrete:
                         return claripy.BVV(arg.concrete_value, ty.size)
-                    raise TypeError("Type mismatch of symbolic data: expected %s, got %d bits" % (ty, len(arg)))
+                    raise TypeError(f"Type mismatch of symbolic data: expected {ty}, got {len(arg)} bits")
                 return arg
             if isinstance(ty, (SimTypeFloat)):
                 raise TypeError(
@@ -2272,7 +2272,7 @@ def default_cc(  # pylint:disable=unused-argument
     platform: str | None = "Linux",
     language: str | None = None,
     syscall: bool = False,
-    **kwargs,
+    default: type[SimCC] | None = None,
 ) -> type[SimCC] | None:
     """
     Return the default calling convention for a given architecture, platform, and language combination.
@@ -2281,19 +2281,19 @@ def default_cc(  # pylint:disable=unused-argument
     :param platform:    The platform name (e.g., "Linux" or "Win32").
     :param language:    The programming language name (e.g., "go").
     :param syscall:     Return syscall convention (True), or normal calling convention (False, default).
+    :param default:     The default calling convention to return if nothing fits.
     :return:            A default calling convention class if we can find one for the architecture, platform, and
-                        language combination, or None if nothing fits.
+                        language combination, or the default if nothing fits.
     """
 
     if platform is None:
         platform = "Linux"
 
-    default = kwargs.get("default", ...)
     cc_map = SYSCALL_CC if syscall else DEFAULT_CC
 
     if arch in cc_map:
         if platform not in cc_map[arch]:
-            if default is not ...:
+            if default is not None:
                 return default
             if "Linux" in cc_map[arch]:
                 return cc_map[arch]["Linux"]
@@ -2301,9 +2301,7 @@ def default_cc(  # pylint:disable=unused-argument
 
     alias = unify_arch_name(arch)
     if alias not in cc_map or platform not in cc_map[alias]:
-        if default is not ...:
-            return default
-        return None
+        return default
     return cc_map[alias][platform]
 
 

angr/code_location.py

@@ -9,14 +9,14 @@ class CodeLocation:
     """
 
     __slots__ = (
+        "_hash",
         "block_addr",
-        "stmt_idx",
-        "sim_procedure",
-        "ins_addr",
+        "block_idx",
         "context",
         "info",
-        "block_idx",
-        "_hash",
+        "ins_addr",
+        "sim_procedure",
+        "stmt_idx",
     )
 
     def __init__(
@@ -65,11 +65,7 @@ class CodeLocation:
                 self.block_addr,
             )
         else:
-            s = "<%s%#x[%d]" % (
-                (f"{self.ins_addr:#x} id=") if self.ins_addr else "",
-                self.block_addr,
-                self.stmt_idx,
-            )
+            s = f"<{(f'{self.ins_addr:#x} id=') if self.ins_addr else ''}{self.block_addr:#x}[{self.stmt_idx}]"
 
         if self.context is None:
             s += " contextless"

angr/codenode.py

@@ -11,7 +11,7 @@ def repr_addr(addr):
 
 
 class CodeNode:
-    __slots__ = ["addr", "size", "_graph", "thumb", "_hash"]
+    __slots__ = ["_graph", "_hash", "addr", "size", "thumb"]
 
     def __init__(self, addr: int, size: int, graph=None, thumb=False):
         self.addr: int = addr
@@ -75,7 +75,7 @@ class BlockNode(CodeNode):
         self.bytestr = bytestr
 
     def __repr__(self):
-        return "<BlockNode at %s (size %d)>" % (repr_addr(self.addr), self.size)
+        return f"<BlockNode at {repr_addr(self.addr)} (size {self.size})>"
 
     def __getstate__(self):
         return (self.addr, self.size, self.bytestr, self.thumb)
@@ -94,7 +94,7 @@ class SootBlockNode(BlockNode):
         assert (stmts is None and size == 0) or (size == len(stmts))
 
     def __repr__(self):
-        return "<SootBlockNode at %s (%d statements)>" % (repr_addr(self.addr), self.size)
+        return f"<SootBlockNode at {repr_addr(self.addr)} ({self.size} statements)>"
 
     def __getstate__(self):
         return self.addr, self.size, self.stmts

angr/engines/__init__.py

@@ -1,7 +1,7 @@
 from __future__ import annotations
 
 from .successors import SimSuccessors
-from .engine import SimEngine, SuccessorsMixin, TLSMixin
+from .engine import SimEngine, SuccessorsMixin
 
 from .vex import HeavyVEXMixin, TrackActionsMixin, SimInspectMixin, HeavyResilienceMixin, SuperFastpathMixin
 from .procedure import ProcedureMixin, ProcedureEngine
@@ -26,29 +26,27 @@ class UberEngine(
     HeavyResilienceMixin,
     SootMixin,
     HeavyVEXMixin,
-    TLSMixin,
 ):
     pass
 
 
 __all__ = [
-    "SimSuccessors",
-    "SimEngine",
-    "SuccessorsMixin",
-    "TLSMixin",
-    "HeavyVEXMixin",
-    "TrackActionsMixin",
-    "SimInspectMixin",
     "HeavyResilienceMixin",
-    "SuperFastpathMixin",
-    "ProcedureMixin",
+    "HeavyVEXMixin",
+    "HooksMixin",
     "ProcedureEngine",
-    "SimEngineUnicorn",
+    "ProcedureMixin",
+    "SimEngine",
+    "SimEngineConcrete",
     "SimEngineFailure",
     "SimEngineSyscall",
-    "SimEngineConcrete",
-    "HooksMixin",
+    "SimEngineUnicorn",
+    "SimInspectMixin",
+    "SimSuccessors",
     "SootMixin",
+    "SuccessorsMixin",
+    "SuperFastpathMixin",
+    "TrackActionsMixin",
     "UberEngine",
 ]
 

angr/engines/engine.py

@@ -1,51 +1,57 @@
-# pylint: disable=no-self-use,unused-private-member
 from __future__ import annotations
 
+from typing import Generic, TypeVar
 import abc
 import logging
-import threading
 
+import claripy
 from archinfo.arch_soot import SootAddressDescriptor
 
 import angr
+from angr.sim_state import SimState
 from angr import sim_options as o
 from angr.errors import SimException
 from angr.state_plugins.inspect import BP_AFTER, BP_BEFORE
-
 from .successors import SimSuccessors
 
+
 l = logging.getLogger(name=__name__)
 
 
-class SimEngineBase:
+StateType = TypeVar("StateType")
+ResultType = TypeVar("ResultType")
+DataType_co = TypeVar("DataType_co", covariant=True)
+HeavyState = SimState[int | SootAddressDescriptor, claripy.ast.BV | SootAddressDescriptor]
+
+
+class SimEngineBase(Generic[StateType]):
     """
     Even more basey of a base class for SimEngine. Used as a base by mixins which want access to the project but for
     which having method `process` (contained in `SimEngine`) doesn't make sense
     """
 
-    def __init__(self, project=None, **kwargs):
+    state: StateType
+
+    def __init__(self, project: angr.Project, **kwargs):
         if kwargs:
             raise TypeError("Unused initializer args: " + ", ".join(kwargs.keys()))
-        self.project: angr.Project | None = project
-        self.state = None
-
-    __tls = ("state",)
+        self.project = project
+        self.arch = self.project.arch
 
     def __getstate__(self):
         return (self.project,)
 
     def __setstate__(self, state):
         self.project = state[0]
-        self.state = None
 
 
-class SimEngine(SimEngineBase, metaclass=abc.ABCMeta):
+class SimEngine(Generic[StateType, ResultType], SimEngineBase[StateType], metaclass=abc.ABCMeta):
     """
     A SimEngine is a class which understands how to perform execution on a state. This is a base class.
     """
 
     @abc.abstractmethod
-    def process(self, state, **kwargs):
+    def process(self, state: StateType, **kwargs) -> ResultType:
         """
         The main entry point for an engine. Should take a state and return a result.
 
@@ -54,51 +60,7 @@ class SimEngine(SimEngineBase, metaclass=abc.ABCMeta):
         """
 
 
-class TLSMixin:
-    """
-    Mix this class into any class that defines __tls to make all of the attributes named in that list into
-    thread-local properties.
-
-    MAGIC MAGIC MAGIC
-    """
-
-    def __new__(cls, *args, **kwargs):  # pylint:disable=unused-argument
-        obj = super().__new__(cls)
-        obj.__local = threading.local()
-        return obj
-
-    def __init_subclass__(cls, **kwargs):
-        super().__init_subclass__(**kwargs)
-
-        for subcls in cls.mro():
-            for attr in subcls.__dict__.get(f"_{subcls.__name__}__tls", ()):
-                if attr.startswith("__"):
-                    attr = f"_{subcls.__name__}{attr}"
-
-                if hasattr(cls, attr):
-                    if type(getattr(cls, attr, None)) is not TLSProperty:
-                        raise Exception(f"Programming error: {attr} is both in __tls and __class__")
-                else:
-                    setattr(cls, attr, TLSProperty(attr))
-
-
-class TLSProperty:  # pylint:disable=missing-class-docstring
-    def __init__(self, name):
-        self.name = name
-
-    def __get__(self, instance, owner):
-        if instance is None:
-            return self
-        return getattr(instance._TLSMixin__local, self.name)
-
-    def __set__(self, instance, value):
-        setattr(instance._TLSMixin__local, self.name, value)
-
-    def __delete__(self, instance):
-        delattr(instance._TLSMixin__local, self.name)
-
-
-class SuccessorsMixin(SimEngine):
+class SuccessorsMixin(SimEngine[HeavyState, SimSuccessors]):
     """
     A mixin for SimEngine which implements ``process`` to perform common operations related to symbolic execution
     and dispatches to a ``process_successors`` method to fill a SimSuccessors object with the results.
@@ -109,9 +71,7 @@ class SuccessorsMixin(SimEngine):
 
         self.successors: SimSuccessors | None = None
 
-    __tls = ("successors",)
-
-    def process(self, state, *args, **kwargs):  # pylint:disable=unused-argument
+    def process(self, state: HeavyState, **kwargs) -> SimSuccessors:  # pylint:disable=unused-argument
         """
         Perform execution with a state.
 
@@ -148,6 +108,7 @@ class SuccessorsMixin(SimEngine):
         new_state.register_plugin("history", old_state.history.make_child())
         new_state.history.recent_bbl_addrs.append(addr)
         if new_state.arch.unicorn_support:
+            assert isinstance(addr, int)
             new_state.scratch.executed_pages_set = {addr & ~0xFFF}
 
         self.successors = SimSuccessors(addr, old_state)
@@ -161,10 +122,12 @@ class SuccessorsMixin(SimEngine):
         except SimException as e:
             if o.EXCEPTION_HANDLING not in old_state.options:
                 raise
+            assert old_state.project is not None
             old_state.project.simos.handle_exception(self.successors, self, e)
 
         new_state._inspect("engine_process", when=BP_AFTER, sim_successors=self.successors, address=addr)
         self.successors = new_state._inspect_getattr("sim_successors", self.successors)
+        assert self.successors is not None
 
         # downsizing
         if new_state.supports_inspect:
@@ -183,7 +146,7 @@ class SuccessorsMixin(SimEngine):
 
         return self.successors
 
-    def process_successors(self, successors, **kwargs):  # pylint:disable=unused-argument
+    def process_successors(self, successors, **kwargs):  # pylint:disable=unused-argument,no-self-use
         """
         Implement this function to fill out the SimSuccessors object with the results of stepping state.
 

angr/engines/light/__init__.py

@@ -1,15 +1,23 @@
 from __future__ import annotations
 
 from .data import ArithmeticExpression, SpOffset, RegisterOffset
-from .engine import SimEngineLight, SimEngineLightVEXMixin, SimEngineLightAILMixin, SimEngineLightVEX, SimEngineLightAIL
+from .engine import (
+    SimEngineLight,
+    SimEngineLightVEX,
+    SimEngineLightAIL,
+    SimEngineNostmtVEX,
+    SimEngineNostmtAIL,
+    SimEngineNoexprAIL,
+)
 
 __all__ = (
     "ArithmeticExpression",
-    "SpOffset",
     "RegisterOffset",
     "SimEngineLight",
-    "SimEngineLightVEXMixin",
-    "SimEngineLightAILMixin",
-    "SimEngineLightVEX",
     "SimEngineLightAIL",
+    "SimEngineLightVEX",
+    "SimEngineNoexprAIL",
+    "SimEngineNostmtAIL",
+    "SimEngineNostmtVEX",
+    "SpOffset",
 )

angr/engines/light/data.py

@@ -332,8 +332,8 @@ class ArithmeticExpression:
 class RegisterOffset:
     __slots__ = (
         "_bits",
-        "reg",
         "offset",
+        "reg",
     )
 
     def __init__(self, bits, reg, offset):