angr 9.2.131__py3-none-manylinux2014_aarch64.whl → 9.2.133__py3-none-manylinux2014_aarch64.whl

angr/procedures/definitions/__init__.py

@@ -5,7 +5,7 @@ import os
 import logging
 import inspect
 from collections import defaultdict
-from typing import Optional, Dict, Type, List, TYPE_CHECKING
+from typing import TYPE_CHECKING
 
 import itanium_demangler
 
@@ -569,7 +569,7 @@ class SimSyscallLibrary(SimLibrary):
             mapping = self.syscall_number_mapping[abi]
             if number in mapping:
                 return mapping[number], arch, abi
-        return "sys_%d" % number, arch, None
+        return f"sys_{number}", arch, None
 
     def _apply_numerical_metadata(self, proc, number, arch, abi):
         proc.syscall_number = number

angr/procedures/definitions/linux_kernel.py

@@ -1,6 +1,5 @@
 from __future__ import annotations
 import logging
-from typing import Dict
 
 from angr.sim_type import SimTypeFunction, SimTypePointer, SimTypeLong, SimStruct, SimTypeInt, SimTypeChar, SimTypeBottom, SimTypeFd, SimTypeLongLong
 from angr.procedures import SIM_PROCEDURES as P

angr/procedures/definitions/parse_syscalls_from_local_system.py

@@ -26,7 +26,7 @@ def parse_unistd_include_header(header_path):
 def dump_mapping(abi, mapping):
     print(f'\nlib.add_number_mapping_from_dict("{abi}", {{')
     for num in sorted(mapping):
-        print('    %d: "%s",' % (num, mapping[num]))
+        print(f'    {num}: "{mapping[num]}",')
     print('})')
 
 def main():

angr/procedures/definitions/parse_win32json.py

@@ -1,7 +1,6 @@
 # Based on https://github.com/dfraze/binja_winmd/blob/main/main.py. Thank you, Dustin Fraze!
 from __future__ import annotations
 
-from typing import Set
 import json
 import codecs
 import sys

angr/procedures/ntdll/exceptions.py

@@ -44,7 +44,7 @@ class KiUserExceptionDispatcher(angr.SimProcedure):
             elif disposition == 3:
                 raise angr.errors.SimUnsupportedError("Exception disposition ExceptionCollidedUnwind is unsupported")
             else:
-                raise angr.errors.SimError("Bad exception disposition %d" % disposition)
+                raise angr.errors.SimError(f"Bad exception disposition {disposition}")
 
         # todo: check cur_ptr against stack bounds
         cur_ptr = self.cur_ptr

angr/procedures/stubs/format_parser.py

@@ -323,11 +323,11 @@ class FormatSpecifier:
     """
 
     __slots__ = (
-        "string",
-        "size",
-        "signed",
         "length_spec",
         "pad_chr",
+        "signed",
+        "size",
+        "string",
     )
 
     def __init__(self, string, length_spec, pad_chr, size, signed):

angr/procedures/win32/dynamic_loading.py

@@ -59,7 +59,7 @@ class GetProcAddress(angr.SimProcedure):
         if claripy.is_true(name_addr < 0x10000):
             # this matches the bogus name specified in the loader...
             ordinal = self.state.solver.eval(name_addr)
-            name = "ordinal.%d.%s" % (ordinal, obj.provides)
+            name = f"ordinal.{ordinal}.{obj.provides}"
         else:
             name = self.state.mem[name_addr].string.concrete.decode("utf-8")
 

angr/protos/__init__.py

@@ -14,9 +14,9 @@ from . import xrefs_pb2
 from . import variables_pb2
 
 __all__ = (
-    "primitives_pb2",
-    "function_pb2",
     "cfg_pb2",
-    "xrefs_pb2",
+    "function_pb2",
+    "primitives_pb2",
     "variables_pb2",
+    "xrefs_pb2",
 )

angr/sim_manager.py

@@ -10,6 +10,7 @@ from types import TracebackType
 import claripy
 import mulpyplexer
 
+from .exploration_techniques import ExplorationTechnique, Veritesting, Threading, Explorer, Suggestions
 from .misc.hookset import HookSet
 from .misc.ux import once
 from .misc.picklable_lock import PicklableLock
@@ -154,10 +155,10 @@ class SimulationManager:
                 self.use_technique(t)
 
     def __repr__(self):
-        stashes_repr = ", ".join(("%d %s" % (len(v), k)) for k, v in self._stashes.items() if len(v) != 0)
+        stashes_repr = ", ".join((f"{len(v)} {k}") for k, v in self._stashes.items() if len(v) != 0)
         if not stashes_repr:
             stashes_repr = "all stashes empty"
-        errored_repr = " (%d errored)" % len(self.errored) if self.errored else ""
+        errored_repr = f" ({len(self.errored)} errored)" if self.errored else ""
         return f"<SimulationManager with {stashes_repr}{errored_repr}>"
 
     def __getattr__(self, item):
@@ -968,6 +969,3 @@ class ErrorRecord:
 
     def __eq__(self, other):
         return self is other or self.state is other
-
-
-from .exploration_techniques import ExplorationTechnique, Veritesting, Threading, Explorer, Suggestions

angr/sim_state.py

@@ -5,12 +5,14 @@ import functools
 import itertools
 import logging
 import weakref
-from typing import TypeVar, TYPE_CHECKING
+from typing import Any, TypeVar, TYPE_CHECKING, Generic
+from collections.abc import Callable
 
 import archinfo
-import claripy
 from archinfo import Arch
 from archinfo.arch_soot import SootAddressDescriptor
+import claripy
+from cle import Clemory
 
 from . import sim_options as o
 from .errors import SimMergeError, SimValueError, SimStateError, SimSolverModeError
@@ -27,6 +29,8 @@ if TYPE_CHECKING:
     from .state_plugins.inspect import SimInspector
     from .state_plugins.jni_references import SimStateJNIReferences
     from .state_plugins.scratch import SimStateScratch
+    from angr.project import Project
+    from angr.simos.javavm import SimJavaVM
 
 
 l = logging.getLogger(name=__name__)
@@ -48,9 +52,12 @@ merge_counter = itertools.count()
 
 _complained_se = False
 
+IPTypeConc = TypeVar("IPTypeConc")
+IPTypeSym = TypeVar("IPTypeSym")
+
 
 # pylint: disable=not-callable
-class SimState(PluginHub):
+class SimState(Generic[IPTypeConc, IPTypeSym], PluginHub[SimStatePlugin]):
     """
     The SimState represents the state of a program, including its memory, registers, and so forth.
 
@@ -88,23 +95,23 @@ class SimState(PluginHub):
 
     def __init__(
         self,
-        project=None,
-        arch=None,
-        plugins=None,
-        mode=None,
-        options=None,
-        add_options=None,
-        remove_options=None,
-        special_memory_filler=None,
-        os_name=None,
-        plugin_preset="default",
-        cle_memory_backer=None,
-        dict_memory_backer=None,
-        permissions_map=None,
-        default_permissions=3,
-        stack_perms=None,
-        stack_end=None,
-        stack_size=None,
+        project: Project | None = None,
+        arch: Arch | None = None,
+        plugins: dict[str, SimStatePlugin] | None = None,
+        mode: str | None = None,
+        options: set[str] | list[str] | SimStateOptions | None = None,
+        add_options: set[str] | None = None,
+        remove_options: set[str] | None = None,
+        special_memory_filler: Callable[[str, int, int, SimState], Any] | None = None,
+        os_name: str | None = None,
+        plugin_preset: str = "default",
+        cle_memory_backer: Clemory | None = None,
+        dict_memory_backer: dict[int, bytes] | None = None,
+        permissions_map: dict[tuple[int, int], int] | None = None,
+        default_permissions: int = 3,
+        stack_perms: int | None = None,
+        stack_end: int | None = None,
+        stack_size: int | None = None,
         regioned_memory_cls=None,
         **kwargs,
     ):
@@ -118,7 +125,9 @@ class SimState(PluginHub):
         self._is_java_jni_project = self.project and self.project.is_java_jni_project
 
         # Arch
-        if self._is_java_jni_project:
+        if self._is_java_jni_project and project is not None:
+            if TYPE_CHECKING:
+                assert isinstance(project.simos, SimJavaVM)
             self._arch = {"soot": project.arch, "vex": project.simos.native_simos.arch}
             # This flag indicates whether the current ip is a native address or
             # a soot address descriptor.
@@ -177,6 +186,7 @@ class SimState(PluginHub):
             # we have no choice but to use the 'default' plugin preset.
             if self.plugin_preset is None:
                 self.use_plugin_preset("default")
+            assert self.plugin_preset is not None
 
             # Determine memory backend
             if self._is_java_project and not self._is_java_jni_project:
@@ -186,16 +196,14 @@ class SimState(PluginHub):
             elif o.ABSTRACT_MEMORY in self.options:
                 # We use SimAbstractMemory in static mode.
                 # Convert memory_backer into 'global' region.
-                if cle_memory_backer is not None:
-                    cle_memory_backer = {"global": cle_memory_backer}
-                if dict_memory_backer is not None:
-                    dict_memory_backer = {"global": dict_memory_backer}
+                cle_memory_backer_map = {"global": cle_memory_backer} if cle_memory_backer is not None else None
+                dict_memory_backer_map = {"global": dict_memory_backer} if dict_memory_backer is not None else None
 
                 # TODO: support permissions backer in SimAbstractMemory
                 sim_memory_cls = self.plugin_preset.request_plugin("abs_memory")
                 sim_memory = sim_memory_cls(
-                    cle_memory_backer=cle_memory_backer,
-                    dict_memory_backer=dict_memory_backer,
+                    cle_memory_backer=cle_memory_backer_map,
+                    dict_memory_backer=dict_memory_backer_map,
                     memory_id="mem",
                     regioned_memory_cls=regioned_memory_cls,
                 )
@@ -234,6 +242,7 @@ class SimState(PluginHub):
             # Same as for 'memory' plugin.
             if self.plugin_preset is None:
                 self.use_plugin_preset("default")
+            assert self.plugin_preset is not None
 
             # Get register endness
             if self._is_java_jni_project:
@@ -322,17 +331,6 @@ class SimState(PluginHub):
         # TODO: This shouldn't be access directly.
         return self._active_plugins
 
-    @property
-    def se(self):
-        """
-        Deprecated alias for `solver`
-        """
-        global _complained_se
-        if not _complained_se:
-            _complained_se = True
-            l.critical("The name state.se is deprecated; please use state.solver.")
-        return self.get_plugin("solver")
-
     @property
     def ip(self):
         """
@@ -348,7 +346,7 @@ class SimState(PluginHub):
         self.regs.ip = val
 
     @property
-    def _ip(self):
+    def _ip(self) -> IPTypeSym:
         """
         Get the instruction pointer expression without triggering SimInspect breakpoints or generating SimActions.
 
@@ -360,7 +358,7 @@ class SimState(PluginHub):
             raise TypeError(str(e)) from e
 
     @_ip.setter
-    def _ip(self, val):
+    def _ip(self, val: IPTypeSym | IPTypeConc):
         """
         Set the instruction pointer without triggering SimInspect breakpoints or generating SimActions.
 
@@ -373,7 +371,7 @@ class SimState(PluginHub):
             raise TypeError(str(e)) from e
 
     @property
-    def addr(self):
+    def addr(self) -> IPTypeConc:
         """
         Get the concrete address of the instruction pointer, without triggering SimInspect breakpoints or generating
         SimActions. An integer is returned, or an exception is raised if the instruction pointer is symbolic.
@@ -600,7 +598,7 @@ class SimState(PluginHub):
 
         if merge_conditions is None:
             # TODO: maybe make the length of this smaller? Maybe: math.ceil(math.log(len(others)+1, 2))
-            merge_flag = claripy.BVS("state_merge_%d" % next(merge_counter), 16)
+            merge_flag = claripy.BVS(f"state_merge_{next(merge_counter)}", 16)
             merge_values = range(len(others) + 1)
             merge_conditions = [merge_flag == b for b in merge_values]
         else:

angr/sim_state_options.py

@@ -11,11 +11,11 @@ class StateOption:
     """
 
     __slots__ = (
-        "name",
-        "types",
+        "_one_type",
         "default",
         "description",
-        "_one_type",
+        "name",
+        "types",
     )
 
     def __init__(self, name, types, default=_NO_DEFAULT_VALUE, description=None):

angr/sim_type.py

@@ -428,7 +428,7 @@ class SimTypeInt(SimTypeReg):
             name = "unsigned " + name
 
         try:
-            return name + " (%d bits)" % self.size
+            return f"{name} ({self.size} bits)"
         except ValueError:
             return name
 
@@ -516,7 +516,7 @@ class SimTypeFixedSizeInt(SimTypeInt):
             name = "u" + name
 
         try:
-            return name + " (%d bits)" % self.size
+            return f"{name} ({self.size} bits)"
         except ValueError:
             return name
 
@@ -535,6 +535,11 @@ class SimTypeInt256(SimTypeFixedSizeInt):
     _fixed_size = 256
 
 
+class SimTypeInt512(SimTypeFixedSizeInt):
+    _base_name = "int512_t"
+    _fixed_size = 512
+
+
 class SimTypeChar(SimTypeReg):
     """
     SimTypeChar is a type that specifies a character;
@@ -773,12 +778,8 @@ class SimTypePointer(SimTypeReg):
         return out
 
     def _init_str(self):
-        return "%s(%s%s, offset=%d)" % (
-            self.__class__.__name__,
-            self.pts_to._init_str(),
-            (f', label="{self.label}"') if self.label is not None else "",
-            self.offset,
-        )
+        label_str = f', label="{self.label}"' if self.label is not None else ""
+        return f"{self.__class__.__name__}({self.pts_to._init_str()}{label_str}, offset={self.offset})"
 
     def copy(self):
         return SimTypePointer(self.pts_to, label=self.label, offset=self.offset)
@@ -1277,7 +1278,7 @@ class SimTypeLength(SimTypeLong):
         return self._arch.bits
 
     def _init_str(self):
-        return "%s(size=%d)" % (self.__class__.__name__, self.size)
+        return f"{self.__class__.__name__}(size={self.size})"
 
     def copy(self):
         return SimTypeLength(signed=self.signed, addr=self.addr, length=self.length, label=self.label)
@@ -1317,7 +1318,7 @@ class SimTypeFloat(SimTypeReg):
         return "float"
 
     def _init_str(self):
-        return "%s(size=%d)" % (self.__class__.__name__, self.size)
+        return f"{self.__class__.__name__}(size={self.size})"
 
     def copy(self):
         return SimTypeFloat(self.size)
@@ -1505,7 +1506,7 @@ class SimStruct(NamedTypeMixin, SimType):
             raise TypeError(f"Can't store struct of type {type(value)}")
 
         if len(value) != len(self.fields):
-            raise ValueError("Passed bad values for %s; expected %d, got %d" % (self, len(self.offsets), len(value)))
+            raise ValueError(f"Passed bad values for {self}; expected {len(self.offsets)}, got {len(value)}")
 
         for field, offset in self.offsets.items():
             ty = self.fields[field]
@@ -1788,7 +1789,7 @@ class SimCppClass(SimStruct):
             raise TypeError(f"Can't store struct of type {type(value)}")
 
         if len(value) != len(self.fields):
-            raise ValueError("Passed bad values for %s; expected %d, got %d" % (self, len(self.offsets), len(value)))
+            raise ValueError(f"Passed bad values for {self}; expected {len(self.offsets)}, got {len(value)}")
 
         for field, offset in self.offsets.items():
             ty = self.fields[field]
@@ -3502,7 +3503,7 @@ def parse_cpp_file(cpp_decl, with_param_names: bool = False):
             idx = s.find(",", last_pos)
             if idx == -1:
                 break
-            arg_name = "a%d" % i
+            arg_name = f"a{i}"
             i += 1
             s = s[:idx] + " " + arg_name + s[idx:]
             last_pos = idx + len(arg_name) + 1 + 1
@@ -3511,7 +3512,7 @@ def parse_cpp_file(cpp_decl, with_param_names: bool = False):
         idx = s.find(")", last_pos)
         # TODO: consider the case where there are one or multiple spaces between ( and )
         if idx != -1 and s[idx - 1] != "(":
-            arg_name = "a%d" % i
+            arg_name = f"a{i}"
             s = s[:idx] + " " + arg_name + s[idx:]
 
     # CppHeaderParser does not like missing function body

angr/sim_variable.py

@@ -13,16 +13,18 @@ if TYPE_CHECKING:
 
 class SimVariable(Serializable):
     __slots__ = [
+        "candidate_names",
+        "category",
         "ident",
         "name",
         "region",
-        "category",
         "renamed",
-        "candidate_names",
         "size",
     ]
 
-    def __init__(self, ident=None, name=None, region: int | None = None, category=None, size: int | None = None):
+    def __init__(
+        self, size: int, ident: str | None = None, name: str | None = None, region: int | None = None, category=None
+    ):
         """
         :param ident: A unique identifier provided by user or the program. Usually a string.
         :param str name: Name of this variable.
@@ -85,9 +87,9 @@ class SimVariable(Serializable):
 
 
 class SimConstantVariable(SimVariable):
-    __slots__ = ["value", "_hash"]
+    __slots__ = ["_hash", "value"]
 
-    def __init__(self, ident=None, value=None, region=None, size=None):
+    def __init__(self, size: int, ident=None, value=None, region=None):
         super().__init__(ident=ident, region=region, size=size)
         self.value = value
         self._hash = None
@@ -120,23 +122,23 @@ class SimConstantVariable(SimVariable):
 
 
 class SimTemporaryVariable(SimVariable):
-    __slots__ = ["tmp_id", "_hash"]
+    __slots__ = ["_hash", "tmp_id"]
 
-    def __init__(self, tmp_id, size=None):
+    def __init__(self, tmp_id: int, size: int):
         SimVariable.__init__(self, size=size)
 
         self.tmp_id = tmp_id
         self._hash = None
 
     def __repr__(self):
-        return "<tmp %d>" % (self.tmp_id,)
+        return f"<tmp {self.tmp_id}>"
 
     def loc_repr(self, arch):
         return f"tmp #{self.tmp_id}"
 
     def __hash__(self):
         if self._hash is None:
-            self._hash = hash("tmp_%d" % (self.tmp_id))
+            self._hash = hash(f"tmp_{self.tmp_id}")
         return self._hash
 
     def __eq__(self, other):
@@ -162,18 +164,18 @@ class SimTemporaryVariable(SimVariable):
 
     @classmethod
     def parse_from_cmessage(cls, cmsg, **kwargs):
-        obj = cls(cmsg.tmp_id)
+        obj = cls(cmsg.tmp_id, cmsg.base.size)
         obj._from_base(cmsg)
         return obj
 
 
 class SimRegisterVariable(SimVariable):
-    __slots__ = ["reg", "_hash"]
+    __slots__ = ["_hash", "reg"]
 
-    def __init__(self, reg_offset, size, ident=None, name=None, region=None, category=None):
+    def __init__(self, reg_offset: int, size: int, ident=None, name=None, region=None, category=None):
         SimVariable.__init__(self, ident=ident, name=name, region=region, category=category, size=size)
 
-        self.reg: int = reg_offset
+        self.reg = reg_offset
         self._hash: int | None = None
 
     @property
@@ -234,9 +236,9 @@ class SimRegisterVariable(SimVariable):
 
 
 class SimMemoryVariable(SimVariable):
-    __slots__ = ["addr", "_hash"]
+    __slots__ = ["_hash", "addr"]
 
-    def __init__(self, addr, size, ident=None, name=None, region=None, category=None):
+    def __init__(self, addr, size: int, ident=None, name=None, region=None, category=None):
         SimVariable.__init__(self, ident=ident, name=name, region=region, category=category, size=size)
 
         self.addr = addr
@@ -249,12 +251,10 @@ class SimMemoryVariable(SimVariable):
         self._hash = None
 
     def __repr__(self):
-        size = "%d" % self.size if type(self.size) is int else f"{self.size}"
-
         if type(self.addr) is int:
-            s = f"<{self.name}: {self.region}-Mem {self.addr:#x} {size}>"
+            s = f"<{self.name}: {self.region}-Mem {self.addr:#x} {self.size}>"
         else:
-            s = f"<{self.name}: {self.region}-Mem {self.addr} {size}>"
+            s = f"<{self.name}: {self.region}-Mem {self.addr} {self.size}>"
 
         return s
 
@@ -309,11 +309,13 @@ class SimMemoryVariable(SimVariable):
 class SimStackVariable(SimMemoryVariable):
     __slots__ = (
         "base",
-        "offset",
         "base_addr",
+        "offset",
     )
 
-    def __init__(self, offset, size, base="sp", base_addr=None, ident=None, name=None, region=None, category=None):
+    def __init__(
+        self, offset: int, size: int, base="sp", base_addr=None, ident=None, name=None, region=None, category=None
+    ):
         if isinstance(offset, int) and offset > 0x1000000:
             # I don't think any positive stack offset will be greater than that...
             # convert it to a negative number
@@ -329,8 +331,6 @@ class SimStackVariable(SimMemoryVariable):
         self.base_addr = base_addr
 
     def __repr__(self):
-        size = "%d" % self.size if type(self.size) is int else f"{self.size}"
-
         prefix = f"{self.name}(stack)" if self.name is not None else "Stack"
         ident = f"[{self.ident}]" if self.ident else ""
         region_str = hex(self.region) if isinstance(self.region, int) else self.region
@@ -343,9 +343,9 @@ class SimStackVariable(SimMemoryVariable):
             else:
                 offset = ""
 
-            s = f"<{region_str}{ident}|{prefix} {self.base}{offset}, {size} B>"
+            s = f"<{region_str}{ident}|{prefix} {self.base}{offset}, {self.size} B>"
         else:
-            s = f"<{region_str}{ident}|{prefix} {self.base}{self.addr}, {size} B>"
+            s = f"<{region_str}{ident}|{prefix} {self.base}{self.addr}, {self.size} B>"
 
         return s
 
@@ -422,16 +422,15 @@ class SimVariableSet(collections.abc.MutableSet):
         # For the sake of performance, we have another set that stores memory addresses of memory_variables
         self.memory_variable_addresses = set()
 
-    def add(self, item):  # pylint:disable=arguments-differ
-        if type(item) is SimRegisterVariable:
-            if not self.contains_register_variable(item):
-                self.add_register_variable(item)
-        elif type(item) is SimMemoryVariable:
-            if not self.contains_memory_variable(item):
-                self.add_memory_variable(item)
+    def add(self, value):
+        if type(value) is SimRegisterVariable:
+            if not self.contains_register_variable(value):
+                self.add_register_variable(value)
+        elif type(value) is SimMemoryVariable:
+            if not self.contains_memory_variable(value):
+                self.add_memory_variable(value)
         else:
-            # TODO:
-            raise Exception("WTF")
+            assert False, "Unknown type"
 
     def add_register_variable(self, reg_var):
         self.register_variables.add(reg_var)
@@ -443,16 +442,15 @@ class SimVariableSet(collections.abc.MutableSet):
         for i in range(mem_var.size):
             self.memory_variable_addresses.add(base_address + i)
 
-    def discard(self, item):  # pylint:disable=arguments-differ
-        if type(item) is SimRegisterVariable:
-            if self.contains_register_variable(item):
-                self.discard_register_variable(item)
-        elif isinstance(item, SimMemoryVariable):
-            if self.contains_memory_variable(item):
-                self.discard_memory_variable(item)
+    def discard(self, value):
+        if type(value) is SimRegisterVariable:
+            if self.contains_register_variable(value):
+                self.discard_register_variable(value)
+        elif isinstance(value, SimMemoryVariable):
+            if self.contains_memory_variable(value):
+                self.discard_memory_variable(value)
         else:
-            # TODO:
-            raise Exception("")
+            assert False, "Unknown type"
 
     def discard_register_variable(self, reg_var):
         self.register_variables.remove(reg_var)
@@ -528,5 +526,4 @@ class SimVariableSet(collections.abc.MutableSet):
             # TODO: Make it better!
             return self.contains_memory_variable(item)
 
-        __import__("ipdb").set_trace()
-        raise Exception("WTF is this variable?")
+        assert False, "WTF is this variable?"

angr/simos/__init__.py

@@ -34,12 +34,12 @@ register_simos("snimmuc_nxp", SimSnimmucNxp)
 
 
 __all__ = (
-    "SimOS",
-    "SimUserland",
-    "SimLinux",
     "SimCGC",
-    "SimWindows",
     "SimJavaVM",
+    "SimLinux",
+    "SimOS",
     "SimSnimmucNxp",
+    "SimUserland",
+    "SimWindows",
     "os_mapping",
 )

angr/simos/cgc.py

@@ -50,7 +50,7 @@ class SimCGC(SimUserland):
 
         # Set up the flag page
         if flag_page is None:
-            flag_page = [s.solver.BVS("cgc-flag-byte-%d" % i, 8, key=("flag", i), eternal=True) for i in range(0x1000)]
+            flag_page = [s.solver.BVS(f"cgc-flag-byte-{i}", 8, key=("flag", i), eternal=True) for i in range(0x1000)]
         elif type(flag_page) is bytes:
             flag_page = [claripy.BVV(c, 8) for c in flag_page]
         elif type(flag_page) is list:

angr/simos/simos.py

@@ -214,7 +214,7 @@ class SimOS:
                 empty_bools = [((val >> (x * 2)) & 3) == 3 for x in range(8)]
                 tag_chars = [claripy.BVV(0 if x else 1, 8) for x in empty_bools]
                 for i, tag in enumerate(tag_chars):
-                    setattr(state.regs, "fpu_t%d" % i, tag)
+                    setattr(state.regs, f"fpu_t{i}", tag)
             elif reg in ("fiseg", "fioff", "foseg", "fooff", "fop"):
                 pass
             elif reg == "mxcsr":

angr/simos/userland.py

@@ -149,7 +149,7 @@ class SimUserland(SimOS):
                 raise AngrUnsupportedSyscallError(f"{self.name} does not have a library of syscalls implemented")
             proc = P["stubs"]["syscall"]()
         elif not allow_unsupported and not self.syscall_library.has_implementation(number, self.arch, abilist):
-            raise AngrUnsupportedSyscallError("No implementation for syscall %d" % number)
+            raise AngrUnsupportedSyscallError(f"No implementation for syscall {number}")
         else:
             proc = self.syscall_library.get(number, self.arch, abilist)