@hybridlabor-api/bdb-hardware-pcb 0.1.0

package/skills/pcb-layout-routing-automation/SKILL.md

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+---
+name: pcb-layout-routing-automation
+description: "Floorplanning, component placement rules, high-speed differential pair routing, return path continuity, thermal via arrays, and keepout enforcement for KiCad PCB layouts. Use when placing footprints, routing traces, creating ground planes, or managing thermal/RF keepouts."
+category: engineering-hardware
+compatibility: "Python 3.10+, kicad-cli 8+, mcp:kicad"
+---
+
+# PCB Layout & Routing Automation
+
+## 1. Overview and Core Philosophy
+
+PCB layout is applied electromagnetic physics and thermal engineering. A schematic guarantees logical connectivity; layout determines whether the physical circuit functions, radiates excessive electromagnetic interference (EMI), overheats, or fails in manufacturing.
+
+This skill directs automated agents through spatial floorplanning, critical trace routing, return path management, thermal copper geometry, and mechanical keepout enforcement.
+
+---
+
+## 2. Floorplanning & Component Placement Hierarchy
+
+Component placement dictates $90\%$ of routing success. Random or purely geometric placement is strictly prohibited. The agent must place components following a strict signal flow and thermal hierarchy:
+
+```
+[External Connectors (USB, Barrel, Headers)]
+   |  (< 2.0mm)
+   v
+[TVS / ESD Protection Diodes]  --> Lowest inductance path to Chassis/GND
+   |
+   v
+[Power Conversion (Buck / LDO)]  --> Perimeter placement with thermal copper
+   |
+   v
+[Core Microcontroller / FPGA]   --> Central placement, decoupling < 1.5mm
+   |
+   +---> [High-Speed Busses (USB, SPI, RAM)]  --> Direct point-to-point
+   |
+   +---> [Sensitive Analog Front-End (ADC)]   --> Isolated quiet zone
+```
+
+### 2.1 Placement Rules of Engagement
+1. **Decoupling Capacitor Placement Rule**:
+   - Every bypass capacitor ($100\text{nF}$) must be placed on the same layer as the IC, with its pad located within **$1.5\text{mm}$** of the power pin.
+   - Trace sequence: `Power Rail Via -> Capacitor Pad -> IC Power Pin`. The capacitor must sit directly in the high-frequency current path.
+2. **Crystal Oscillator Placement**:
+   - Crystals ($12\text{MHz}$, $16\text{MHz}$, $32.768\text{kHz}$) and their load capacitors must be placed within **$3.0\text{mm}$** of the MCU oscillator pins.
+   - Surround oscillator traces with a ground guard ring; do not route any other signals under or adjacent to the oscillator.
+3. **Switch-Mode Power Supply (SMPS) Loop Minimization**:
+   - The high-frequency switching loop formed by the input capacitor ($C_{in}$), switching FETs, inductor ($L$), and catch diode must have minimal enclosed loop area to prevent magnetic dipole radiation:
+     $$V_{radiated} \propto \frac{dI}{dt} \cdot \text{Loop Area}$$
+4. **Thermal Partitioning**:
+   - Power dissipating devices ($P_D > 0.5\text{W}$) must be positioned at least $10\text{mm}$ away from temperature-sensitive components (voltage references, analog sensors, crystal oscillators).
+
+---
+
+## 3. High-Speed Routing & Return Path Physics
+
+### 3.1 Return Path Continuity (The Fundamental Law of High Speed)
+At frequencies above $100\text{kHz}$, return current ceases following the path of lowest DC resistance and instead follows the **path of lowest loop inductance**, traveling directly beneath the signal trace in the adjacent ground plane:
+
+```
+Layer 1 (Signal Trace):    =======================================>
+                                   | H = 0.2mm (Prepreg)
+Layer 2 (Solid GND Plane): <--------------------------------------- (Return Current Mirror)
+```
+
+#### Plane Split Prohibition
+- **STRICT PROHIBITION**: A signal trace must **NEVER** cross a split, slot, or void in its underlying reference plane.
+- Crossing a split forces return current to divert around the perimeter of the void, creating a large loop antenna that radiates EMI and induces massive inductive ringing:
+  $$\Delta V = L_{loop} \frac{dI}{dt}$$
+- If a high-speed signal must change layers (e.g., Layer 1 to Layer 4 in a 4-layer board), a **Ground Return Stitching Via** must be placed within **$0.5\text{mm}$** of the signal via to bridge the return current between reference planes.
+
+### 3.2 Differential Pair Routing (USB 90Ω, Ethernet 100Ω)
+1. **Symmetric Coupling**:
+   - Maintain constant trace width ($W$) and edge-to-edge separation ($S$) across the entire run.
+   - Do not separate differential traces around vias or components; neck down both traces symmetrically if passing through tight BGA ball grids.
+2. **Phase / Skew Matching**:
+   - The two complementary conductors ($D+$ and $D-$) must arrive at the receiver simultaneously.
+   - Length difference between legs must satisfy:
+     $$\Delta L \le 0.1\text{mm} \quad (\approx 0.6\text{ps skew in FR-4})$$
+   - Implement small serpentine delay bumps located as close as possible to the point where the length mismatch originated (e.g., outside a bend).
+3. **Corner Geometry**:
+   - All trace bends must use **$45^\circ$ chamfers** or smooth circular arcs.
+   - **$90^\circ$ corners are strictly prohibited**: they create localized capacitive impedance dips ($Z_0$ drops by $10-15\%$) and act as acid traps during PCB chemical etching.
+
+---
+
+## 4. Thermal Management & Copper Plane Architecture
+
+### 4.1 Thermal Via Arrays
+For components with exposed thermal pads (QFN, DFN, PowerSO):
+- Drop an array of thermal vias directly inside the thermal pad footprint.
+- Via drill diameter: $0.3\text{mm}$ (avoids solder wicking during reflow).
+- Via pitch: $0.6\text{mm}$ grid spacing.
+- Thermal vias must connect directly to internal and bottom ground copper planes to distribute heat.
+
+### 4.2 Thermal Relief on Plane Connections
+- Pads directly connected to large copper planes must have **thermal relief spokes** (typically 4 orthogonal spokes, spoke width $0.35\text{mm} - 0.50\text{mm}$).
+- Direct solid pad-to-plane connections without thermal relief sink excessive heat away from soldering irons and reflow ovens, resulting in cold solder joints.
+- *Exception*: Small surface mount decoupling capacitors may use direct solid connections to minimize parasitic inductance, provided solder paste volumes are calibrated.
+
+### 4.3 Perimeter Stitching Via Fencing
+- Board edges emit fringing electromagnetic fields.
+- Along the entire perimeter of the PCB ground plane, place a continuous row of ground stitching vias spaced at:
+  $$d_{via} \le \frac{\lambda_{min}}{20}$$
+  For a $2.4\text{GHz}$ system ($\lambda \approx 125\text{mm}$), via spacing $d \le 3.0\text{mm}$.
+
+---
+
+## 5. Keepout Envelopes & Safety Isolation
+
+### 5.1 RF Antenna Keepouts
+- For onboard PCB trace antennas (meandered inverted-F) or ceramic chip antennas:
+  - Maintain a complete **No-Copper Keepout** across **ALL LAYERS** (Top, Bottom, and all Internal Planes) directly beneath and around the antenna element.
+  - No ground pours, traces, or mounting screws may enter the manufacturer's specified antenna clearance zone (typically $\ge 5.0\text{mm}$).
+
+### 5.2 High-Voltage Creepage and Clearance (IEC 62368)
+- For circuits interfacing with AC mains ($120\text{V} / 230\text{V}$):
+  - Minimum clearance through air: $\ge 3.0\text{mm}$.
+  - Minimum creepage along surface: $\ge 5.0\text{mm}$.
+  - Milled physical isolation slots ($1.5\text{mm}$ wide) must be cut into the board dielectric (`Edge.Cuts`) between primary and secondary domains to prevent surface carbon tracking.
+
+---
+
+## 6. Layout Automation via Konnect MCP and Freerouting
+
+When executing automated layout in the AOS pipeline:
+
+1. **Initialize Layout Session via Konnect**:
+   - Activate the `pcb_layout` and `pcb_routing` toolsets in Konnect.
+   - Place footprints according to the floorplanning hierarchy.
+2. **Export Specctra Design (`.dsn`)**:
+   - Emit the board geometry, netclasses, and keepouts to Specctra format:
+     ```bash
+     kicad-cli pcb export dsn -o board.dsn board.kicad_pcb
+     ```
+3. **Execute Routing Engine**:
+   - Run Freerouting headless:
+     ```bash
+     java -jar freerouting.jar -de board.dsn -do board.ses
+     ```
+4. **Import Session (`.ses`) and Run Ground Pour**:
+   - Import the routed session back into `.kicad_pcb`.
+   - Re-fill all copper zones (`B` in KiCad or via `kicad-cli`).
+
+---
+
+## 7. Negative Constraints (Anti-Slop Directives)
+
+- **DO NOT** use $90^\circ$ trace bends anywhere on the PCB. Always use $45^\circ$ miters or circular arcs.
+- **DO NOT** route high-speed digital or analog traces across splits in underlying reference planes.
+- **DO NOT** place decoupling capacitors farther than $1.5\text{mm}$ from the target IC power pin.
+- **DO NOT** omit ground return stitching vias when high-speed signals transition layers.
+- **DO NOT** route copper or traces within the specified keepout zone of an RF antenna.
+- **DO NOT** connect component pads to solid copper planes without thermal relief spokes, unless explicitly designated as high-current low-inductance nodes.

package/skills/pcb-validation-dfm-signoff/SKILL.md

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+---
+name: pcb-validation-dfm-signoff
+description: "Automated DRC/ERC verification, SI/PI screening, fab house DFM/DFA compliance, and production release sign-off for KiCad projects. Use when running final design rule checks, auditing manufacturing limits, generating Gerbers/BOM/CPL, or issuing DFM sign-off reports."
+category: engineering-hardware
+compatibility: "Python 3.10+, kicad-cli 8+, mcp:kicad"
+---
+
+# Critical Validation, DFM & Production Sign-Off
+
+## 1. Overview and Core Philosophy
+
+In the AOS release architecture, the validation and sign-off phase is an unforgiving automated gate. No PCB design may be released to fabrication based on visual inspection or LLM self-attestation. 
+
+This skill governs the execution of headless Electrical Rules Checks (ERC), Design Rules Checks (DRC), Signal/Power Integrity (SI/PI) screening, Design for Manufacturing (DFM) verification, Design for Assembly (DFA) verification, and the generation of production-ready manufacturing packages.
+
+---
+
+## 2. Headless DRC / ERC Verification Gate
+
+The agent must execute `kicad-cli` with deterministic exit codes. Any non-zero exit code represents an immediate gate blockage:
+
+### 2.1 Headless ERC Execution
+```bash
+kicad-cli sch erc --exit-code-violations -o reports/erc_report.txt project.kicad_sch
+```
+- **Exit Code 0**: Clean schematic; zero errors, zero unhandled warnings.
+- **Exit Code 1**: Electrical violations detected (unconnected pins, missing `PWR_FLAG`, conflicting output drivers). The pipeline halts immediately.
+
+### 2.2 Headless DRC Execution
+```bash
+kicad-cli pcb drc --exit-code-violations --format json -o reports/drc_report.json board.kicad_pcb
+```
+- Must verify zero unrouted nets, zero clearance violations, zero broken annular rings, and zero thermal spoke disconnections.
+
+---
+
+## 3. Signal & Power Integrity (SI / PI) Pre-Screening
+
+Before releasing copper to manufacturing, the agent must perform first-order SI/PI calculations:
+
+### 3.1 DC IR Drop Estimation
+Calculate the DC voltage drop on power distribution traces to ensure $<3\%$ drop at maximum load:
+$$R_{trace} = \rho \cdot \frac{L}{w \cdot t}$$
+Where:
+- $\rho \approx 1.72 \times 10^{-8} \ \Omega\cdot\text{m}$ (Copper resistivity at $20^\circ\text{C}$).
+- $t = 35\mu\text{m}$ for $1\text{ oz}$ copper.
+- $V_{drop} = I_{peak} \cdot R_{trace}$.
+- *Rule*: On a $+3.3\text{V}$ rail, maximum allowable $V_{drop} \le 0.10\text{V}$ ($3\%$). If $V_{drop} > 0.10\text{V}$, increase trace width or assign to a dedicated copper flood.
+
+### 3.2 Crosstalk Prevention (The 3W Rule)
+- To prevent capacitive and inductive crosstalk between parallel signal traces running longer than $15\text{mm}$:
+  $$\text{Center-to-Center Separation } D \ge 3 \cdot w$$
+  Where $w$ is the trace width. The 3W rule guarantees that mutual coupling drops by $>70\%$, maintaining signal integrity on sensitive analog and clock lines.
+
+---
+
+## 4. Design for Manufacturing (DFM) Rules
+
+The board layout must be benchmarked against standard commercial fabrication house capabilities (e.g., JLCPCB standard, PCBWay 4-layer):
+
+| Metric | Minimum Value | Standard Process | Advanced Process (Cost Factor) |
+|---|---|---|---|
+| **Minimum Trace Width** | $0.127\text{mm}$ ($5\text{ mils}$) | $0.15\text{mm}$ ($6\text{ mils}$) | $0.09\text{mm}$ ($3.5\text{ mils}$) ($1.8\times$) |
+| **Minimum Trace Clearance** | $0.127\text{mm}$ ($5\text{ mils}$) | $0.15\text{mm}$ ($6\text{ mils}$) | $0.09\text{mm}$ ($3.5\text{ mils}$) ($1.8\times$) |
+| **Minimum Drill Size** | $0.20\text{mm}$ ($8\text{ mils}$) | $0.30\text{mm}$ ($12\text{ mils}$) | $0.15\text{mm}$ ($6\text{ mils}$) ($2.5\times$) |
+| **Minimum Annular Ring** | $0.15\text{mm}$ ($6\text{ mils}$) | $0.20\text{mm}$ ($8\text{ mils}$) | $0.10\text{mm}$ ($4\text{ mils}$) ($2.0\times$) |
+| **Solder Mask Bridge (Dam)**| $0.10\text{mm}$ ($4\text{ mils}$) | $0.12\text{mm}$ ($5\text{ mils}$) | $0.08\text{mm}$ ($3\text{ mils}$) |
+| **Board Edge Clearance** | $0.35\text{mm}$ ($14\text{ mils}$) | $0.50\text{mm}$ ($20\text{ mils}$) | $0.25\text{mm}$ ($10\text{ mils}$) |
+| **Silkscreen Text Height** | $0.80\text{mm}$ ($32\text{ mils}$) | $1.00\text{mm}$ ($40\text{ mils}$) | $0.60\text{mm}$ ($24\text{ mils}$) |
+| **Silkscreen Stroke Width** | $0.15\text{mm}$ ($6\text{ mils}$) | $0.18\text{mm}$ ($7\text{ mils}$) | $0.12\text{mm}$ ($5\text{ mils}$) |
+
+### 4.1 Solder Mask Dam Rule
+Between fine-pitch QFP or QFN IC pads (pitch $\le 0.5\text{mm}$):
+- Solder mask dam width must be $\ge 0.10\text{mm}$ to prevent molten solder bridging adjacent pins during automated reflow.
+- If pad spacing does not permit a $0.10\text{mm}$ dam, gang-mask the pads (open single aperture) and ensure solder paste stencil apertures are reduced by $20\%$.
+
+---
+
+## 5. Design for Assembly (DFA) Standards
+
+For automated pick-and-place surface mount assembly (SMT):
+
+### 5.1 Fiducial Marker Placement
+- **Global Fiducials**: The PCB must contain **at least 3 non-collinear fiducial markers** placed on the top surface near the board corners (minimum $5\text{mm}$ from board edges):
+  - Copper Pad: $1.0\text{mm}$ circular copper pad.
+  - Mask Clearance: $2.0\text{mm}$ circular solder mask opening (bare substrate).
+  - Keepout: No traces, vias, or silkscreen within $3.0\text{mm}$ diameter of the center.
+- **Local Fiducials**: Mandatory for high-pin-count fine-pitch components (QFP $\ge 64$ pins, BGA, QFN pitch $\le 0.4\text{mm}$). Place 2 diagonal fiducials outside opposing corners of the footprint.
+
+### 5.2 Component Orientation & Pin-1 Identifiers
+- Every IC, polarized capacitor, diode, and connector must have a distinct, unambiguous Pin-1 / polarity marker on both the silkscreen layer (`F.SilkS`) and fabrication layer (`F.Fab`).
+- Marking standards:
+  - ICs: Solid dot ($\ge 0.5\text{mm}$ diameter) adjacent to Pin 1.
+  - Diodes: Double bar or cathode band aligned with the package cathode line.
+  - Polarized Capacitors: `+` symbol placed adjacent to the anode pad.
+
+---
+
+## 6. Manufacturing Package Generation via `kicad-cli`
+
+When all gates pass, the agent generates the complete fabrication archive:
+
+```bash
+#!/usr/bin/env bash
+set -e
+
+PROJECT="board"
+OUT_DIR="production_artifacts/fabrication"
+mkdir -p "$OUT_DIR/gerbers" "$OUT_DIR/assembly"
+
+echo "--> 1. Exporting Gerber Production Layers..."
+kicad-cli pcb export gerbers \
+    --layers "F.Cu,B.Cu,In1.Cu,In2.Cu,F.Paste,B.Paste,F.SilkS,B.SilkS,F.Mask,B.Mask,Edge.Cuts" \
+    --output "$OUT_DIR/gerbers/" \
+    "$PROJECT.kicad_pcb"
+
+echo "--> 2. Exporting Excellon Drill Files..."
+kicad-cli pcb export drill \
+    --format excellon \
+    --drill-origin absolute \
+    --output "$OUT_DIR/gerbers/" \
+    "$PROJECT.kicad_pcb"
+
+echo "--> 3. Exporting IPC-D-356 Bare-Board Test Netlist..."
+kicad-cli pcb export netlist \
+    --format ipc2581 \
+    --output "$OUT_DIR/assembly/$PROJECT_ipc_test.d356" \
+    "$PROJECT.kicad_pcb"
+
+echo "--> 4. Exporting Centroid / Component Placement List (CPL)..."
+kicad-cli pcb export pos \
+    --format csv \
+    --units mm \
+    --side both \
+    --output "$OUT_DIR/assembly/$PROJECT_cpl.csv" \
+    "$PROJECT.kicad_pcb"
+
+echo "--> 5. Exporting 3D Assembly STEP Model..."
+kicad-cli pcb export step \
+    --subst-models \
+    --output "$OUT_DIR/assembly/$PROJECT.step" \
+    "$PROJECT.kicad_pcb"
+
+echo "--> 6. Packaging Gerber ZIP Archive..."
+cd "$OUT_DIR/gerbers"
+zip -r "../$PROJECT_gerbers.zip" ./*
+cd - > /dev/null
+
+echo "--> Fabrication release artifacts generated successfully."
+```
+
+---
+
+## 7. Formal Sign-Off Deliverable (`DFM_SIGNOFF_REPORT.md`)
+
+The agent emits a signed release report certifying production readiness:
+
+```markdown
+# DFM Production Sign-Off Report
+
+- **Project**: iot-telemetry-node
+- **Sign-Off Date**: 2026-09-14T20:45:00Z
+- **Auditor**: Godmode_Shipping
+- **Target Fabricator**: JLCPCB 4-Layer Standard
+
+## 1. Gate Execution Summary
+| Check | Tool / Engine | Exit Code | Result | Violations |
+|---|---|---|---|---|
+| **Schematic ERC** | `kicad-cli sch erc` | 0 | PASS | 0 Errors, 0 Warnings |
+| **Layout DRC** | `kicad-cli pcb drc` | 0 | PASS | 0 Errors, 0 Warnings |
+| **Unrouted Nets** | `kicad-cli pcb drc` | 0 | PASS | 0 Unconnected Nets |
+| **Signal Integrity (3W)** | AOS SI Analyzer | 0 | PASS | 0 Crosstalk Hazards |
+| **Power Integrity (IR Drop)** | AOS PI Analyzer | 0 | PASS | Max Drop 1.8% on +3V3 |
+| **DFM Clearance Audit** | JLCPCB Standard Rules | 0 | PASS | Min trace 6 mil, min drill 0.3mm |
+| **DFA SMT Verification** | Fiducial & CPL Checker | 0 | PASS | 3 Global Fiducials Verified |
+
+## 2. Release Artifacts Generated
+- `production_artifacts/fabrication/board_gerbers.zip` (SHA256: e3b0c44298fc...)
+- `production_artifacts/fabrication/assembly/board_cpl.csv`
+- `production_artifacts/fabrication/assembly/board_bom.csv`
+- `production_artifacts/fabrication/assembly/board.step`
+
+## 3. Final Production Verdict: APPROVED FOR FABRICATION
+```
+
+---
+
+## 8. Negative Constraints (Anti-Slop Directives)
+
+- **DO NOT** generate Gerber or drill files if `kicad-cli pcb drc` or `kicad-cli sch erc` returns a non-zero exit code.
+- **DO NOT** release a design for automated SMT assembly without at least three non-collinear fiducial markers on the board surface.
+- **DO NOT** permit silkscreen text or polarity marks to overlap exposed copper pads (causes solder dewetting and tombstoning).
+- **DO NOT** use non-standard drill diameters outside the fabricator's standard drill rack without flagging increased tool-change costs.
+- **DO NOT** omit the IPC-D-356 netlist export; flying probe testing requires this netlist to detect electrical opens and shorts before component population.

package/skills/schematic-datasheet-analysis/SKILL.md

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+---
+name: schematic-datasheet-analysis
+description: "Electrical rule auditing, datasheet grounding, pinout validation, power tree tracing, and negative evidence analysis for KiCad schematics. Use when analyzing schematics, auditing pinmux/logic levels, checking component ratings, or validating datasheets."
+category: engineering-hardware
+compatibility: "Python 3.10+, PyMuPDF, kicad-cli, kicad-happy, mcp:kicad"
+---
+
+# Schematic & Datasheet Analysis
+
+## 1. Overview and Core Philosophy
+
+In hardware design, an ungrounded assumption is a hardware failure. Unlike software, where runtime exceptions can be patched in seconds, hardware fabrication defects result in burnt silicon, weeks of PCB re-spin delays, and thousands of dollars in wasted fabrication costs.
+
+This skill embodies the rigorous methodologies established by Seeed Studio's `schematic-analyzer` and `ee-datasheet-master`, adapted for the BDB Agent OS multi-agent hardware pipeline.
+
+### The Iron Rule of Grounded Hardware Analysis
+> **Accuracy and evidence override coverage.** Every electrical claim, pin function, voltage threshold, and decoupling requirement must cite direct evidence from the manufacturer's datasheet (page number, table number, note number). If no direct evidence exists, the agent must report an open verification gap—never invent plausible values.
+
+---
+
+## 2. Datasheet Extraction Pipeline (`ee-datasheet-master` Protocol)
+
+When analyzing an IC datasheet (PDF), the agent must follow a phased, low-latency extraction strategy using `pymupdf` (MuPDF):
+
+```
++-----------------------------------------------------------------------------------------+
+| PHASE 0: Page Hints       -> Structural scan of the table of contents and headings.     |
+| PHASE 1: Info Scan        -> Detect vector text vs scanned bitmap (flag if OCR needed).|
+| PHASE 2: Device Overview  -> Pages 1-2: absolute max ratings, package type, part codes. |
+| PHASE 3: Pin Description  -> Pinout diagrams and pin assignment tables.                 |
+| PHASE 4: Electrical Specs -> DC electrical characteristics, V_IL/V_IH thresholds, timing|
++-----------------------------------------------------------------------------------------+
+```
+
+### 2.1 Python Extraction Script (`datasheet_query.py`)
+```python
+#!/usr/bin/env python3
+"""
+Grounded Datasheet Parameter Extractor using PyMuPDF.
+Extracts pin tables and electrical characteristics with exact page citations.
+"""
+import sys
+import fitz  # PyMuPDF
+import json
+
+def extract_pin_table(pdf_path: str, keyword: str = "Pin Description"):
+    doc = fitz.open(pdf_path)
+    findings = []
+    
+    for page_num in range(len(doc)):
+        page = doc[page_num]
+        text = page.get_text("text")
+        if keyword.lower() in text.lower():
+            tables = page.find_tables()
+            for tab in tables:
+                df = tab.extract()
+                findings.append({
+                    "page": page_num + 1,
+                    "table_header": df[0] if df else [],
+                    "row_count": len(df),
+                    "sample_rows": df[1:5]
+                })
+    return findings
+
+if __name__ == "__main__":
+    if len(sys.argv) < 2:
+        print("Usage: python3 datasheet_query.py <datasheet.pdf>")
+        sys.exit(1)
+    results = extract_pin_table(sys.argv[1])
+    print(json.dumps(results, indent=2))
+```
+
+---
+
+## 3. Systematic Electrical Verification Disciplines
+
+### 3.1 Absolute Maximum Ratings & The 80/70 Derating Rule
+Components must never be operated near their absolute maximum ratings. The agent must enforce conservative engineering derating:
+- **Voltage Derating (80% Rule)**: Working voltage must not exceed $80\%$ of rated breakdown voltage ($V_{applied} \le 0.8 \cdot V_{max}$).
+  - *Example*: Ceramic capacitors on a $+12\text{V}$ rail must be rated for at least $16\text{V}$, preferably $25\text{V}$ (due to Class II ceramic DC bias capacitance drop).
+- **Power & Current Derating (70% Rule)**: Continuous current and power dissipation must not exceed $70\%$ of rated package capacity ($P_{actual} \le 0.7 \cdot P_{rated}$).
+  - *Linear Regulator Thermal Check*:
+    $$P_D = (V_{in} - V_{out}) \cdot I_{load}$$
+    $$T_J = T_A + P_D \cdot \theta_{JA}$$
+    If $T_J > 105^\circ\text{C}$ at $T_A = 45^\circ\text{C}$, the design is flagged as a thermal failure.
+
+### 3.2 Logic Level Compatibility & Signal Interfacing
+Direct connections between mixed-voltage domains are strictly audited:
+- **Drive Compatibility Condition**:
+  $$V_{OH,min} (\text{Driver}) > V_{IH,min} (\text{Receiver})$$
+  $$V_{OL,max} (\text{Driver}) < V_{IL,max} (\text{Receiver})$$
+- Flag any $5\text{V}$ output connected directly to a $3.3\text{V}$ input unless the receiving pin is explicitly certified as "5V Tolerant" in the datasheet pin description table.
+
+### 3.3 Pinmux & Active-Low Assertions
+- **Active-Low Signals**: Pins designated with an overbar, leading tilde, or hash (e.g., `~{RESET}`, `nCS`, `RESET_N`) must have an explicit external pull-up resistor ($4.7\text{k}\Omega - 10\text{k}\Omega$) unless internal pull-ups are confirmed active during boot in the datasheet.
+- **Open-Drain Busses (I2C / SMBus)**: Both `SDA` and `SCL` lines must have physical pull-up resistors to the bus $V_{DD}$. Sized via bus capacitance:
+  $$R_{min} = \frac{V_{DD} - 0.4\text{V}}{3\text{mA}}, \quad R_{max} = \frac{t_r}{0.8473 \cdot C_{bus}}$$
+  For standard $400\text{ kHz}$ Fast-mode with $C_{bus} \approx 100\text{pF}$, standard pull-up is $2.2\text{k}\Omega - 4.7\text{k}\Omega$.
+
+---
+
+## 4. Power Distribution Tree & Subsystem Tracing
+
+Every schematic audit must construct a hierarchical Power Tree starting from the primary power inlet to every downstream load:
+
+```
+[USB-C VBUS (+5.0V / 3A)]
+   |
+   +---> [USBLC6-2SC6 TVS Diode] ---> GND
+   |
+   +---> [Reverse Polarity P-FET (AO3401A)]
+            |
+            +---> [Main DC Rail (+5V0)]
+                     |
+                     +---> [AP2112K-3.3 LDO (Cin=4.7uF)]
+                              |
+                              +---> [+3V3 Digital Rail] (Cout=4.7uF)
+                                       |
+                                       +---> RP2040 IOVDD (4x 100nF)
+                                       +---> Flash Memory SPI VDD (1x 100nF)
+                                       +---> Reset Generator Pullup (10k)
+```
+
+### Decoupling Rules of Engagement
+1. Every IC supply pin (`VDD`, `VCC`, `IOVDD`, `AVDD`) must have at least one dedicated low-ESR ceramic bypass capacitor (typically $100\text{nF}$, $0402$ or $0603$) placed within $1.5\text{mm}$ of the physical pin.
+2. Analog power pins (`AVDD`, `VREF`) must include high-frequency noise rejection (ferrite bead or series $10\Omega$ resistor forming an RC low-pass filter with $\ge 1\mu\text{F}$ capacitor).
+
+---
+
+## 5. Negative Evidence Analysis (The "What is NOT Connected" Rule)
+
+Traditional reviews only verify existing wires. The Reviewer agent must systematically audit **missing** connections:
+1. **Floating CMOS Inputs**:
+   - High-impedance CMOS inputs left floating drift to intermediate logic levels ($V_{DD}/2$), causing both P-FET and N-FET transistors to conduct simultaneously, resulting in excessive shoot-through current ($>10\text{mA}$ per pin) and thermal destruction.
+   - *Rule*: Every unused digital input must be tied to $V_{DD}$ or $GND$, or explicitly configured as an output with internal pull-down in firmware.
+2. **Unconnected Peripheral Pins**:
+   - Flag unconnected `BOOT`, `SWCLK`, `SWDIO`, or `TEST` pins.
+3. **Do-Not-Populate (DNP) Component Impact**:
+   - Audit DNP zero-ohm links to ensure critical signal paths are not permanently open-circuited.
+
+---
+
+## 6. Formal Audit Schema (`schematic_audit_report.json`)
+
+The output of this skill is a machine-readable audit report:
+
+```json
+{
+  "schema_version": "1.0.0",
+  "audit_timestamp": "2026-09-14T20:30:00Z",
+  "project_name": "iot-telemetry-node",
+  "total_components": 42,
+  "total_nets": 78,
+  "grounded_findings": [
+    {
+      "finding_id": "PWR-001",
+      "severity": "PASS",
+      "subsystem": "Power Distribution",
+      "component": "U1 (AP2112K-3.3)",
+      "assertion": "Input voltage is within operating range",
+      "evidence": {
+        "datasheet": "AP2112K_Rev5.pdf",
+        "page": 4,
+        "table": "Absolute Maximum Ratings",
+        "rated_max_v": 6.0,
+        "actual_v": 5.0,
+        "derating_margin_pct": 16.7
+      }
+    },
+    {
+      "finding_id": "PIN-002",
+      "severity": "FAIL",
+      "subsystem": "Microcontroller",
+      "component": "U2 (RP2040)",
+      "pin": "PIN 19 (RUN)",
+      "assertion": "Active-low reset line must have pull-up resistor",
+      "evidence": {
+        "datasheet": "rp2040_datasheet.pdf",
+        "page": 24,
+        "quote": "RUN is active-low. Driven low to reset. High-impedance with weak internal pull-up (~50k); external 10k recommended in noisy environments."
+      },
+      "remediation": "Add 10k pull-up resistor R5 between net ~{RESET} and +3V3."
+    }
+  ],
+  "negative_evidence_audit": {
+    "floating_inputs_detected": 0,
+    "unconnected_power_pins": 0,
+    "dnp_components_verified": 2
+  },
+  "overall_verdict": "FAIL"
+}
+```
+
+---
+
+## 7. Negative Constraints (Anti-Slop Directives)
+
+- **DO NOT** declare a pin connection valid without cross-referencing the official datasheet pin description table.
+- **DO NOT** approve an I2C bus lacking physical pull-up resistors on both `SDA` and `SCL`.
+- **DO NOT** permit linear regulators with an estimated junction temperature $T_J > 105^\circ\text{C}$.
+- **DO NOT** assume microcontrollers have internal pull-ups enabled during hardware reset; hardware reset pins must have external hardware pull-ups.
+- **DO NOT** mark an audit as `PASS` if any high-impedance CMOS inputs are left floating.