@aptre/v86 0.5.0

package/src/rust/js_api.rs

@@ -0,0 +1,6 @@
+use crate::cpu::cpu::translate_address_system_read;
+
+#[no_mangle]
+pub unsafe fn translate_address_system_read_js(addr: i32) -> u32 {
+    translate_address_system_read(addr).unwrap()
+}

package/src/rust/leb.rs

@@ -0,0 +1,46 @@
+pub fn write_leb_i32(buf: &mut Vec<u8>, v: i32) { write_leb_i64(buf, v as i64); }
+
+pub fn write_leb_i64(buf: &mut Vec<u8>, mut v: i64) {
+    // https://en.wikipedia.org/wiki/LEB128#Encode_signed_integer
+    loop {
+        let mut byte = v as u8 & 0b0111_1111;
+        v >>= 7;
+        let sign = byte & (1 << 6);
+        let done = v == 0 && sign == 0 || v == -1 && sign != 0;
+        if !done {
+            byte |= 0b1000_0000;
+        }
+        buf.push(byte);
+        if done {
+            break;
+        }
+    }
+}
+
+pub fn write_leb_u32(buf: &mut Vec<u8>, mut v: u32) {
+    loop {
+        let mut byte = v as u8 & 0b0111_1111;
+        v >>= 7;
+        if v != 0 {
+            byte |= 0b1000_0000;
+        }
+        buf.push(byte);
+        if v == 0 {
+            break;
+        }
+    }
+}
+
+pub fn write_fixed_leb16_at_idx(vec: &mut Vec<u8>, idx: usize, x: u16) {
+    dbg_assert!(x < (1 << 14)); // we have 14 bits of available space in 2 bytes for leb
+    vec[idx] = ((x & 0b1111111) | 0b10000000) as u8;
+    vec[idx + 1] = (x >> 7) as u8;
+}
+
+pub fn write_fixed_leb32_at_idx(vec: &mut Vec<u8>, idx: usize, x: u32) {
+    dbg_assert!(x < (1 << 28)); // we have 28 bits of available space in 4 bytes for leb
+    vec[idx] = (x & 0b1111111) as u8 | 0b10000000;
+    vec[idx + 1] = (x >> 7 & 0b1111111) as u8 | 0b10000000;
+    vec[idx + 2] = (x >> 14 & 0b1111111) as u8 | 0b10000000;
+    vec[idx + 3] = (x >> 21 & 0b1111111) as u8;
+}

package/src/rust/lib.rs

@@ -0,0 +1,29 @@
+#[macro_use]
+mod dbg;
+
+#[macro_use]
+mod paging;
+
+pub mod cpu;
+
+pub mod js_api;
+pub mod profiler;
+
+mod analysis;
+mod codegen;
+mod config;
+mod control_flow;
+mod cpu_context;
+mod gen;
+mod jit;
+mod jit_instructions;
+mod leb;
+mod modrm;
+mod opstats;
+mod page;
+mod prefix;
+mod regs;
+mod softfloat;
+mod state_flags;
+mod wasmgen;
+mod zstd;

package/src/rust/modrm.rs

@@ -0,0 +1,330 @@
+use crate::codegen;
+use crate::cpu::global_pointers;
+use crate::cpu_context::CpuContext;
+use crate::jit::JitContext;
+use crate::prefix::{PREFIX_MASK_SEGMENT, SEG_PREFIX_ZERO};
+use crate::profiler;
+use crate::regs::{BP, BX, DI, SI};
+use crate::regs::{CS, DS, ES, FS, GS, SS};
+use crate::regs::{EAX, EBP, EBX, ECX, EDI, EDX, ESI, ESP};
+
+pub struct ModrmByte {
+    segment: u32,
+    first_reg: Option<u32>,
+    second_reg: Option<u32>,
+    shift: u8,
+    immediate: i32,
+    is_16: bool,
+}
+impl ModrmByte {
+    pub fn is_nop(&self, reg: u32) -> bool {
+        self.first_reg == Some(reg)
+            && self.second_reg.is_none()
+            && self.shift == 0
+            && self.immediate == 0
+            && !self.is_16
+    }
+}
+
+pub fn decode(ctx: &mut CpuContext, modrm_byte: u8) -> ModrmByte {
+    if ctx.asize_32() {
+        decode32(ctx, modrm_byte)
+    }
+    else {
+        decode16(ctx, modrm_byte)
+    }
+}
+
+fn decode16(ctx: &mut CpuContext, modrm_byte: u8) -> ModrmByte {
+    fn mk16(
+        segment: u32,
+        first_reg: Option<u32>,
+        second_reg: Option<u32>,
+        immediate: i32,
+    ) -> ModrmByte {
+        ModrmByte {
+            segment,
+            first_reg,
+            second_reg,
+            shift: 0,
+            immediate,
+            is_16: true,
+        }
+    }
+
+    match modrm_byte & !0o070 {
+        0o000 => mk16(DS, Some(BX), Some(SI), 0),
+        0o001 => mk16(DS, Some(BX), Some(DI), 0),
+        0o002 => mk16(SS, Some(BP), Some(SI), 0),
+        0o003 => mk16(SS, Some(BP), Some(DI), 0),
+        0o004 => mk16(DS, Some(SI), None, 0),
+        0o005 => mk16(DS, Some(DI), None, 0),
+        0o006 => mk16(DS, None, None, ctx.read_imm16() as i32),
+        0o007 => mk16(DS, Some(BX), None, 0),
+
+        0o100 => mk16(DS, Some(BX), Some(SI), ctx.read_imm8s() as i32),
+        0o101 => mk16(DS, Some(BX), Some(DI), ctx.read_imm8s() as i32),
+        0o102 => mk16(SS, Some(BP), Some(SI), ctx.read_imm8s() as i32),
+        0o103 => mk16(SS, Some(BP), Some(DI), ctx.read_imm8s() as i32),
+        0o104 => mk16(DS, Some(SI), None, ctx.read_imm8s() as i32),
+        0o105 => mk16(DS, Some(DI), None, ctx.read_imm8s() as i32),
+        0o106 => mk16(SS, Some(BP), None, ctx.read_imm8s() as i32),
+        0o107 => mk16(DS, Some(BX), None, ctx.read_imm8s() as i32),
+
+        0o200 => mk16(DS, Some(BX), Some(SI), ctx.read_imm16() as i32),
+        0o201 => mk16(DS, Some(BX), Some(DI), ctx.read_imm16() as i32),
+        0o202 => mk16(SS, Some(BP), Some(SI), ctx.read_imm16() as i32),
+        0o203 => mk16(SS, Some(BP), Some(DI), ctx.read_imm16() as i32),
+        0o204 => mk16(DS, Some(SI), None, ctx.read_imm16() as i32),
+        0o205 => mk16(DS, Some(DI), None, ctx.read_imm16() as i32),
+        0o206 => mk16(SS, Some(BP), None, ctx.read_imm16() as i32),
+        0o207 => mk16(DS, Some(BX), None, ctx.read_imm16() as i32),
+
+        _ => panic!("modrm byte >= 0xC0"),
+    }
+}
+
+fn decode32(ctx: &mut CpuContext, modrm_byte: u8) -> ModrmByte {
+    fn mk32(segment: u32, first_reg: Option<u32>, immediate: i32) -> ModrmByte {
+        ModrmByte {
+            segment,
+            first_reg,
+            second_reg: None,
+            shift: 0,
+            immediate,
+            is_16: false,
+        }
+    }
+
+    match modrm_byte & !0o070 {
+        0o000 => mk32(DS, Some(EAX), 0),
+        0o001 => mk32(DS, Some(ECX), 0),
+        0o002 => mk32(DS, Some(EDX), 0),
+        0o003 => mk32(DS, Some(EBX), 0),
+        0o004 => decode_sib(ctx, Imm32::None),
+        0o005 => mk32(DS, None, ctx.read_imm32() as i32),
+        0o006 => mk32(DS, Some(ESI), 0),
+        0o007 => mk32(DS, Some(EDI), 0),
+
+        0o100 => mk32(DS, Some(EAX), ctx.read_imm8s() as i32),
+        0o101 => mk32(DS, Some(ECX), ctx.read_imm8s() as i32),
+        0o102 => mk32(DS, Some(EDX), ctx.read_imm8s() as i32),
+        0o103 => mk32(DS, Some(EBX), ctx.read_imm8s() as i32),
+        0o104 => decode_sib(ctx, Imm32::Imm8),
+        0o105 => mk32(SS, Some(EBP), ctx.read_imm8s() as i32),
+        0o106 => mk32(DS, Some(ESI), ctx.read_imm8s() as i32),
+        0o107 => mk32(DS, Some(EDI), ctx.read_imm8s() as i32),
+
+        0o200 => mk32(DS, Some(EAX), ctx.read_imm32() as i32),
+        0o201 => mk32(DS, Some(ECX), ctx.read_imm32() as i32),
+        0o202 => mk32(DS, Some(EDX), ctx.read_imm32() as i32),
+        0o203 => mk32(DS, Some(EBX), ctx.read_imm32() as i32),
+        0o204 => decode_sib(ctx, Imm32::Imm32),
+        0o205 => mk32(SS, Some(EBP), ctx.read_imm32() as i32),
+        0o206 => mk32(DS, Some(ESI), ctx.read_imm32() as i32),
+        0o207 => mk32(DS, Some(EDI), ctx.read_imm32() as i32),
+
+        _ => panic!("modrm byte >= 0xC0"),
+    }
+}
+
+fn decode_sib(ctx: &mut CpuContext, immediate: Imm32) -> ModrmByte {
+    let sib_byte = ctx.read_imm8();
+    let r = sib_byte & 7;
+    let m = sib_byte >> 3 & 7;
+    let shift = sib_byte >> 6 & 3;
+
+    let second_reg = if m == 4 { None } else { Some(m as u32) };
+
+    let segment;
+    let reg;
+
+    if r == 4 {
+        segment = SS;
+        reg = ESP;
+    }
+    else if r == 5 {
+        if immediate == Imm32::None {
+            return ModrmByte {
+                segment: DS,
+                first_reg: None,
+                second_reg,
+                shift,
+                immediate: ctx.read_imm32() as i32,
+                is_16: false,
+            };
+        }
+        else {
+            segment = SS;
+            reg = EBP;
+        }
+    }
+    else {
+        segment = DS;
+        reg = r as u32;
+    }
+
+    let immediate = match immediate {
+        Imm32::None => 0,
+        Imm32::Imm8 => ctx.read_imm8s() as i32,
+        Imm32::Imm32 => ctx.read_imm32() as i32,
+    };
+
+    ModrmByte {
+        segment,
+        first_reg: Some(reg),
+        second_reg,
+        shift,
+        immediate,
+        is_16: false,
+    }
+}
+
+pub fn gen(ctx: &mut JitContext, modrm_byte: ModrmByte, esp_offset: i32) {
+    codegen::gen_profiler_stat_increment(
+        ctx.builder,
+        match modrm_byte {
+            ModrmByte {
+                first_reg: None,
+                second_reg: None,
+                ..
+            } => profiler::stat::MODRM_SIMPLE_CONST_OFFSET,
+            ModrmByte {
+                first_reg: Some(_),
+                second_reg: None,
+                ..
+            }
+            | ModrmByte {
+                first_reg: None,
+                second_reg: Some(_),
+                shift: 0,
+                ..
+            } => {
+                if modrm_byte.immediate == 0 {
+                    profiler::stat::MODRM_SIMPLE_REG
+                }
+                else {
+                    profiler::stat::MODRM_SIMPLE_REG_WITH_OFFSET
+                }
+            },
+            _ => profiler::stat::MODRM_COMPLEX,
+        },
+    );
+
+    let mut have_something_on_stack = false;
+
+    if let Some(reg) = modrm_byte.first_reg {
+        codegen::gen_get_reg32(ctx, reg);
+        if reg == ESP && esp_offset != 0 {
+            ctx.builder.const_i32(esp_offset);
+            ctx.builder.add_i32();
+        }
+        have_something_on_stack = true;
+    }
+
+    if let Some(reg) = modrm_byte.second_reg {
+        codegen::gen_get_reg32(ctx, reg);
+        dbg_assert!(reg != ESP); // second reg cannot be esp, no need to handle esp_offset
+        if modrm_byte.shift != 0 {
+            ctx.builder.const_i32(modrm_byte.shift.into());
+            ctx.builder.shl_i32();
+        }
+        if have_something_on_stack {
+            ctx.builder.add_i32();
+        }
+        have_something_on_stack = true;
+    }
+
+    if modrm_byte.immediate != 0 || !have_something_on_stack {
+        ctx.builder.const_i32(modrm_byte.immediate);
+        if have_something_on_stack {
+            ctx.builder.add_i32();
+        }
+    }
+
+    if modrm_byte.is_16 {
+        ctx.builder.const_i32(0xFFFF);
+        ctx.builder.and_i32();
+    }
+    jit_add_seg_offset(ctx, modrm_byte.segment);
+}
+
+pub fn get_as_reg_index_if_possible(ctx: &mut JitContext, modrm_byte: &ModrmByte) -> Option<u32> {
+    let prefix = ctx.cpu.prefixes & PREFIX_MASK_SEGMENT;
+    let seg = if prefix != 0 { (prefix - 1) as u32 } else { modrm_byte.segment };
+    if can_optimize_get_seg(ctx, seg)
+        && modrm_byte.second_reg.is_none()
+        && modrm_byte.immediate == 0
+        && !modrm_byte.is_16
+        && modrm_byte.shift == 0
+    {
+        modrm_byte.first_reg
+    }
+    else {
+        None
+    }
+}
+
+pub fn skip(ctx: &mut CpuContext, modrm_byte: u8) { let _ = decode(ctx, modrm_byte); }
+
+#[derive(PartialEq)]
+enum Imm32 {
+    None,
+    Imm8,
+    Imm32,
+}
+
+fn can_optimize_get_seg(ctx: &mut JitContext, segment: u32) -> bool {
+    (segment == DS || segment == SS || segment == CS) && ctx.cpu.has_flat_segmentation()
+}
+
+pub fn jit_add_seg_offset(ctx: &mut JitContext, default_segment: u32) {
+    let prefix = ctx.cpu.prefixes & PREFIX_MASK_SEGMENT;
+
+    if prefix == SEG_PREFIX_ZERO {
+        return;
+    }
+
+    let seg = if prefix != 0 { (prefix - 1) as u32 } else { default_segment };
+    jit_add_seg_offset_no_override(ctx, seg);
+}
+
+pub fn jit_add_seg_offset_no_override(ctx: &mut JitContext, seg: u32) {
+    if can_optimize_get_seg(ctx, seg) {
+        codegen::gen_profiler_stat_increment(ctx.builder, profiler::stat::SEG_OFFSET_OPTIMISED);
+        return;
+    }
+    codegen::gen_profiler_stat_increment(ctx.builder, profiler::stat::SEG_OFFSET_NOT_OPTIMISED);
+    codegen::gen_profiler_stat_increment(
+        ctx.builder,
+        if seg == ES {
+            profiler::stat::SEG_OFFSET_NOT_OPTIMISED_ES
+        }
+        else if seg == FS {
+            profiler::stat::SEG_OFFSET_NOT_OPTIMISED_FS
+        }
+        else if seg == GS {
+            profiler::stat::SEG_OFFSET_NOT_OPTIMISED_GS
+        }
+        else {
+            profiler::stat::SEG_OFFSET_NOT_OPTIMISED_NOT_FLAT
+        },
+    );
+
+    if seg != CS && seg != SS {
+        if cfg!(feature = "profiler") {
+            ctx.builder.const_i32(seg as i32);
+            ctx.builder.call_fn1("log_segment_null");
+        }
+
+        ctx.builder
+            .load_fixed_u8(global_pointers::get_segment_is_null_offset(seg));
+        ctx.builder.if_void();
+        codegen::gen_trigger_gp(ctx, 0);
+        ctx.builder.block_end();
+    }
+
+    ctx.builder
+        .load_fixed_i32(global_pointers::get_seg_offset(seg));
+    ctx.builder.add_i32();
+}

package/src/rust/opstats.rs

@@ -0,0 +1,249 @@
+use crate::wasmgen::wasm_builder::WasmBuilder;
+
+const SIZE: usize = if cfg!(feature = "profiler") { 8192 } else { 0 };
+
+#[allow(non_upper_case_globals)]
+pub static mut opstats_buffer: [u64; SIZE] = [0; SIZE];
+#[allow(non_upper_case_globals)]
+pub static mut opstats_compiled_buffer: [u64; SIZE] = [0; SIZE];
+#[allow(non_upper_case_globals)]
+pub static mut opstats_jit_exit_buffer: [u64; SIZE] = [0; SIZE];
+#[allow(non_upper_case_globals)]
+pub static mut opstats_unguarded_register_buffer: [u64; SIZE] = [0; SIZE];
+#[allow(non_upper_case_globals)]
+pub static mut opstats_wasm_size: [u64; SIZE] = [0; SIZE];
+
+pub struct Instruction {
+    pub prefixes: Vec<u8>,
+    pub opcode: u8,
+    pub fixed_g: u8,
+    pub is_mem: bool,
+    pub is_0f: bool,
+}
+
+pub fn decode(mut instruction: u32) -> Instruction {
+    let mut is_0f = false;
+    let mut prefixes = vec![];
+    let mut final_opcode = 0;
+
+    for _ in 0..4 {
+        let opcode = (instruction & 0xFF) as u8;
+        instruction >>= 8;
+
+        // TODO:
+        // - If the instruction uses 4 or more prefixes, only the prefixes will be counted
+
+        if is_0f {
+            final_opcode = opcode;
+            break;
+        }
+        else {
+            if opcode == 0x0F {
+                is_0f = true;
+            }
+            else if opcode == 0x26
+                || opcode == 0x2E
+                || opcode == 0x36
+                || opcode == 0x3E
+                || opcode == 0x64
+                || opcode == 0x65
+                || opcode == 0x66
+                || opcode == 0x67
+                || opcode == 0xF0
+                || opcode == 0xF2
+                || opcode == 0xF3
+            {
+                prefixes.push(opcode);
+            }
+            else {
+                final_opcode = opcode;
+                break;
+            }
+        }
+    }
+
+    let has_modrm_byte = if is_0f {
+        match final_opcode {
+            0x0 | 0x1 | 0x2 | 0x3 | 0x10 | 0x11 | 0x12 | 0x13 | 0x14 | 0x15 | 0x16 | 0x17
+            | 0x18 | 0x19 | 0x20 | 0x21 | 0x22 | 0x23 | 0x28 | 0x29 | 0x40 | 0x41 | 0x42 | 0x43
+            | 0x44 | 0x45 | 0x46 | 0x47 | 0x48 | 0x49 | 0x50 | 0x51 | 0x52 | 0x53 | 0x54 | 0x55
+            | 0x56 | 0x57 | 0x58 | 0x59 | 0x60 | 0x61 | 0x62 | 0x63 | 0x64 | 0x65 | 0x66 | 0x67
+            | 0x68 | 0x69 | 0x70 | 0x71 | 0x72 | 0x73 | 0x74 | 0x75 | 0x76 | 0x90 | 0x91 | 0x92
+            | 0x93 | 0x94 | 0x95 | 0x96 | 0x97 | 0x98 | 0x99 | 0x1c | 0x1d | 0x1e | 0x1f | 0x2a
+            | 0x2b | 0x2c | 0x2d | 0x2e | 0x2f | 0x4a | 0x4b | 0x4c | 0x4d | 0x4e | 0x4f | 0x5a
+            | 0x5b | 0x5c | 0x5d | 0x5e | 0x5f | 0x6a | 0x6b | 0x6c | 0x6d | 0x6e | 0x6f | 0x7e
+            | 0x7f | 0x9a | 0x9b | 0x9c | 0x9d | 0x9e | 0x9f | 0xa3 | 0xa4 | 0xa5 | 0xab | 0xac
+            | 0xad | 0xae | 0xaf | 0xb0 | 0xb1 | 0xb2 | 0xb3 | 0xb4 | 0xb5 | 0xb6 | 0xb7 | 0xb8
+            | 0xba | 0xbb | 0xbc | 0xbd | 0xbe | 0xbf | 0xc0 | 0xc1 | 0xc2 | 0xc3 | 0xc4 | 0xc5
+            | 0xc6 | 0xc7 | 0xd1 | 0xd2 | 0xd3 | 0xd4 | 0xd5 | 0xd6 | 0xd7 | 0xd8 | 0xd9 | 0xda
+            | 0xdb | 0xdc | 0xdd | 0xde | 0xdf | 0xe0 | 0xe1 | 0xe2 | 0xe3 | 0xe4 | 0xe5 | 0xe6
+            | 0xe7 | 0xe8 | 0xe9 | 0xea | 0xeb | 0xec | 0xed | 0xee | 0xef | 0xf1 | 0xf2 | 0xf3
+            | 0xf4 | 0xf5 | 0xf6 | 0xf7 | 0xf8 | 0xf9 | 0xfa | 0xfb | 0xfc | 0xfd | 0xfe => true,
+            _ => false,
+        }
+    }
+    else {
+        match final_opcode {
+            0x0 | 0x1 | 0x2 | 0x3 | 0x8 | 0x9 | 0x10 | 0x11 | 0x12 | 0x13 | 0x18 | 0x19 | 0x20
+            | 0x21 | 0x22 | 0x23 | 0x28 | 0x29 | 0x30 | 0x31 | 0x32 | 0x33 | 0x38 | 0x39 | 0x62
+            | 0x63 | 0x69 | 0x80 | 0x81 | 0x82 | 0x83 | 0x84 | 0x85 | 0x86 | 0x87 | 0x88 | 0x89
+            | 0xa | 0xb | 0x1a | 0x1b | 0x2a | 0x2b | 0x3a | 0x3b | 0x6b | 0x8a | 0x8b | 0x8c
+            | 0x8d | 0x8e | 0x8f | 0xc0 | 0xc1 | 0xc4 | 0xc5 | 0xc6 | 0xc7 | 0xd0 | 0xd1 | 0xd2
+            | 0xd3 | 0xd8 | 0xd9 | 0xda | 0xdb | 0xdc | 0xdd | 0xde | 0xdf | 0xf6 | 0xf7 | 0xfe
+            | 0xff => true,
+            _ => false,
+        }
+    };
+
+    let has_fixed_g = if is_0f {
+        final_opcode == 0x71
+            || final_opcode == 0x72
+            || final_opcode == 0x73
+            || final_opcode == 0xAE
+            || final_opcode == 0xBA
+            || final_opcode == 0xC7
+    }
+    else {
+        final_opcode >= 0x80 && final_opcode < 0x84
+            || final_opcode >= 0xC0 && final_opcode < 0xC2
+            || final_opcode >= 0xD0 && final_opcode < 0xD4
+            || final_opcode >= 0xD8 && final_opcode < 0xE0
+            || final_opcode >= 0xF6 && final_opcode < 0xF8
+            || final_opcode == 0xFE
+            || final_opcode == 0xFF
+    };
+
+    let mut is_mem = false;
+    let mut fixed_g = 0;
+
+    if has_fixed_g {
+        dbg_assert!(has_modrm_byte);
+        let modrm_byte = (instruction & 0xFF) as u8;
+        fixed_g = modrm_byte >> 3 & 7;
+        is_mem = modrm_byte < 0xC0
+    }
+    if has_modrm_byte {
+        let modrm_byte = (instruction & 0xFF) as u8;
+        is_mem = modrm_byte < 0xC0
+    }
+
+    Instruction {
+        prefixes,
+        opcode: final_opcode,
+        is_mem,
+        fixed_g,
+        is_0f,
+    }
+}
+
+pub fn gen_opstats(builder: &mut WasmBuilder, opcode: u32) {
+    if !cfg!(feature = "profiler") {
+        return;
+    }
+
+    let instruction = decode(opcode);
+
+    for prefix in instruction.prefixes {
+        let index = (prefix as u32) << 4;
+        builder.increment_fixed_i64(
+            unsafe { &mut opstats_buffer[index as usize] as *mut _ } as u32,
+            1,
+        );
+    }
+
+    let index = (instruction.is_0f as u32) << 12
+        | (instruction.opcode as u32) << 4
+        | (instruction.is_mem as u32) << 3
+        | instruction.fixed_g as u32;
+
+    builder.increment_fixed_i64(
+        unsafe { &mut opstats_buffer[index as usize] as *mut _ } as u32,
+        1,
+    );
+}
+
+pub fn record_opstat_compiled(opcode: u32) {
+    if !cfg!(feature = "profiler") {
+        return;
+    }
+
+    let instruction = decode(opcode);
+
+    for prefix in instruction.prefixes {
+        let index = (prefix as u32) << 4;
+        unsafe { opstats_compiled_buffer[index as usize] += 1 }
+    }
+
+    let index = (instruction.is_0f as u32) << 12
+        | (instruction.opcode as u32) << 4
+        | (instruction.is_mem as u32) << 3
+        | instruction.fixed_g as u32;
+
+    unsafe { opstats_compiled_buffer[index as usize] += 1 }
+}
+
+pub fn record_opstat_jit_exit(opcode: u32) {
+    if !cfg!(feature = "profiler") {
+        return;
+    }
+
+    let instruction = decode(opcode);
+
+    for prefix in instruction.prefixes {
+        let index = (prefix as u32) << 4;
+        unsafe { opstats_jit_exit_buffer[index as usize] += 1 }
+    }
+
+    let index = (instruction.is_0f as u32) << 12
+        | (instruction.opcode as u32) << 4
+        | (instruction.is_mem as u32) << 3
+        | instruction.fixed_g as u32;
+
+    unsafe { opstats_jit_exit_buffer[index as usize] += 1 }
+}
+
+pub fn gen_opstat_unguarded_register(builder: &mut WasmBuilder, opcode: u32) {
+    if !cfg!(feature = "profiler") {
+        return;
+    }
+
+    let instruction = decode(opcode);
+
+    for prefix in instruction.prefixes {
+        let index = (prefix as u32) << 4;
+        builder.increment_fixed_i64(
+            unsafe { &mut opstats_unguarded_register_buffer[index as usize] as *mut _ } as u32,
+            1,
+        );
+    }
+
+    let index = (instruction.is_0f as u32) << 12
+        | (instruction.opcode as u32) << 4
+        | (instruction.is_mem as u32) << 3
+        | instruction.fixed_g as u32;
+
+    builder.increment_fixed_i64(
+        unsafe { &mut opstats_unguarded_register_buffer[index as usize] as *mut _ } as u32,
+        1,
+    );
+}
+
+pub fn record_opstat_size_wasm(opcode: u32, size: u64) {
+    if !cfg!(feature = "profiler") {
+        return;
+    }
+
+    let instruction = decode(opcode);
+
+    for prefix in instruction.prefixes {
+        let index = (prefix as u32) << 4;
+        unsafe { opstats_wasm_size[index as usize] += size }
+    }
+
+    let index = (instruction.is_0f as u32) << 12
+        | (instruction.opcode as u32) << 4
+        | (instruction.is_mem as u32) << 3
+        | instruction.fixed_g as u32;
+
+    unsafe { opstats_wasm_size[index as usize] += size }
+}

package/src/rust/page.rs

@@ -0,0 +1,15 @@
+use std::ops::RangeInclusive;
+
+#[derive(Copy, Clone, Eq, Hash, PartialEq)]
+pub struct Page(u32);
+impl Page {
+    pub fn page_of(address: u32) -> Page { Page(address >> 12) }
+    pub fn to_address(self) -> u32 { self.0 << 12 }
+
+    pub fn to_u32(self) -> u32 { self.0 }
+    pub fn of_u32(page: u32) -> Page { Page(page) }
+
+    pub fn address_range(self) -> RangeInclusive<u32> {
+        self.to_address()..=self.to_address() + 4095
+    }
+}

package/src/rust/paging.rs

@@ -0,0 +1,25 @@
+pub type OrPageFault<T> = Result<T, ()>;
+
+macro_rules! return_on_pagefault {
+    ($expr:expr) => {
+        match $expr {
+            Ok(v) => v,
+            Err(()) => return,
+        }
+    };
+    ($expr:expr, $ret:expr) => {
+        match $expr {
+            Ok(v) => v,
+            Err(()) => return $ret,
+        }
+    };
+}
+
+macro_rules! break_on_pagefault {
+    ($expr:expr) => {
+        match $expr {
+            Ok(v) => v,
+            Err(()) => break,
+        }
+    };
+}