@aptre/v86 0.5.0

package/src/rust/cpu/ioapic.rs

@@ -0,0 +1,316 @@
+// http://download.intel.com/design/chipsets/datashts/29056601.pdf
+
+use crate::cpu::{apic, global_pointers::acpi_enabled};
+use std::sync::{Mutex, MutexGuard};
+
+const IOAPIC_LOG_VERBOSE: bool = false;
+
+const IOREGSEL: u32 = 0;
+const IOWIN: u32 = 0x10;
+
+const IOAPIC_IRQ_COUNT: usize = 24;
+
+const IOAPIC_FIRST_IRQ_REG: u32 = 0x10;
+const IOAPIC_LAST_IRQ_REG: u32 = 0x10 + 2 * IOAPIC_IRQ_COUNT as u32;
+
+const IOAPIC_ID: u32 = 0; // must match value in seabios
+
+pub const IOAPIC_CONFIG_TRIGGER_MODE_LEVEL: u32 = 1 << 15;
+
+const IOAPIC_CONFIG_MASKED: u32 = 1 << 16;
+const IOAPIC_CONFIG_DELIVS: u32 = 1 << 12;
+const IOAPIC_CONFIG_REMOTE_IRR: u32 = 1 << 14;
+const IOAPIC_CONFIG_READONLY_MASK: u32 =
+    IOAPIC_CONFIG_REMOTE_IRR | IOAPIC_CONFIG_DELIVS | 0xFFFE0000;
+
+const IOAPIC_DELIVERY_FIXED: u8 = 0;
+const IOAPIC_DELIVERY_LOWEST_PRIORITY: u8 = 1;
+const _IOAPIC_DELIVERY_NMI: u8 = 4;
+const _IOAPIC_DELIVERY_INIT: u8 = 5;
+
+const DELIVERY_MODES: [&str; 8] = [
+    "Fixed (0)",
+    "Lowest Prio (1)",
+    "SMI (2)",
+    "Reserved (3)",
+    "NMI (4)",
+    "INIT (5)",
+    "Reserved (6)",
+    "ExtINT (7)",
+];
+
+const DESTINATION_MODES: [&str; 2] = ["physical", "logical"];
+
+// keep in sync with cpu.js
+#[allow(dead_code)]
+const IOAPIC_STRUCT_SIZE: usize = 4 * 52;
+
+// Note: JavaScript (cpu.get_state_apic) depens on this layout
+const _: () = assert!(std::mem::offset_of!(Ioapic, ioredtbl_destination) == 24 * 4);
+const _: () = assert!(std::mem::offset_of!(Ioapic, ioregsel) == 48 * 4);
+const _: () = assert!(std::mem::offset_of!(Ioapic, irq_value) == 51 * 4);
+const _: () = assert!(std::mem::size_of::<Ioapic>() == IOAPIC_STRUCT_SIZE);
+#[repr(C)]
+struct Ioapic {
+    ioredtbl_config: [u32; IOAPIC_IRQ_COUNT],
+    ioredtbl_destination: [u32; IOAPIC_IRQ_COUNT],
+    ioregsel: u32,
+    ioapic_id: u32,
+    irr: u32,
+    irq_value: u32,
+}
+
+static IOAPIC: Mutex<Ioapic> = Mutex::new(Ioapic {
+    ioredtbl_config: [IOAPIC_CONFIG_MASKED; IOAPIC_IRQ_COUNT],
+    ioredtbl_destination: [0; IOAPIC_IRQ_COUNT],
+    ioregsel: 0,
+    ioapic_id: IOAPIC_ID,
+    irr: 0,
+    irq_value: 0,
+});
+
+fn get_ioapic() -> MutexGuard<'static, Ioapic> { IOAPIC.try_lock().unwrap() }
+
+#[no_mangle]
+pub fn get_ioapic_addr() -> u32 { &raw mut *get_ioapic() as u32 }
+
+pub fn remote_eoi(apic: &mut apic::Apic, vector: u8) {
+    remote_eoi_internal(&mut get_ioapic(), apic, vector);
+}
+
+fn remote_eoi_internal(ioapic: &mut Ioapic, apic: &mut apic::Apic, vector: u8) {
+    for i in 0..IOAPIC_IRQ_COUNT as u8 {
+        let config = ioapic.ioredtbl_config[i as usize];
+
+        if (config & 0xFF) as u8 == vector && config & IOAPIC_CONFIG_REMOTE_IRR != 0 {
+            dbg_log!("Clear remote IRR for irq={:x}", i);
+            ioapic.ioredtbl_config[i as usize] &= !IOAPIC_CONFIG_REMOTE_IRR;
+            check_irq(ioapic, apic, i);
+        }
+    }
+}
+
+fn check_irq(ioapic: &mut Ioapic, apic: &mut apic::Apic, irq: u8) {
+    let mask = 1 << irq;
+
+    if ioapic.irr & mask == 0 {
+        return;
+    }
+
+    let config = ioapic.ioredtbl_config[irq as usize];
+
+    if config & IOAPIC_CONFIG_MASKED == 0 {
+        let delivery_mode = ((config >> 8) & 7) as u8;
+        let destination_mode = ((config >> 11) & 1) as u8;
+        let vector = (config & 0xFF) as u8;
+        let destination = (ioapic.ioredtbl_destination[irq as usize] >> 24) as u8;
+        let is_level =
+            config & IOAPIC_CONFIG_TRIGGER_MODE_LEVEL == IOAPIC_CONFIG_TRIGGER_MODE_LEVEL;
+
+        if config & IOAPIC_CONFIG_TRIGGER_MODE_LEVEL == 0 {
+            ioapic.irr &= !mask;
+        }
+        else {
+            ioapic.ioredtbl_config[irq as usize] |= IOAPIC_CONFIG_REMOTE_IRR;
+
+            if config & IOAPIC_CONFIG_REMOTE_IRR != 0 {
+                dbg_log!("No route: level interrupt and remote IRR still set");
+                return;
+            }
+        }
+
+        if delivery_mode == IOAPIC_DELIVERY_FIXED
+            || delivery_mode == IOAPIC_DELIVERY_LOWEST_PRIORITY
+        {
+            apic::route(
+                apic,
+                vector,
+                delivery_mode,
+                is_level,
+                destination,
+                destination_mode,
+            );
+        }
+        else {
+            dbg_assert!(false, "TODO");
+        }
+
+        ioapic.ioredtbl_config[irq as usize] &= !IOAPIC_CONFIG_DELIVS;
+    }
+}
+
+pub fn set_irq(i: u8) { set_irq_internal(&mut get_ioapic(), &mut apic::get_apic(), i) }
+
+fn set_irq_internal(ioapic: &mut Ioapic, apic: &mut apic::Apic, i: u8) {
+    if i as usize >= IOAPIC_IRQ_COUNT {
+        dbg_assert!(false, "Bad irq: {}", i);
+        return;
+    }
+
+    let mask = 1 << i;
+
+    if ioapic.irq_value & mask == 0 {
+        if IOAPIC_LOG_VERBOSE {
+            dbg_log!("apic set irq {}", i);
+        }
+
+        ioapic.irq_value |= mask;
+
+        let config = ioapic.ioredtbl_config[i as usize];
+        if config & (IOAPIC_CONFIG_TRIGGER_MODE_LEVEL | IOAPIC_CONFIG_MASKED)
+            == IOAPIC_CONFIG_MASKED
+        {
+            // edge triggered and masked
+            return;
+        }
+
+        ioapic.irr |= mask;
+
+        check_irq(ioapic, apic, i);
+    }
+}
+
+pub fn clear_irq(i: u8) { clear_irq_internal(&mut get_ioapic(), i) }
+
+fn clear_irq_internal(ioapic: &mut Ioapic, i: u8) {
+    if i as usize >= IOAPIC_IRQ_COUNT {
+        dbg_assert!(false, "Bad irq: {}", i);
+        return;
+    }
+
+    let mask = 1 << i;
+
+    if ioapic.irq_value & mask == mask {
+        ioapic.irq_value &= !mask;
+
+        let config = ioapic.ioredtbl_config[i as usize];
+        if config & IOAPIC_CONFIG_TRIGGER_MODE_LEVEL != 0 {
+            ioapic.irr &= !mask;
+        }
+    }
+}
+
+pub fn read32(addr: u32) -> u32 {
+    if unsafe { !*acpi_enabled } {
+        return 0;
+    }
+    read32_internal(&mut get_ioapic(), addr)
+}
+
+fn read32_internal(ioapic: &mut Ioapic, addr: u32) -> u32 {
+    match addr {
+        IOREGSEL => ioapic.ioregsel,
+        IOWIN => match ioapic.ioregsel {
+            0 => {
+                dbg_log!("IOAPIC Read id");
+                ioapic.ioapic_id << 24
+            },
+            1 => {
+                dbg_log!("IOAPIC Read version");
+                0x11 | (IOAPIC_IRQ_COUNT as u32 - 1) << 16
+            },
+            2 => {
+                dbg_log!("IOAPIC Read arbitration id");
+                ioapic.ioapic_id << 24
+            },
+            IOAPIC_FIRST_IRQ_REG..IOAPIC_LAST_IRQ_REG => {
+                let irq = ((ioapic.ioregsel - IOAPIC_FIRST_IRQ_REG) >> 1) as u8;
+                let index = ioapic.ioregsel & 1;
+
+                if index != 0 {
+                    let value = ioapic.ioredtbl_destination[irq as usize];
+                    dbg_log!("IOAPIC Read destination irq={:x} -> {:08x}", irq, value);
+                    value
+                }
+                else {
+                    let value = ioapic.ioredtbl_config[irq as usize];
+                    dbg_log!("IOAPIC Read config irq={:x} -> {:08x}", irq, value);
+                    value
+                }
+            },
+            reg => {
+                dbg_assert!(false, "IOAPIC register read outside of range {:x}", reg);
+                0
+            },
+        },
+        _ => {
+            dbg_assert!(false, "Unaligned or oob IOAPIC memory read: {:x}", addr);
+            0
+        },
+    }
+}
+
+pub fn write32(addr: u32, value: u32) {
+    if unsafe { !*acpi_enabled } {
+        return;
+    }
+    write32_internal(&mut get_ioapic(), &mut apic::get_apic(), addr, value)
+}
+
+fn write32_internal(ioapic: &mut Ioapic, apic: &mut apic::Apic, addr: u32, value: u32) {
+    //dbg_log!("IOAPIC write {:x} <- {:08x}", reg, value);
+
+    match addr {
+        IOREGSEL => ioapic.ioregsel = value,
+        IOWIN => match ioapic.ioregsel {
+            0 => ioapic.ioapic_id = (value >> 24) & 0x0F,
+            1 | 2 => {
+                dbg_log!("IOAPIC Invalid write: {}", ioapic.ioregsel);
+            },
+            IOAPIC_FIRST_IRQ_REG..IOAPIC_LAST_IRQ_REG => {
+                let irq = ((ioapic.ioregsel - IOAPIC_FIRST_IRQ_REG) >> 1) as u8;
+                let index = ioapic.ioregsel & 1;
+
+                if index != 0 {
+                    dbg_log!(
+                        "Write destination {:08x} irq={:x} dest={:02x}",
+                        value,
+                        irq,
+                        value >> 24
+                    );
+                    ioapic.ioredtbl_destination[irq as usize] = value & 0xFF000000;
+                }
+                else {
+                    let old_value = ioapic.ioredtbl_config[irq as usize] as u32;
+                    ioapic.ioredtbl_config[irq as usize] = (value & !IOAPIC_CONFIG_READONLY_MASK)
+                        | (old_value & IOAPIC_CONFIG_READONLY_MASK);
+
+                    let vector = value & 0xFF;
+                    let delivery_mode = (value >> 8) & 7;
+                    let destination_mode = (value >> 11) & 1;
+                    let is_level = (value >> 15) & 1;
+                    let disabled = (value >> 16) & 1;
+
+                    dbg_log!(
+                            "Write config {:08x} irq={:x} vector={:02x} deliverymode={} destmode={} is_level={} disabled={}",
+                            value,
+                            irq,
+                            vector,
+                            DELIVERY_MODES[delivery_mode as usize],
+                            DESTINATION_MODES[destination_mode as usize],
+                            is_level,
+                            disabled
+                        );
+
+                    check_irq(ioapic, apic, irq);
+                }
+            },
+            reg => {
+                dbg_assert!(
+                    false,
+                    "IOAPIC register write outside of range {:x} <- {:x}",
+                    reg,
+                    value
+                )
+            },
+        },
+        _ => {
+            dbg_assert!(
+                false,
+                "Unaligned or oob IOAPIC memory write: {:x} <- {:x}",
+                addr,
+                value
+            )
+        },
+    }
+}

package/src/rust/cpu/memory.rs

@@ -0,0 +1,351 @@
+mod ext {
+    extern "C" {
+        pub fn mmap_read8(addr: u32) -> i32;
+        pub fn mmap_read32(addr: u32) -> i32;
+
+        pub fn mmap_write8(addr: u32, value: i32);
+        pub fn mmap_write16(addr: u32, value: i32);
+        pub fn mmap_write32(addr: u32, value: i32);
+        pub fn mmap_write64(addr: u32, v0: i32, v1: i32);
+        pub fn mmap_write128(addr: u32, v0: i32, v1: i32, v2: i32, v3: i32);
+    }
+}
+
+use crate::cpu::apic;
+use crate::cpu::cpu::{
+    handle_irqs, reg128, APIC_MEM_ADDRESS, APIC_MEM_SIZE, IOAPIC_MEM_ADDRESS, IOAPIC_MEM_SIZE,
+};
+use crate::cpu::global_pointers::memory_size;
+use crate::cpu::ioapic;
+use crate::cpu::vga;
+use crate::jit;
+use crate::page::Page;
+
+use std::alloc;
+use std::ptr;
+
+#[allow(non_upper_case_globals)]
+pub static mut mem8: *mut u8 = ptr::null_mut();
+
+#[no_mangle]
+pub fn allocate_memory(size: u32) -> u32 {
+    unsafe {
+        dbg_assert!(mem8.is_null());
+    };
+    dbg_log!("Allocate memory size={}m", size >> 20);
+    let layout = alloc::Layout::from_size_align(size as usize, 0x1000).unwrap();
+    let ptr = unsafe { alloc::alloc(layout) as u32 };
+    unsafe {
+        mem8 = ptr as *mut u8;
+    };
+    ptr
+}
+
+#[no_mangle]
+pub unsafe fn zero_memory(addr: u32, size: u32) {
+    ptr::write_bytes(mem8.offset(addr as isize), 0, size as usize);
+}
+
+#[allow(non_upper_case_globals)]
+pub static mut vga_mem8: *mut u8 = ptr::null_mut();
+#[allow(non_upper_case_globals)]
+pub static mut vga_memory_size: u32 = 0;
+
+#[no_mangle]
+pub fn svga_allocate_memory(size: u32) -> u32 {
+    unsafe {
+        dbg_assert!(vga_mem8.is_null());
+    };
+    let layout = alloc::Layout::from_size_align(size as usize, 0x1000).unwrap();
+    let ptr = unsafe { alloc::alloc(layout) };
+    dbg_assert!(
+        size & (1 << 12 << 6) == 0,
+        "size not aligned to dirty_bitmap"
+    );
+    unsafe {
+        vga_mem8 = ptr;
+        vga_memory_size = size;
+        vga::set_dirty_bitmap_size(size >> 12 >> 6);
+    };
+    ptr as u32
+}
+
+#[no_mangle]
+pub fn in_mapped_range(addr: u32) -> bool {
+    return addr >= 0xA0000 && addr < 0xC0000 || addr >= unsafe { *memory_size };
+}
+
+pub const VGA_LFB_ADDRESS: u32 = 0xE0000000;
+pub fn in_svga_lfb(addr: u32) -> bool {
+    addr >= VGA_LFB_ADDRESS && addr <= unsafe { VGA_LFB_ADDRESS + (vga_memory_size - 1) }
+}
+
+#[no_mangle]
+pub fn read8(addr: u32) -> i32 {
+    if in_mapped_range(addr) {
+        if in_svga_lfb(addr) {
+            unsafe { *vga_mem8.offset((addr - VGA_LFB_ADDRESS) as isize) as i32 }
+        }
+        else if addr >= APIC_MEM_ADDRESS && addr < APIC_MEM_ADDRESS + APIC_MEM_SIZE {
+            apic::read32((addr - APIC_MEM_ADDRESS) & !3) as i32 >> 8 * (addr & 3) & 0xFF
+        }
+        else if addr >= IOAPIC_MEM_ADDRESS && addr < IOAPIC_MEM_ADDRESS + IOAPIC_MEM_SIZE {
+            ioapic::read32((addr - IOAPIC_MEM_ADDRESS) & !3) as i32 >> 8 * (addr & 3) & 0xFF
+        }
+        else {
+            unsafe { ext::mmap_read8(addr) }
+        }
+    }
+    else {
+        read8_no_mmap_check(addr)
+    }
+}
+pub fn read8_no_mmap_check(addr: u32) -> i32 { unsafe { *mem8.offset(addr as isize) as i32 } }
+
+#[no_mangle]
+pub fn read16(addr: u32) -> i32 {
+    if in_mapped_range(addr) {
+        if in_svga_lfb(addr) {
+            unsafe {
+                ptr::read_unaligned(vga_mem8.offset((addr - VGA_LFB_ADDRESS) as isize) as *const u16)
+                    as i32
+            }
+        }
+        else {
+            read8(addr) | read8(addr + 1) << 8
+        }
+    }
+    else {
+        read16_no_mmap_check(addr)
+    }
+}
+pub fn read16_no_mmap_check(addr: u32) -> i32 {
+    unsafe { ptr::read_unaligned(mem8.offset(addr as isize) as *const u16) as i32 }
+}
+
+#[no_mangle]
+pub fn read32s(addr: u32) -> i32 {
+    if in_mapped_range(addr) {
+        if in_svga_lfb(addr) {
+            unsafe {
+                ptr::read_unaligned(vga_mem8.offset((addr - VGA_LFB_ADDRESS) as isize) as *const i32)
+            } // XXX
+        }
+        else if addr >= APIC_MEM_ADDRESS && addr < APIC_MEM_ADDRESS + APIC_MEM_SIZE {
+            apic::read32(addr - APIC_MEM_ADDRESS) as i32
+        }
+        else if addr >= IOAPIC_MEM_ADDRESS && addr < IOAPIC_MEM_ADDRESS + IOAPIC_MEM_SIZE {
+            ioapic::read32(addr - IOAPIC_MEM_ADDRESS) as i32
+        }
+        else {
+            unsafe { ext::mmap_read32(addr) }
+        }
+    }
+    else {
+        read32_no_mmap_check(addr)
+    }
+}
+pub fn read32_no_mmap_check(addr: u32) -> i32 {
+    unsafe { ptr::read_unaligned(mem8.offset(addr as isize) as *const i32) }
+}
+
+pub unsafe fn read64s(addr: u32) -> i64 {
+    if in_mapped_range(addr) {
+        if in_svga_lfb(addr) {
+            ptr::read_unaligned(vga_mem8.offset((addr - VGA_LFB_ADDRESS) as isize) as *const i64)
+        }
+        else {
+            read32s(addr) as i64 | (read32s(addr + 4) as i64) << 32
+        }
+    }
+    else {
+        ptr::read_unaligned(mem8.offset(addr as isize) as *const i64)
+    }
+}
+
+pub unsafe fn read128(addr: u32) -> reg128 {
+    if in_mapped_range(addr) {
+        if in_svga_lfb(addr) {
+            ptr::read_unaligned(vga_mem8.offset((addr - VGA_LFB_ADDRESS) as isize) as *const reg128)
+        }
+        else {
+            reg128 {
+                i32: [
+                    read32s(addr + 0),
+                    read32s(addr + 4),
+                    read32s(addr + 8),
+                    read32s(addr + 12),
+                ],
+            }
+        }
+    }
+    else {
+        ptr::read_unaligned(mem8.offset(addr as isize) as *const reg128)
+    }
+}
+
+#[no_mangle]
+pub unsafe fn write8(addr: u32, value: i32) {
+    if in_mapped_range(addr) {
+        mmap_write8(addr, value & 0xFF);
+    }
+    else {
+        jit::jit_dirty_page(Page::page_of(addr));
+        write8_no_mmap_or_dirty_check(addr, value);
+    };
+}
+
+pub unsafe fn write8_no_mmap_or_dirty_check(addr: u32, value: i32) {
+    *mem8.offset(addr as isize) = value as u8
+}
+
+#[no_mangle]
+pub unsafe fn write16(addr: u32, value: i32) {
+    if in_mapped_range(addr) {
+        mmap_write16(addr, value & 0xFFFF);
+    }
+    else {
+        jit::jit_dirty_cache_small(addr, addr + 2);
+        write16_no_mmap_or_dirty_check(addr, value);
+    };
+}
+pub unsafe fn write16_no_mmap_or_dirty_check(addr: u32, value: i32) {
+    ptr::write_unaligned(mem8.offset(addr as isize) as *mut u16, value as u16)
+}
+
+#[no_mangle]
+pub unsafe fn write32(addr: u32, value: i32) {
+    if in_mapped_range(addr) {
+        mmap_write32(addr, value);
+    }
+    else {
+        jit::jit_dirty_cache_small(addr, addr + 4);
+        write32_no_mmap_or_dirty_check(addr, value);
+    }
+}
+
+pub unsafe fn write32_no_mmap_or_dirty_check(addr: u32, value: i32) {
+    ptr::write_unaligned(mem8.offset(addr as isize) as *mut i32, value)
+}
+
+pub unsafe fn write64_no_mmap_or_dirty_check(addr: u32, value: u64) {
+    ptr::write_unaligned(mem8.offset(addr as isize) as *mut u64, value)
+}
+
+pub unsafe fn write128_no_mmap_or_dirty_check(addr: u32, value: reg128) {
+    ptr::write_unaligned(mem8.offset(addr as isize) as *mut reg128, value)
+}
+
+pub unsafe fn memset_no_mmap_or_dirty_check(addr: u32, value: u8, count: u32) {
+    ptr::write_bytes(mem8.offset(addr as isize), value, count as usize);
+}
+
+pub unsafe fn memcpy_no_mmap_or_dirty_check(src_addr: u32, dst_addr: u32, count: u32) {
+    dbg_assert!(src_addr < *memory_size);
+    dbg_assert!(dst_addr < *memory_size);
+    ptr::copy(
+        mem8.offset(src_addr as isize),
+        mem8.offset(dst_addr as isize),
+        count as usize,
+    )
+}
+
+pub unsafe fn memcpy_into_svga_lfb(src_addr: u32, dst_addr: u32, count: u32) {
+    dbg_assert!(src_addr < *memory_size);
+    dbg_assert!(in_svga_lfb(dst_addr));
+    dbg_assert!(Page::page_of(dst_addr) == Page::page_of(dst_addr + count - 1));
+    vga::mark_dirty(dst_addr);
+    ptr::copy_nonoverlapping(
+        mem8.offset(src_addr as isize),
+        vga_mem8.offset((dst_addr - VGA_LFB_ADDRESS) as isize),
+        count as usize,
+    )
+}
+
+pub unsafe fn mmap_write8(addr: u32, value: i32) {
+    if in_svga_lfb(addr) {
+        vga::mark_dirty(addr);
+        *vga_mem8.offset((addr - VGA_LFB_ADDRESS) as isize) = value as u8
+    }
+    else {
+        ext::mmap_write8(addr, value)
+    }
+}
+pub unsafe fn mmap_write16(addr: u32, value: i32) {
+    if in_svga_lfb(addr) {
+        vga::mark_dirty(addr);
+        ptr::write_unaligned(
+            vga_mem8.offset((addr - VGA_LFB_ADDRESS) as isize) as *mut u16,
+            value as u16,
+        )
+    }
+    else {
+        ext::mmap_write16(addr, value)
+    }
+}
+pub unsafe fn mmap_write32(addr: u32, value: i32) {
+    if in_svga_lfb(addr) {
+        vga::mark_dirty(addr);
+        ptr::write_unaligned(
+            vga_mem8.offset((addr - VGA_LFB_ADDRESS) as isize) as *mut i32,
+            value,
+        )
+    }
+    else if addr >= APIC_MEM_ADDRESS && addr < APIC_MEM_ADDRESS + APIC_MEM_SIZE {
+        apic::write32(addr - APIC_MEM_ADDRESS, value as u32);
+        handle_irqs();
+    }
+    else if addr >= IOAPIC_MEM_ADDRESS && addr < IOAPIC_MEM_ADDRESS + IOAPIC_MEM_SIZE {
+        ioapic::write32(addr - IOAPIC_MEM_ADDRESS, value as u32);
+        handle_irqs();
+    }
+    else {
+        ext::mmap_write32(addr, value)
+    }
+}
+pub unsafe fn mmap_write64(addr: u32, value: u64) {
+    if in_svga_lfb(addr) {
+        vga::mark_dirty(addr);
+        ptr::write_unaligned(
+            vga_mem8.offset((addr - VGA_LFB_ADDRESS) as isize) as *mut u64,
+            value,
+        )
+    }
+    else {
+        ext::mmap_write64(addr, value as i32, (value >> 32) as i32)
+    }
+}
+pub unsafe fn mmap_write128(addr: u32, v0: u64, v1: u64) {
+    if in_svga_lfb(addr) {
+        vga::mark_dirty(addr);
+        ptr::write_unaligned(
+            vga_mem8.offset((addr - VGA_LFB_ADDRESS) as isize) as *mut u64,
+            v0,
+        );
+        ptr::write_unaligned(
+            vga_mem8.offset((addr - VGA_LFB_ADDRESS + 8) as isize) as *mut u64,
+            v1,
+        )
+    }
+    else {
+        ext::mmap_write128(
+            addr,
+            v0 as i32,
+            (v0 >> 32) as i32,
+            v1 as i32,
+            (v1 >> 32) as i32,
+        )
+    }
+}
+
+#[no_mangle]
+pub unsafe fn is_memory_zeroed(addr: u32, length: u32) -> bool {
+    dbg_assert!(addr % 8 == 0);
+    dbg_assert!(length % 8 == 0);
+    for i in (addr..addr + length).step_by(8) {
+        if *(mem8.offset(i as isize) as *const i64) != 0 {
+            return false;
+        }
+    }
+    return true;
+}