vertigo_vhdl 0.8.9 → 0.8.10

checksums.yaml

@@ -1,7 +1,7 @@
 ---
 SHA256:
-  metadata.gz: 7e866afeff8d83a8d41c6f02a4084ff2133e33e761f4a56e630e0d66d18482d4
-  data.tar.gz: 882a98fbeaa78f7d0c998a6949e473d02930edd11f76de78ecb38753958c7b05
+  metadata.gz: beaea4415336c64910ab051d6882dbc9e5320f65a9531a2862a336f30142d7ff
+  data.tar.gz: f190bce2287c4d40b69a191e5c34ae6bfaee628f3c19213ddec253d8c4fb6a0f
 SHA512:
-  metadata.gz: 50dc9ace16e8d93780258eaa055ddb7cb42c53e470261b124cadfc6871603bde2e5e598d4414ff5bb788796f38cea09968b2aa14a98e696e6596ac8af2685bcb
-  data.tar.gz: 9ec14b4037ff37532341cceacade51ad22d7859de92af2ac1927d582e168c21ac732992e6878600701999c6349302c2896141b578eaa2480af0c1b6773888466
+  metadata.gz: e35cadb37ba4f987501b079bc9c69f73bbb3d1699ec1966410448e4dd4637b26f5d3aa205121cf1fbebcf94c6ccf4de21dd21e121a3291793d6c264bfb980b32
+  data.tar.gz: 6bdd446db85780a7bd16214776651fed9896d6cfd5edf5e4a4fae483bb0b2d8323cf6d890722f346586f0e2ceabf0bbeefda219d46cfa65bc64cfd9fdebc76e9

data/lib/vertigo/parser.rb

@@ -801,12 +801,25 @@ module Vertigo
       expect :if
       ret.cond=parse_expression
       expect :generate
-      if showNext.is_a?(:begin) # seems optional!
+      # maybe local declarations :
+      if showNext.is_a? [:signal,:constant]
+        while showNext.is_not_a?(:begin)
+          parse_decls
+        end
+      end
+
+      #...or simply "begin"
+      if showNext.is_a?(:begin)
         acceptIt
       end
-      ret.body=parse_concurrent_stmt
+      ret.body=body=Body.new
+
+      while !showNext.is_a?(:end)
+        body << parse_concurrent_stmt
+      end
       expect :end
       expect :generate
+      maybe :ident
       expect :semicolon
       ret
     end
@@ -818,16 +831,26 @@ module Vertigo
       expect :in
       ret.range=parse_discrete_range
       expect :generate
-      while showNext.is_not_a?(:begin)
-        parse_decls
+
+      # maybe local declarations :
+      if showNext.is_a? [:signal,:constant]
+        while showNext.is_not_a?(:begin)
+          parse_decls
+        end
+      end
+
+      #...or simply "begin"
+      if showNext.is_a?(:begin)
+        acceptIt
       end
       ret.body=body=Body.new
-      expect :begin
+
       while !showNext.is_a?(:end)
         body << parse_concurrent_stmt
       end
       expect :end
       expect :generate
+      maybe :ident
       expect :semicolon
       ret
     end

data/lib/vertigo/tb_generator.rb

@@ -145,7 +145,7 @@ module Vertigo
       code << "report \"waiting for asynchronous reset\";"
       code << "wait until #{@reset_name}='1';"
       code << "wait_cycles(10);"
-      code << "wait_cycles(100);"
+      code << "wait_cycles(200);"
       code << "report \"end of simulation\";"
       code << "running <= false;"
       code << "wait;"

data/lib/vertigo/version.rb

@@ -1,3 +1,3 @@
 module Vertigo
-  VERSION="0.8.9"
+  VERSION="0.8.10"
 end

data/tests/parser_tests/test_adder_rca_vhdl93.vhd

@@ -0,0 +1,37 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+architecture rca_vhdl_93 of adder is
+  signal co : std_logic_vector(N-1 downto 0);
+begin
+
+  gen_loop: for i in 0 to N-1 generate
+
+    bit0 : if i=0 generate
+      fa_0: entity work.fa(arch)
+      port map(
+        a  => a(0),
+        b  => b(0),
+        ci => '0',
+        s  => sum(0),
+        co => co(0)
+      );
+    end generate bit0;
+
+    other_bits : if i >0  generate
+      fa_i : entity work.fa(arch)
+      port map(
+        a  => a(i),
+        b  => b(i),
+        ci => co(i-1),
+        s  => sum(i),
+        co => co(i)
+      );
+    end generate other_bits;
+
+  end generate gen_loop;
+
+  carry <= co(N-1);
+
+end architecture;

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: vertigo_vhdl
 version: !ruby/object:Gem::Version
-  version: 0.8.9
+  version: 0.8.10
 platform: ruby
 authors:
 - Jean-Christophe Le Lann
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2021-04-06 00:00:00.000000000 Z
+date: 2021-09-07 00:00:00.000000000 Z
 dependencies: []
 description: A Ruby handwritten VHDL parser and utilities
 email: jean-christophe.le_lann@ensta-bretagne.fr
@@ -37,167 +37,86 @@ files:
 - lib/vertigo/visitor_vertigo_rkgen.rb
 - tests/ghdl_tests/fsm.vhd
 - tests/ghdl_tests/fsm_synth.vhd
-- tests/ghdl_tests/test_fsm.vhd
-- tests/parser_tests/else.vhd
-- tests/parser_tests/pingpong.vhd
 - tests/parser_tests/test_MUST_fail.vhd
 - tests/parser_tests/test_accelerator.vhd
-- tests/parser_tests/test_accelerator_pp.vhd
+- tests/parser_tests/test_adder_rca_vhdl93.vhd
 - tests/parser_tests/test_aggregate.vhd
-- tests/parser_tests/test_aggregate_pp.vhd
 - tests/parser_tests/test_archi_1.vhd
-- tests/parser_tests/test_archi_1_pp.vhd
 - tests/parser_tests/test_array_array_00.vhd
-- tests/parser_tests/test_array_array_00_pp.vhd
 - tests/parser_tests/test_array_urange.vhd
-- tests/parser_tests/test_array_urange_pp.vhd
 - tests/parser_tests/test_chu-1.vhd
-- tests/parser_tests/test_chu-1_pp.vhd
 - tests/parser_tests/test_concat.vhd
-- tests/parser_tests/test_concat_pp.vhd
 - tests/parser_tests/test_counter.vhd
-- tests/parser_tests/test_counter_pp.vhd
 - tests/parser_tests/test_de2.vhd
-- tests/parser_tests/test_de2_pp.vhd
 - tests/parser_tests/test_encode.vhd
-- tests/parser_tests/test_encode_pp.vhd
 - tests/parser_tests/test_fsm.vhd
-- tests/parser_tests/test_fsm_pp.vhd
 - tests/parser_tests/test_fsm_synth.vhd
-- tests/parser_tests/test_fsm_synth_pp.vhd
 - tests/parser_tests/test_function-01.vhd
-- tests/parser_tests/test_function-01_pp.vhd
 - tests/parser_tests/test_lfsr.vhd
-- tests/parser_tests/test_lfsr_pp.vhd
 - tests/parser_tests/test_microwatt_cache_ram.vhd
-- tests/parser_tests/test_microwatt_cache_ram_pp.vhd
 - tests/parser_tests/test_microwatt_common.vhd
-- tests/parser_tests/test_microwatt_common_pp.vhd
 - tests/parser_tests/test_microwatt_control.vhd
-- tests/parser_tests/test_microwatt_control_pp.vhd
 - tests/parser_tests/test_microwatt_core.vhd
 - tests/parser_tests/test_microwatt_core_debug.vhd
-- tests/parser_tests/test_microwatt_core_debug_pp.vhd
-- tests/parser_tests/test_microwatt_core_pp.vhd
 - tests/parser_tests/test_microwatt_core_tb.vhd
-- tests/parser_tests/test_microwatt_core_tb_pp.vhd
 - tests/parser_tests/test_microwatt_countzero.vhd
-- tests/parser_tests/test_microwatt_countzero_pp.vhd
 - tests/parser_tests/test_microwatt_countzero_tb.vhd
-- tests/parser_tests/test_microwatt_countzero_tb_pp.vhd
 - tests/parser_tests/test_microwatt_cr_file.vhd
-- tests/parser_tests/test_microwatt_cr_file_pp.vhd
 - tests/parser_tests/test_microwatt_cr_hazard.vhd
-- tests/parser_tests/test_microwatt_cr_hazard_pp.vhd
 - tests/parser_tests/test_microwatt_crhelpers.vhd
-- tests/parser_tests/test_microwatt_crhelpers_pp.vhd
 - tests/parser_tests/test_microwatt_dcache.vhd
-- tests/parser_tests/test_microwatt_dcache_pp.vhd
 - tests/parser_tests/test_microwatt_dcache_tb.vhd
-- tests/parser_tests/test_microwatt_dcache_tb_pp.vhd
 - tests/parser_tests/test_microwatt_decode1.vhd
-- tests/parser_tests/test_microwatt_decode1_pp.vhd
 - tests/parser_tests/test_microwatt_decode2.vhd
-- tests/parser_tests/test_microwatt_decode2_pp.vhd
 - tests/parser_tests/test_microwatt_decode_types.vhd
-- tests/parser_tests/test_microwatt_decode_types_pp.vhd
 - tests/parser_tests/test_microwatt_divider.vhd
-- tests/parser_tests/test_microwatt_divider_pp.vhd
 - tests/parser_tests/test_microwatt_divider_tb.vhd
-- tests/parser_tests/test_microwatt_divider_tb_pp.vhd
 - tests/parser_tests/test_microwatt_dmi_dtm_dummy.vhd
-- tests/parser_tests/test_microwatt_dmi_dtm_dummy_pp.vhd
 - tests/parser_tests/test_microwatt_dmi_dtm_tb.vhd
-- tests/parser_tests/test_microwatt_dmi_dtm_tb_pp.vhd
 - tests/parser_tests/test_microwatt_dmi_dtm_xilinx.vhd
-- tests/parser_tests/test_microwatt_dmi_dtm_xilinx_pp.vhd
 - tests/parser_tests/test_microwatt_execute1.vhd
-- tests/parser_tests/test_microwatt_execute1_pp.vhd
 - tests/parser_tests/test_microwatt_fetch1.vhd
-- tests/parser_tests/test_microwatt_fetch1_pp.vhd
 - tests/parser_tests/test_microwatt_fetch2.vhd
-- tests/parser_tests/test_microwatt_fetch2_pp.vhd
 - tests/parser_tests/test_microwatt_glibc_random.vhd
 - tests/parser_tests/test_microwatt_glibc_random_helpers.vhd
-- tests/parser_tests/test_microwatt_glibc_random_helpers_pp.vhd
-- tests/parser_tests/test_microwatt_glibc_random_pp.vhd
 - tests/parser_tests/test_microwatt_gpr_hazard.vhd
-- tests/parser_tests/test_microwatt_gpr_hazard_pp.vhd
 - tests/parser_tests/test_microwatt_helpers.vhd
-- tests/parser_tests/test_microwatt_helpers_pp.vhd
 - tests/parser_tests/test_microwatt_icache.vhd
-- tests/parser_tests/test_microwatt_icache_pp.vhd
 - tests/parser_tests/test_microwatt_icache_tb.vhd
-- tests/parser_tests/test_microwatt_icache_tb_pp.vhd
 - tests/parser_tests/test_microwatt_insn_helpers.vhd
-- tests/parser_tests/test_microwatt_insn_helpers_pp.vhd
 - tests/parser_tests/test_microwatt_loadstore1.vhd
-- tests/parser_tests/test_microwatt_loadstore1_pp.vhd
 - tests/parser_tests/test_microwatt_logical.vhd
-- tests/parser_tests/test_microwatt_logical_pp.vhd
 - tests/parser_tests/test_microwatt_multiply.vhd
-- tests/parser_tests/test_microwatt_multiply_pp.vhd
 - tests/parser_tests/test_microwatt_multiply_tb.vhd
-- tests/parser_tests/test_microwatt_multiply_tb_pp.vhd
 - tests/parser_tests/test_microwatt_plru.vhd
-- tests/parser_tests/test_microwatt_plru_pp.vhd
 - tests/parser_tests/test_microwatt_plru_tb.vhd
-- tests/parser_tests/test_microwatt_plru_tb_pp.vhd
 - tests/parser_tests/test_microwatt_ppc_fx_insns.vhd
-- tests/parser_tests/test_microwatt_ppc_fx_insns_pp.vhd
 - tests/parser_tests/test_microwatt_register_file.vhd
-- tests/parser_tests/test_microwatt_register_file_pp.vhd
 - tests/parser_tests/test_microwatt_rotator.vhd
-- tests/parser_tests/test_microwatt_rotator_pp.vhd
 - tests/parser_tests/test_microwatt_rotator_tb.vhd
-- tests/parser_tests/test_microwatt_rotator_tb_pp.vhd
 - tests/parser_tests/test_microwatt_sim_bram.vhd
 - tests/parser_tests/test_microwatt_sim_bram_helpers.vhd
-- tests/parser_tests/test_microwatt_sim_bram_helpers_pp.vhd
-- tests/parser_tests/test_microwatt_sim_bram_pp.vhd
 - tests/parser_tests/test_microwatt_sim_console.vhd
-- tests/parser_tests/test_microwatt_sim_console_pp.vhd
 - tests/parser_tests/test_microwatt_sim_jtag.vhd
-- tests/parser_tests/test_microwatt_sim_jtag_pp.vhd
 - tests/parser_tests/test_microwatt_sim_jtag_socket.vhd
-- tests/parser_tests/test_microwatt_sim_jtag_socket_pp.vhd
 - tests/parser_tests/test_microwatt_sim_uart.vhd
-- tests/parser_tests/test_microwatt_sim_uart_pp.vhd
 - tests/parser_tests/test_microwatt_soc.vhd
-- tests/parser_tests/test_microwatt_soc_pp.vhd
 - tests/parser_tests/test_microwatt_utils.vhd
-- tests/parser_tests/test_microwatt_utils_pp.vhd
 - tests/parser_tests/test_microwatt_wishbone_arbiter.vhd
-- tests/parser_tests/test_microwatt_wishbone_arbiter_pp.vhd
 - tests/parser_tests/test_microwatt_wishbone_bram_tb.vhd
-- tests/parser_tests/test_microwatt_wishbone_bram_tb_pp.vhd
 - tests/parser_tests/test_microwatt_wishbone_bram_wrapper.vhd
-- tests/parser_tests/test_microwatt_wishbone_bram_wrapper_pp.vhd
 - tests/parser_tests/test_microwatt_wishbone_debug_master.vhd
-- tests/parser_tests/test_microwatt_wishbone_debug_master_pp.vhd
 - tests/parser_tests/test_microwatt_wishbone_types.vhd
-- tests/parser_tests/test_microwatt_wishbone_types_pp.vhd
 - tests/parser_tests/test_microwatt_writeback.vhd
-- tests/parser_tests/test_microwatt_writeback_pp.vhd
 - tests/parser_tests/test_package-1.vhd
-- tests/parser_tests/test_package-1_pp.vhd
 - tests/parser_tests/test_precedence.vhd
-- tests/parser_tests/test_precedence_pp.vhd
 - tests/parser_tests/test_selected_sig.vhd
-- tests/parser_tests/test_selected_sig_pp.vhd
 - tests/parser_tests/test_slice.vhd
-- tests/parser_tests/test_slice_pp.vhd
 - tests/parser_tests/test_tb-00.vhd
-- tests/parser_tests/test_tb-00_pp.vhd
 - tests/parser_tests/test_type_decl_02.vhd
-- tests/parser_tests/test_type_decl_02_pp.vhd
 - tests/parser_tests/test_use.vhd
-- tests/parser_tests/test_use_pp.vhd
 - tests/parser_tests/test_while_1.vhd
-- tests/parser_tests/test_while_1_pp.vhd
 - tests/parser_tests/test_with-00.vhd
-- tests/parser_tests/test_with-00_pp.vhd
-- tests/tb_gen_tests/test_accelerator.vhd
 homepage: http://www.github.com/JC-LL/vertigo
 licenses:
 - GPL-2.0-only
@@ -217,7 +136,7 @@ required_rubygems_version: !ruby/object:Gem::Requirement
     - !ruby/object:Gem::Version
       version: '0'
 requirements: []
-rubygems_version: 3.0.6
+rubygems_version: 3.2.3
 signing_key: 
 specification_version: 4
 summary: VHDL parser and utilities

data/tests/ghdl_tests/test_fsm.vhd

@@ -1,162 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-entity fsm is
-  port (
-    reset_n: in std_logic;
-    clk: in std_logic;
-    switches: in std_logic_vector (7 downto 0);
-    leds: out std_logic_vector (7 downto 0)
-  );
-end entity;
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-architecture rtl of fsm is
-  signal wrap_reset_n: std_logic;
-  signal wrap_clk: std_logic;
-  signal wrap_switches: std_logic_vector (7 downto 0);
-  signal wrap_leds: std_logic_vector (7 downto 0);
-  signal state : std_logic_vector (2 downto 0);
-  signal state_c : std_logic_vector (2 downto 0);
-  signal n4_o : std_logic;
-  signal n9_q : std_logic_vector (2 downto 0);
-  signal n12_o : std_logic;
-  signal n14_o : std_logic_vector (2 downto 0);
-  signal n15_o : std_logic;
-  signal n17_o : std_logic_vector (2 downto 0);
-  signal n18_o : std_logic;
-  signal n20_o : std_logic_vector (2 downto 0);
-  signal n21_o : std_logic;
-  signal n23_o : std_logic_vector (2 downto 0);
-  signal n24_o : std_logic;
-  signal n26_o : std_logic_vector (2 downto 0);
-  signal n27_o : std_logic;
-  signal n29_o : std_logic_vector (2 downto 0);
-  signal n30_o : std_logic;
-  signal n32_o : std_logic_vector (2 downto 0);
-  signal n33_o : std_logic;
-  signal n35_o : std_logic_vector (2 downto 0);
-  signal n36_o : std_logic_vector (1 downto 0);
-  signal n37_o : std_logic_vector (2 downto 0);
-  signal n38_o : std_logic_vector (2 downto 0);
-  signal n39_o : std_logic;
-  signal n40_o : std_logic_vector (2 downto 0);
-  signal n44_o : std_logic;
-  signal n45_o : std_logic_vector (7 downto 0);
-  signal n48_o : std_logic;
-  signal n49_o : std_logic_vector (7 downto 0);
-  signal n52_o : std_logic;
-  signal n53_o : std_logic_vector (7 downto 0);
-  signal n56_o : std_logic;
-  signal n57_o : std_logic_vector (7 downto 0);
-  signal n60_o : std_logic;
-  signal n61_o : std_logic_vector (7 downto 0);
-  signal n64_o : std_logic;
-  signal n65_o : std_logic_vector (7 downto 0);
-  signal n68_o : std_logic;
-  signal n69_o : std_logic_vector (7 downto 0);
-begin
-  wrap_reset_n <= reset_n;
-  wrap_clk <= clk;
-  wrap_switches <= switches;
-  leds <= wrap_leds;
-  wrap_leds <= n45_o;
-  -- fsm.vhd:16:10
-  state <= n9_q; -- (signal)
-  -- fsm.vhd:16:16
-  state_c <= n40_o; -- (signal)
-  -- fsm.vhd:20:15
-  n4_o <= not wrap_reset_n;
-  -- fsm.vhd:22:5
-  process (wrap_clk, n4_o)
-  begin
-    if n4_o = '1' then
-      n9_q <= "000";
-    elsif rising_edge (wrap_clk) then
-      n9_q <= state_c;
-    end if;
-  end process;
-  -- fsm.vhd:33:20
-  n12_o <= wrap_switches (0);
-  -- fsm.vhd:33:9
-  n14_o <= state when n12_o = '0' else "001";
-  -- fsm.vhd:37:20
-  n15_o <= wrap_switches (1);
-  -- fsm.vhd:37:9
-  n17_o <= state when n15_o = '0' else "010";
-  -- fsm.vhd:41:20
-  n18_o <= wrap_switches (2);
-  -- fsm.vhd:41:9
-  n20_o <= state when n18_o = '0' else "011";
-  -- fsm.vhd:45:20
-  n21_o <= wrap_switches (3);
-  -- fsm.vhd:45:9
-  n23_o <= state when n21_o = '0' else "100";
-  -- fsm.vhd:49:20
-  n24_o <= wrap_switches (4);
-  -- fsm.vhd:49:9
-  n26_o <= state when n24_o = '0' else "101";
-  -- fsm.vhd:53:20
-  n27_o <= wrap_switches (5);
-  -- fsm.vhd:53:9
-  n29_o <= state when n27_o = '0' else "110";
-  -- fsm.vhd:57:20
-  n30_o <= wrap_switches (6);
-  -- fsm.vhd:57:9
-  n32_o <= state when n30_o = '0' else "111";
-  -- fsm.vhd:61:20
-  n33_o <= wrap_switches (7);
-  -- fsm.vhd:61:9
-  n35_o <= state when n33_o = '0' else "000";
-  -- fsm.vhd:31:10
-  n36_o <= state (1 downto 0);
-  -- fsm.vhd:31:10
-  with n36_o select n37_o <=
-    n14_o when "00",
-    n17_o when "01",
-    n20_o when "10",
-    n23_o when "11",
-    "XXX" when others;
-  -- fsm.vhd:31:10
-  with n36_o select n38_o <=
-    n26_o when "00",
-    n29_o when "01",
-    n32_o when "10",
-    n35_o when "11",
-    "XXX" when others;
-  -- fsm.vhd:31:10
-  n39_o <= state (2);
-  -- fsm.vhd:31:10
-  n40_o <= n37_o when n39_o = '0' else n38_o;
-  -- fsm.vhd:71:56
-  n44_o <= '1' when state = "000" else '0';
-  -- fsm.vhd:71:46
-  n45_o <= n49_o when n44_o = '0' else "00000000";
-  -- fsm.vhd:72:56
-  n48_o <= '1' when state = "001" else '0';
-  -- fsm.vhd:71:60
-  n49_o <= n53_o when n48_o = '0' else "00000001";
-  -- fsm.vhd:73:56
-  n52_o <= '1' when state = "010" else '0';
-  -- fsm.vhd:72:60
-  n53_o <= n57_o when n52_o = '0' else "00000010";
-  -- fsm.vhd:74:56
-  n56_o <= '1' when state = "011" else '0';
-  -- fsm.vhd:73:60
-  n57_o <= n61_o when n56_o = '0' else "00000011";
-  -- fsm.vhd:75:56
-  n60_o <= '1' when state = "100" else '0';
-  -- fsm.vhd:74:60
-  n61_o <= n65_o when n60_o = '0' else "00000100";
-  -- fsm.vhd:76:56
-  n64_o <= '1' when state = "101" else '0';
-  -- fsm.vhd:75:60
-  n65_o <= n69_o when n64_o = '0' else "00000101";
-  -- fsm.vhd:77:56
-  n68_o <= '1' when state = "110" else '0';
-  -- fsm.vhd:76:60
-  n69_o <= "00000111" when n68_o = '0' else "00000110";
-end rtl;