vertigo_vhdl 0.8.9 → 0.8.10

data/tests/parser_tests/test_microwatt_countzero_tb_pp.vhd

@@ -1,70 +0,0 @@
--- generated by Vertigo VHDL tool
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-library work;
-use work.common.all;
-use work.glibc_random.all;
- 
-entity countzero_tb is
-end entity countzero_tb;
- 
-architecture behave of countzero_tb is
-  constant clk_period : time := 10 ns;
-  signal rs : std_ulogic_vector(63 downto 0);
-  signal is_32bit : std_ulogic;
-  signal count_right : std_ulogic := '0';
-  signal result : std_ulogic_vector(63 downto 0);
-  signal randno : std_ulogic_vector(63 downto 0);
-  signal clk : std_ulogic;
-begin
- 
-  zerocounter_0 : entity work.zero_counter
-    port map(
-      clk => clk,
-      rs => rs,
-      result => result,
-      count_right => count_right,
-      is_32bit => is_32bit);
-   
-   
-  clk_process : process
-  begin
-    clk <= '0';
-    wait clk_period / 2;
-    clk <= '1';
-    wait clk_period / 2;
-  end process;
-   
-  stim_process : process
-    variable r : std_ulogic_vector(63 downto 0);
-  begin
-    report "test zero input";
-    rs <= (others => '0');
-    is_32bit <= '0';
-    count_right <= '0';
-    wait clk_period;
-    assert result = x"0000000000000040"
-      report "bad cntlzd 0 = " & to_hstring(result);
-    count_right <= '1';
-    wait clk_period;
-    assert result = x"0000000000000040"
-      report "bad cnttzd 0 = " & to_hstring(result);
-    is_32bit <= '1';
-    count_right <= '0';
-    wait clk_period;
-    assert result = x"0000000000000020"
-      report "bad cntlzw 0 = " & to_hstring(result);
-    count_right <= '1';
-    wait clk_period;
-    assert result = x"0000000000000020"
-      report "bad cnttzw 0 = " & to_hstring(result);
-    report "test cntlzd/w";
-    count_right <= '0';
-    report "test cnttzd/w";
-    count_right <= '1';
-    assert false
-      report "end of test" severity failure;
-    wait ;
-  end process;
-end behave;

data/tests/parser_tests/test_microwatt_cr_file_pp.vhd

@@ -1,74 +0,0 @@
--- generated by Vertigo VHDL tool
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-library work;
-use work.common.all;
- 
-entity cr_file is
-  generic(
-    sim : booleanfalse := false);
-  port(
-    clk : in std_logic;
-    d_in : in decode2tocrfiletype;
-    d_out : out crfiletodecode2type;
-    w_in : in writebacktocrfiletype;
-    sim_dump : in std_ulogic);
-end entity cr_file;
- 
-architecture behaviour of cr_file is
-  signal crs : std_ulogic_vector(31 downto 0) := (others => '0');
-  signal crs_updated : std_ulogic_vector(31 downto 0);
-  signal xerc : xer_common_t := xerc_init;
-  signal xerc_updated : xer_common_t;
-begin
- 
-   
-  cr_create_0 : process(all)
-    variable hi : integer;
-    variable lo : integer := 0;
-    variable cr_tmp : std_ulogic_vector(31 downto 0) := (others => '0');
-  begin
-    cr_tmp := crs;
-    crs_updated <= cr_tmp;
-    if w_in.write_xerc_enable = '1' then
-      xerc_updated <= w_in.write_xerc_data;
-    else
-      xerc_updated <= xerc;
-    end if;
-  end process;
-   
-  cr_write_0 : process(clk)
-  begin
-    if rising_edge(clk) then
-      if w_in.write_cr_enable = '1' then
-        report "writing " & to_hstring(w_in.write_cr_data) & " to cr mask " & to_hstring(w_in.write_cr_mask);
-        crs <= crs_updated;
-      end if;
-      if w_in.write_xerc_enable = '1' then
-        report "writing xerc";
-        xerc <= xerc_updated;
-      end if;
-    end if;
-  end process;
-   
-  cr_read_0 : process(all)
-  begin
-    if d_in.read = '1' then
-      report "reading cr " & to_hstring(crs_updated);
-    end if;
-    d_out.read_cr_data <= crs_updated;
-    d_out.read_xerc_data <= xerc_updated;
-  end process;
-  if sim generate
-     
-    dump_cr : process(all)
-    begin
-      if sim_dump = '1' then
-        report "cr 00000000" & to_hstring(crs);
-        assert false
-          report "end of test" severity failure;
-      end if;
-    end process;
-  end generate;
-end behaviour;

data/tests/parser_tests/test_microwatt_cr_hazard_pp.vhd

@@ -1,51 +0,0 @@
--- generated by Vertigo VHDL tool
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
- 
-entity cr_hazard is
-  generic(
-    pipeline_depth : natural2 := 2);
-  port(
-    clk : in std_ulogic;
-    stall_in : in std_ulogic;
-    cr_read_in : in std_ulogic;
-    cr_write_in : in std_ulogic;
-    stall_out : out std_ulogic);
-end entity cr_hazard;
- 
-architecture behaviour of cr_hazard is
-   
-  type pipeline_entry_type is record
-    valid : std_ulogic;
-  end record;
-  constant pipeline_entry_init : pipeline_entry_type := (valid => '0');
-   
-  type pipeline_t is array(range 0 to pipeline_depth - 1) of pipeline_entry_type;
-  constant pipeline_t_init : pipeline_t := (others => pipeline_entry_init);
-  signal r : pipeline_t;
-  signal rin : pipeline_t := pipeline_t_init;
-begin
- 
-   
-  cr_hazard0 : process(clk)
-  begin
-    if rising_edge(clk) then
-      if stall_in = '0' then
-        r <= rin;
-      end if;
-    end if;
-  end process;
-   
-  cr_hazard1 : process(all)
-    variable v : pipeline_t;
-  begin
-    v := r;
-    stall_out <= '0';
-    v(0).valid := cr_write_in;
-    if cr_read_in = '0' then
-      stall_out <= '0';
-    end if;
-    rin <= v;
-  end process;
-end behaviour;

data/tests/parser_tests/test_microwatt_crhelpers_pp.vhd

@@ -1,48 +0,0 @@
--- generated by Vertigo VHDL tool
-library ieee;
-use ieee.std_logic_1164.all;
-library work;
-use work.common.all;
- 
-package crhelpers is
-   
-  subtype crnum_t is integer range 0 to 7;
-   
-  subtype crmask_t is std_ulogic_vector(7 downto 0);
-  function fxm_to_num(fxm : crmask_t) return crnum_t
-  function num_to_fxm(num : crnum_t) return crmask_t
- 
-end crhelpers;
- 
-package body crhelpers is
-   
-  function fxm_to_num(fxm : crmask_t) return crnum_t is
-  begin
-    ;
-    return 7;
-  end function fxm_to_num;
-   
-  function num_to_fxm(num : crnum_t) return crmask_t is
-  begin
-    case num is
-      when 0 =>
-        return "10000000";
-      when 1 =>
-        return "01000000";
-      when 2 =>
-        return "00100000";
-      when 3 =>
-        return "00010000";
-      when 4 =>
-        return "00001000";
-      when 5 =>
-        return "00000100";
-      when 6 =>
-        return "00000010";
-      when 7 =>
-        return "00000001";
-      when others =>
-        return "00000000";
-    end case;
-  end function num_to_fxm;
-end crhelpers;

data/tests/parser_tests/test_microwatt_dcache_pp.vhd

@@ -1,481 +0,0 @@
--- generated by Vertigo VHDL tool
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-library work;
-use work.utils.all;
-use work.common.all;
-use work.helpers.all;
-use work.wishbone_types.all;
- 
-entity dcache is
-  generic(
-    line_size : positive64 := 64;
-    num_lines : positive32 := 32;
-    num_ways : positive4 := 4);
-  port(
-    clk : in std_ulogic;
-    rst : in std_ulogic;
-    d_in : in loadstore1todcachetype;
-    d_out : out dcachetoloadstore1type;
-    stall_out : out std_ulogic;
-    wishbone_out : out wishbone_master_out;
-    wishbone_in : in wishbone_slave_out);
-end entity dcache;
- 
-architecture rtl of dcache is
-  constant row_size : natural := wishbone_data_bits / 8;
-  constant row_per_line : natural := line_size / row_size;
-  constant bram_rows : natural := num_lines * row_per_line;
-  constant row_bits : natural := log2(bram_rows);
-  constant row_linebits : natural := log2(row_per_line);
-  constant line_off_bits : natural := log2(line_size);
-  constant row_off_bits : natural := log2(row_size);
-  constant index_bits : natural := log2(num_lines);
-  constant tag_bits : natural := 64 - line_off_bits - index_bits;
-  constant way_bits : natural := log2(num_ways);
-   
-  subtype row_t is integer range 0 to bram_rows - 1;
-   
-  subtype index_t is integer range 0 to num_lines - 1;
-   
-  subtype way_t is integer range 0 to num_ways - 1;
-   
-  subtype cache_row_t is std_ulogic_vector(wishbone_data_bits - 1 downto 0);
-   
-  subtype cache_tag_t is std_logic_vector(tag_bits - 1 downto 0);
-  constant tag_ram_width : natural := tag_bits * num_ways;
-   
-  subtype cache_tags_set_t is std_logic_vector(tag_ram_width - 1 downto 0);
-   
-  type cache_tags_array_t is array(range index_t) of cache_tags_set_t;
-   
-  subtype cache_way_valids_t is std_ulogic_vector(num_ways - 1 downto 0);
-   
-  type cache_valids_t is array(range index_t) of cache_way_valids_t;
-  signal cache_tags : cache_tags_array_t;
-  signal cache_valids : cache_valids_t;
-  attribute ram_style : string;
-  attribute ram_style of cache_tags : signal is "distributed";
-  signal r0 : loadstore1todcachetype;
-   
-  type op_t is (op_none,op_load_hit,op_load_miss,op_load_nc,op_bad,op_store_hit,op_store_miss);
-   
-  type state_t is (idle,reload_wait_ack,finish_ld_miss,store_wait_ack,nc_load_wait_ack);
-   
-  type reg_stage_1_t is record
-    req : loadstore1todcachetype;
-    hit_way : way_t;
-    hit_load_valid : std_ulogic;
-    slow_data : std_ulogic_vector(63 downto 0);
-    slow_valid : std_ulogic;
-    stcx_fail : std_ulogic;
-    state : state_t;
-    wb : wishbone_master_out;
-    store_way : way_t;
-    store_row : row_t;
-    store_index : index_t;
-  end record;
-  signal r1 : reg_stage_1_t;
-   
-  type reservation_t is record
-    valid : std_ulogic;
-    addr : std_ulogic_vector(63 downto line_off_bits);
-  end record;
-  signal reservation : reservation_t;
-  signal req_index : index_t;
-  signal req_row : row_t;
-  signal req_hit_way : way_t;
-  signal req_tag : cache_tag_t;
-  signal req_op : op_t;
-  signal req_data : std_ulogic_vector(63 downto 0);
-  signal req_laddr : std_ulogic_vector(63 downto 0);
-  signal early_req_row : row_t;
-  signal cancel_store : std_ulogic;
-  signal set_rsrv : std_ulogic;
-  signal clear_rsrv : std_ulogic;
-   
-  type cache_ram_out_t is array(range way_t) of cache_row_t;
-  signal cache_out : cache_ram_out_t;
-   
-  type plru_out_t is array(range index_t) of std_ulogic_vector(way_bits - 1 downto 0);
-  signal plru_victim : plru_out_t;
-  signal replace_way : way_t;
-  signal bus_sel : std_ulogic_vector(7 downto 0);
-   
-  function get_index(addr : std_ulogic_vector(63 downto 0)) return index_t is
-  begin
-    return to_integer(unsigned(addr(63 - tag_bits downto line_off_bits)));
-  end function get_index;
-   
-  function get_row(addr : std_ulogic_vector(63 downto 0)) return row_t is
-  begin
-    return to_integer(unsigned(addr(63 - tag_bits downto row_off_bits)));
-  end function get_row;
-   
-  function is_last_row_addr(addr : wishbone_addr_type) return boolean is
-    constant ones : std_ulogic_vector(row_linebits - 1 downto 0) := (others => '1');
-  begin
-    return addr(line_off_bits - 1 downto row_off_bits) = ones;
-  end function is_last_row_addr;
-   
-  function is_last_row(row : row_t) return boolean is
-    variable row_v : std_ulogic_vector(row_bits - 1 downto 0);
-    constant ones : std_ulogic_vector(row_linebits - 1 downto 0) := (others => '1');
-  begin
-    row_v := std_ulogic_vector(to_unsigned(row,row_bits));
-    return row_v(row_linebits - 1 downto 0) = ones;
-  end function is_last_row;
-   
-  function next_row_addr(addr : wishbone_addr_type) return std_ulogic_vector is
-    variable row_idx : std_ulogic_vector(row_linebits - 1 downto 0);
-    variable result : wishbone_addr_type;
-  begin
-    row_idx := addr(line_off_bits - 1 downto row_off_bits);
-    row_idx := std_ulogic_vector(unsigned(row_idx) + 1);
-    result := addr;
-    result(line_off_bits - 1 downto row_off_bits) := row_idx;
-    return result;
-  end function next_row_addr;
-   
-  function next_row(row : row_t) return row_t is
-    variable row_v : std_ulogic_vector(row_bits - 1 downto 0);
-    variable row_idx : std_ulogic_vector(row_linebits - 1 downto 0);
-    variable result : std_ulogic_vector(row_bits - 1 downto 0);
-  begin
-    row_v := std_ulogic_vector(to_unsigned(row,row_bits));
-    row_idx := row_v(row_linebits - 1 downto 0);
-    row_v(row_linebits - 1 downto 0) := std_ulogic_vector(unsigned(row_idx) + 1);
-    return to_integer(unsigned(row_v));
-  end function next_row;
-   
-  function get_tag(addr : std_ulogic_vector(63 downto 0)) return cache_tag_t is
-  begin
-    return addr(63 downto 64 - tag_bits);
-  end function get_tag;
-   
-  function read_tag(way : way_t;tagset : cache_tags_set_t) return cache_tag_t is
-  begin
-    return tagset((way + 1) * tag_bits - 1 downto way * tag_bits);
-  end function read_tag;
-   
-  procedure write_tag(
-    way : in way_t;
-    tagset : inout cache_tags_set_t;
-    tag : cache_tag_t) is
-  begin
-    tagset((way + 1) * tag_bits - 1 downto way * tag_bits) := tag;
-  end write_tag;
-begin
- 
-  assert line_size mod row_size = 0
-    report "line_size not multiple of row_size" severity failure;
-  assert ispow2(line_size)
-    report "line_size not power of 2" severity failure;
-  assert ispow2(num_lines)
-    report "num_lines not power of 2" severity failure;
-  assert ispow2(row_per_line)
-    report "row_per_line not power of 2" severity failure;
-  assert (row_bits = index_bits + row_linebits)
-    report "geometry bits don't add up" severity failure;
-  assert (line_off_bits = row_off_bits + row_linebits)
-    report "geometry bits don't add up" severity failure;
-  assert (64 = tag_bits + index_bits + line_off_bits)
-    report "geometry bits don't add up" severity failure;
-  assert (64 = tag_bits + row_bits + row_off_bits)
-    report "geometry bits don't add up" severity failure;
-  assert (64 = wishbone_data_bits)
-    report "can't yet handle a wishbone width that isn't 64-bits" severity failure;
-  if num_ways > 1 generate
-    for i in 0 to num_lines - 1 generate
-      plru : entity work.plru
-        port map(
-          clk => clk,
-          rst => rst,
-          acc => plru_acc,
-          acc_en => plru_acc_en,
-          lru => plru_out);
-       
-       
-      process(req_index,req_op,req_hit_way,plru_out)
-      begin
-        if (req_op = op_load_hit or req_op = op_store_hit) and req_index = i then
-          plru_acc_en <= '1';
-        else
-          plru_acc_en <= '0';
-        end if;
-        plru_acc <= std_ulogic_vector(to_unsigned(req_hit_way,way_bits));
-        plru_victim(i) <= plru_out;
-      end process;
-    end generate;
-  end generate;
-   
-  stage_0 : process(clk)
-  begin
-    if rising_edge(clk) then
-      if rst = '1' then
-        r0.valid <= '0';
-      elsif stall_out = '0' then
-        r0 <= d_in;
-      end if;
-    end if;
-  end process;
-   
-  dcache_request : process(all)
-    variable is_hit : std_ulogic;
-    variable hit_way : way_t;
-    variable op : op_t;
-    variable tmp : std_ulogic_vector(63 downto 0);
-    variable data : std_ulogic_vector(63 downto 0);
-    variable opsel : std_ulogic_vector(3 downto 0);
-    variable go : std_ulogic;
-  begin
-    req_index <= get_index(r0.addr);
-    req_row <= get_row(r0.addr);
-    req_tag <= get_tag(r0.addr);
-    go := r0.valid and stall_out;
-    req_laddr <= r0.addr(63 downto line_off_bits) & (line_off_bits - 1 downto 0 => '0');
-    hit_way := 0;
-    is_hit := '0';
-    req_hit_way <= hit_way;
-    replace_way <= to_integer(unsigned(plru_victim(req_index)));
-    opsel := go & r0.load & r0.nc & is_hit;
-    case opsel is
-      when "1101" =>
-        op := op_load_hit;
-      when "1100" =>
-        op := op_load_miss;
-      when "1110" =>
-        op := op_load_nc;
-      when "1001" =>
-        op := op_store_hit;
-      when "1000" =>
-        op := op_store_miss;
-      when "1010" =>
-        op := op_store_miss;
-      when "1011" =>
-        op := op_bad;
-      when "1111" =>
-        op := op_bad;
-      when others =>
-        op := op_none;
-    end case;
-    req_op <= op;
-    if stall_out = '0' then
-      early_req_row <= get_row(d_in.addr);
-    else
-      early_req_row <= req_row;
-    end if;
-  end process;
-  wishbone_out <= r1.wb;
-  stall_out <= '1' when r1.state /= idle else  '0';
-   
-  reservation_comb : process(all)
-  begin
-    cancel_store <= '0';
-    set_rsrv <= '0';
-    clear_rsrv <= '0';
-    if stall_out = '0' and r0.valid = '1' and r0.reserve = '1' then
-      if r0.load = '1' then
-        set_rsrv <= '1';
-      else
-        clear_rsrv <= '1';
-        if reservation.valid = '0' or r0.addr(63 downto line_off_bits) /= reservation.addr then
-          cancel_store <= '1';
-        end if;
-      end if;
-    end if;
-  end process;
-   
-  reservation_reg : process(clk)
-  begin
-    if rising_edge(clk) then
-      if rst = '1' or clear_rsrv = '1' then
-        reservation.valid <= '0';
-      elsif set_rsrv = '1' then
-        reservation.valid <= '1';
-        reservation.addr <= r0.addr(63 downto line_off_bits);
-      end if;
-    end if;
-  end process;
-   
-  writeback_control : process(all)
-  begin
-    d_out.valid <= '0';
-    d_out.data <= cache_out(r1.hit_way);
-    d_out.store_done <= '0';
-    assert (r1.slow_valid and r1.stcx_fail) /= '1'
-      report "unexpected slow_valid collision with stcx_fail" severity failure;
-    assert ((r1.slow_valid or r1.stcx_fail) and r1.hit_load_valid) /= '1'
-      report "unexpected hit_load_delayed collision with slow_valid" severity failure;
-    if r1.hit_load_valid = '1' then
-      report "completing load hit";
-      d_out.valid <= '1';
-    end if;
-    if r1.slow_valid = '1' then
-      if r1.req.load then
-        d_out.data <= r1.slow_data;
-      end if;
-      d_out.store_done <= '1';
-      report "completing store or load miss";
-      d_out.valid <= '1';
-    end if;
-    if r1.stcx_fail = '1' then
-      d_out.store_done <= '0';
-      d_out.valid <= '1';
-    end if;
-  end process;
-  for i in 0 to num_ways - 1 generate
-    way : entity work.cache_ram
-      port map(
-        clk => clk,
-        rd_en => do_read,
-        rd_addr => rd_addr,
-        rd_data => dout,
-        wr_en => do_write,
-        wr_sel => wr_sel,
-        wr_addr => wr_addr,
-        wr_data => wr_data);
-     
-     
-    process(all)
-      variable tmp_adr : std_ulogic_vector(63 downto 0);
-      variable reloading : boolean;
-    begin
-      do_read <= '1';
-      rd_addr <= std_ulogic_vector(to_unsigned(early_req_row,row_bits));
-      cache_out(i) <= dout;
-      if r1.state = idle then
-        wr_addr <= std_ulogic_vector(to_unsigned(req_row,row_bits));
-        wr_data <= r0.data;
-        wr_sel <= r0.byte_sel;
-      else
-        wr_data <= wishbone_in.dat;
-        wr_sel <= (others => '1');
-        wr_addr <= std_ulogic_vector(to_unsigned(r1.store_row,row_bits));
-      end if;
-      do_write <= '0';
-      reloading := r1.state = reload_wait_ack;
-      if reloading and wishbone_in.ack = '1' and r1.store_way = i then
-        do_write <= '1';
-      end if;
-      if req_op = op_store_hit and req_hit_way = i and cancel_store = '0' then
-        assert reloading
-          report "store hit while in state:" & state_t'image(r1.state) severity failure;
-        do_write <= '1';
-      end if;
-    end process;
-  end generate;
-   
-  dcache_fast_hit : process(clk)
-  begin
-    if rising_edge(clk) then
-      if req_op /= op_none and stall_out = '0' then
-        r1.req <= r0;
-        report "op:" & op_t'image(req_op) & " addr:" & to_hstring(r0.addr) & " nc:" & std_ulogic'image(r0.nc) & " idx:" & integer'image(req_index) & " tag:" & to_hstring(req_tag) & " way: " & integer'image(req_hit_way);
-      end if;
-      if req_op = op_load_hit then
-        r1.hit_way <= req_hit_way;
-        r1.hit_load_valid <= '1';
-      else
-        r1.hit_load_valid <= '0';
-      end if;
-    end if;
-  end process;
-   
-  dcache_slow : process(clk)
-    variable tagset : cache_tags_set_t;
-    variable stbs_done : boolean;
-  begin
-    if rising_edge(clk) then
-      if rst = '1' then
-        ;
-        r1.state <= idle;
-        r1.slow_valid <= '0';
-        r1.wb.cyc <= '0';
-        r1.wb.stb <= '0';
-        r1.wb.adr <= (others => '0');
-      else
-        r1.slow_valid <= '0';
-        r1.stcx_fail <= '0';
-        case r1.state is
-          when idle =>
-            case req_op is
-              when op_load_hit =>
-              when op_load_miss =>
-                report "cache miss addr:" & to_hstring(r0.addr) & " idx:" & integer'image(req_index) & " way:" & integer'image(replace_way) & " tag:" & to_hstring(req_tag);
-                cache_valids(req_index)(replace_way) <= '0';
-                r1.store_index <= req_index;
-                r1.store_way <= replace_way;
-                r1.store_row <= get_row(req_laddr);
-                r1.wb.adr <= req_laddr(r1.wb.adr'left downto 0);
-                r1.wb.sel <= (others => '1');
-                r1.wb.we <= '0';
-                r1.wb.cyc <= '1';
-                r1.wb.stb <= '1';
-                r1.state <= reload_wait_ack;
-              when op_load_nc =>
-                r1.wb.sel <= r0.byte_sel;
-                r1.wb.adr <= r0.addr(r1.wb.adr'left downto 3) & "000";
-                r1.wb.cyc <= '1';
-                r1.wb.stb <= '1';
-                r1.wb.we <= '0';
-                r1.state <= nc_load_wait_ack;
-              when op_store_hit | op_store_miss =>
-                r1.wb.sel <= r0.byte_sel;
-                r1.wb.adr <= r0.addr(r1.wb.adr'left downto 3) & "000";
-                r1.wb.dat <= r0.data;
-                if cancel_store = '0' then
-                  r1.wb.cyc <= '1';
-                  r1.wb.stb <= '1';
-                  r1.wb.we <= '1';
-                  r1.state <= store_wait_ack;
-                else
-                  r1.stcx_fail <= '1';
-                  r1.state <= idle;
-                end if;
-              when op_none =>
-              when op_bad =>
-            end case;
-          when reload_wait_ack =>
-            stbs_done := r1.wb.stb = '0';
-            if wishbone_in.stall = '0' and stbs_done then
-              if is_last_row_addr(r1.wb.adr) then
-                r1.wb.stb <= '0';
-                stbs_done := true;
-              end if;
-              r1.wb.adr <= next_row_addr(r1.wb.adr);
-            end if;
-            if wishbone_in.ack = '1' then
-              if r1.store_row = get_row(r1.req.addr) then
-                r1.slow_data <= wishbone_in.dat;
-              end if;
-              if stbs_done and is_last_row(r1.store_row) then
-                r1.wb.cyc <= '0';
-                cache_valids(r1.store_index)(r1.store_way) <= '1';
-                r1.state <= finish_ld_miss;
-              end if;
-              r1.store_row <= next_row(r1.store_row);
-            end if;
-          when finish_ld_miss =>
-            r1.slow_valid <= '1';
-            r1.state <= idle;
-            report "completing miss !";
-          when store_wait_ack | nc_load_wait_ack =>
-            if wishbone_in.stall = '0' then
-              r1.wb.stb <= '0';
-            end if;
-            if wishbone_in.ack = '1' then
-              if r1.state = nc_load_wait_ack then
-                r1.slow_data <= wishbone_in.dat;
-              end if;
-              r1.state <= idle;
-              r1.slow_valid <= '1';
-              r1.wb.cyc <= '0';
-              r1.wb.stb <= '0';
-            end if;
-        end case;
-      end if;
-    end if;
-  end process;
-end rtl;