vertigo_vhdl 0.8.9 → 0.8.10
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- checksums.yaml +4 -4
- data/lib/vertigo/parser.rb +28 -5
- data/lib/vertigo/tb_generator.rb +1 -1
- data/lib/vertigo/version.rb +1 -1
- data/tests/parser_tests/test_adder_rca_vhdl93.vhd +37 -0
- metadata +4 -85
- data/tests/ghdl_tests/test_fsm.vhd +0 -162
- data/tests/parser_tests/else.vhd +0 -64
- data/tests/parser_tests/pingpong.vhd +0 -34
- data/tests/parser_tests/test_accelerator_pp.vhd +0 -144
- data/tests/parser_tests/test_aggregate_pp.vhd +0 -15
- data/tests/parser_tests/test_archi_1_pp.vhd +0 -41
- data/tests/parser_tests/test_array_array_00_pp.vhd +0 -25
- data/tests/parser_tests/test_array_urange_pp.vhd +0 -25
- data/tests/parser_tests/test_chu-1_pp.vhd +0 -104
- data/tests/parser_tests/test_concat_pp.vhd +0 -14
- data/tests/parser_tests/test_counter_pp.vhd +0 -35
- data/tests/parser_tests/test_de2_pp.vhd +0 -274
- data/tests/parser_tests/test_encode_pp.vhd +0 -2549
- data/tests/parser_tests/test_fsm_pp.vhd +0 -125
- data/tests/parser_tests/test_fsm_synth_pp.vhd +0 -197
- data/tests/parser_tests/test_function-01_pp.vhd +0 -18
- data/tests/parser_tests/test_lfsr_pp.vhd +0 -44
- data/tests/parser_tests/test_microwatt_cache_ram_pp.vhd +0 -68
- data/tests/parser_tests/test_microwatt_common_pp.vhd +0 -336
- data/tests/parser_tests/test_microwatt_control_pp.vhd +0 -187
- data/tests/parser_tests/test_microwatt_core_debug_pp.vhd +0 -104
- data/tests/parser_tests/test_microwatt_core_pp.vhd +0 -231
- data/tests/parser_tests/test_microwatt_core_tb_pp.vhd +0 -43
- data/tests/parser_tests/test_microwatt_countzero_pp.vhd +0 -120
- data/tests/parser_tests/test_microwatt_countzero_tb_pp.vhd +0 -70
- data/tests/parser_tests/test_microwatt_cr_file_pp.vhd +0 -74
- data/tests/parser_tests/test_microwatt_cr_hazard_pp.vhd +0 -51
- data/tests/parser_tests/test_microwatt_crhelpers_pp.vhd +0 -48
- data/tests/parser_tests/test_microwatt_dcache_pp.vhd +0 -481
- data/tests/parser_tests/test_microwatt_dcache_tb_pp.vhd +0 -98
- data/tests/parser_tests/test_microwatt_decode1_pp.vhd +0 -138
- data/tests/parser_tests/test_microwatt_decode2_pp.vhd +0 -300
- data/tests/parser_tests/test_microwatt_decode_types_pp.vhd +0 -67
- data/tests/parser_tests/test_microwatt_divider_pp.vhd +0 -132
- data/tests/parser_tests/test_microwatt_divider_tb_pp.vhd +0 -95
- data/tests/parser_tests/test_microwatt_dmi_dtm_dummy_pp.vhd +0 -29
- data/tests/parser_tests/test_microwatt_dmi_dtm_tb_pp.vhd +0 -197
- data/tests/parser_tests/test_microwatt_dmi_dtm_xilinx_pp.vhd +0 -139
- data/tests/parser_tests/test_microwatt_execute1_pp.vhd +0 -689
- data/tests/parser_tests/test_microwatt_fetch1_pp.vhd +0 -88
- data/tests/parser_tests/test_microwatt_fetch2_pp.vhd +0 -79
- data/tests/parser_tests/test_microwatt_glibc_random_helpers_pp.vhd +0 -25
- data/tests/parser_tests/test_microwatt_glibc_random_pp.vhd +0 -41
- data/tests/parser_tests/test_microwatt_gpr_hazard_pp.vhd +0 -68
- data/tests/parser_tests/test_microwatt_helpers_pp.vhd +0 -153
- data/tests/parser_tests/test_microwatt_icache_pp.vhd +0 -337
- data/tests/parser_tests/test_microwatt_icache_tb_pp.vhd +0 -104
- data/tests/parser_tests/test_microwatt_insn_helpers_pp.vhd +0 -208
- data/tests/parser_tests/test_microwatt_loadstore1_pp.vhd +0 -222
- data/tests/parser_tests/test_microwatt_logical_pp.vhd +0 -87
- data/tests/parser_tests/test_microwatt_multiply_pp.vhd +0 -84
- data/tests/parser_tests/test_microwatt_multiply_tb_pp.vhd +0 -75
- data/tests/parser_tests/test_microwatt_plru_pp.vhd +0 -46
- data/tests/parser_tests/test_microwatt_plru_tb_pp.vhd +0 -93
- data/tests/parser_tests/test_microwatt_ppc_fx_insns_pp.vhd +0 -665
- data/tests/parser_tests/test_microwatt_register_file_pp.vhd +0 -86
- data/tests/parser_tests/test_microwatt_rotator_pp.vhd +0 -149
- data/tests/parser_tests/test_microwatt_rotator_tb_pp.vhd +0 -134
- data/tests/parser_tests/test_microwatt_sim_bram_helpers_pp.vhd +0 -52
- data/tests/parser_tests/test_microwatt_sim_bram_pp.vhd +0 -53
- data/tests/parser_tests/test_microwatt_sim_console_pp.vhd +0 -43
- data/tests/parser_tests/test_microwatt_sim_jtag_pp.vhd +0 -64
- data/tests/parser_tests/test_microwatt_sim_jtag_socket_pp.vhd +0 -36
- data/tests/parser_tests/test_microwatt_sim_uart_pp.vhd +0 -90
- data/tests/parser_tests/test_microwatt_soc_pp.vhd +0 -195
- data/tests/parser_tests/test_microwatt_utils_pp.vhd +0 -39
- data/tests/parser_tests/test_microwatt_wishbone_arbiter_pp.vhd +0 -54
- data/tests/parser_tests/test_microwatt_wishbone_bram_tb_pp.vhd +0 -157
- data/tests/parser_tests/test_microwatt_wishbone_bram_wrapper_pp.vhd +0 -62
- data/tests/parser_tests/test_microwatt_wishbone_debug_master_pp.vhd +0 -124
- data/tests/parser_tests/test_microwatt_wishbone_types_pp.vhd +0 -38
- data/tests/parser_tests/test_microwatt_writeback_pp.vhd +0 -87
- data/tests/parser_tests/test_package-1_pp.vhd +0 -53
- data/tests/parser_tests/test_precedence_pp.vhd +0 -16
- data/tests/parser_tests/test_selected_sig_pp.vhd +0 -10
- data/tests/parser_tests/test_slice_pp.vhd +0 -16
- data/tests/parser_tests/test_tb-00_pp.vhd +0 -71
- data/tests/parser_tests/test_type_decl_02_pp.vhd +0 -11
- data/tests/parser_tests/test_use_pp.vhd +0 -10
- data/tests/parser_tests/test_while_1_pp.vhd +0 -26
- data/tests/parser_tests/test_with-00_pp.vhd +0 -12
- data/tests/tb_gen_tests/test_accelerator.vhd +0 -160
@@ -1,53 +0,0 @@
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-- generated by Vertigo VHDL tool
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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package alu_package is
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constant interval : time := 8 ns;
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signal sig_a : std_logic_vector(1 downto 0);
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signal sig_b : std_logic_vector(1 downto 0);
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signal sig_sel : std_logic_vector(1 downto 0);
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signal sig_res : std_logic_vector(1 downto 0);
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procedure load_data(
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a : out std_logic_vector(1 downto 0);
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b : out std_logic_vector(1 downto 0);
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sel : out std_logic_vector(1 downto 0));
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procedure check_data(
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sel : out std_logic_vector(1 downto 0));
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end alu_package;
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package body alu_package is
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procedure load_data(
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a : out std_logic_vector(1 downto 0);
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b : out std_logic_vector(1 downto 0);
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sel : out std_logic_vector(1 downto 0)) is
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begin
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a <= sig_a;
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b <= sig_b;
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sel <= sig_sel;
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end load_data;
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procedure check_data(
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sel : out std_logic_vector(1 downto 0)) is
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begin
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sel <= sig_sel;
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if (sig_sel = "00") then
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assert (sig_res = (sig_a + sig_b))
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report "error detected in addition!" severity warning;
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elsif (sig_sel = "01") then
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assert (sig_res = (sig_a - sig_b))
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report "error detected in subtraction!" severity warning;
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elsif (sig_sel = "10") then
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assert (sig_res = (sig_a and sig_b))
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report "and operation error!" severity warning;
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elsif (sig_sel = "11") then
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assert (sig_res = (sig_a or sig_b))
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report "or operation error!" severity warning;
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end if;
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end check_data;
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end alu_package;
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-- generated by Vertigo VHDL tool
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity test is
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end entity test;
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architecture arch of test is
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constant cst : std_logic_vector(15 downto 0) := x"1234";
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signal s1 : std_logic_vector(31 downto 0);
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signal s2 : std_logic_vector(31 downto 0);
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begin
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s2 <= s1(15 downto 0) & cst;
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end arch;
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-- generated by Vertigo VHDL tool
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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entity decoder_tb is
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end entity decoder_tb;
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architecture tb of decoder_tb is
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signal t_i : std_logic_vector(1 downto 0) := "00";
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signal t_o : std_logic_vector(3 downto 0);
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component decoder is
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port(
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i : in std_logic_vector(1 downto 0);
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o : out std_logic_vector(3 downto 0));
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end component;
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begin
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u_decoder : component decoder
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port map(
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t_i,
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t_o);
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process
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variable err_cnt : integer := 0;
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begin
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wait 10 ns;
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t_i <= "00";
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wait 1 ns;
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assert (t_o = "0001")
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report "error case 0" severity error;
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if (t_o /= "0001") then
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err_cnt := err_cnt + 1;
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end if;
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wait 10 ns;
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t_i <= "01";
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wait 1 ns;
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assert (t_o = "0010")
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report "error case 1" severity error;
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if (t_o /= "0010") then
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err_cnt := err_cnt + 1;
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end if;
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wait 10 ns;
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t_i <= "10";
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wait 1 ns;
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assert (t_o = "0100")
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report "error case 2" severity error;
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if (t_o /= "0100") then
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err_cnt := err_cnt + 1;
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end if;
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wait 10 ns;
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t_i <= "11";
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wait 1 ns;
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assert (t_o = "1000")
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report "error case 3" severity error;
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if (t_o /= "1000") then
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err_cnt := err_cnt + 1;
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end if;
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wait 10 ns;
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t_i <= "uu";
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if (err_cnt = 0) then
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assert false
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report "testbench of adder completed successfully!" severity note;
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else
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assert true
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report "something wrong, try again" severity error;
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end if;
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wait ;
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end process;
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end tb;
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-- generated by Vertigo VHDL tool
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architecture test_while of while_tester is
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begin
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clk_1 : process(clock)
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begin
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;
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end process;
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process
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begin
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;
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end process;
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shift_3 : process(input_x)
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variable i : positive := 1;
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begin
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;
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end process;
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shift_4 : process(input_x)
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begin
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;
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end process;
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end test_while;
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-- generated by Vertigo VHDL tool
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architecture flow of ttimer is
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begin
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with s_sum select dig_sig1 <=
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"10000001" when 0,
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"11001111" when 1,
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"10010010" when 2,
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"10000110" when 3,
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"10000100" when 59,;
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dig_sig0 <= "10000001" when s_sum >= 0 and s_sum <= 9 else "11001111" when s_sum >= 10 and s_sum <= 19 else "10010010" when s_sum >= 20 and s_sum <= 29 else "10000110" when s_sum >= 30 and s_sum <= 39 else "11001100" when s_sum >= 40 and s_sum <= 49 else "10100100";
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end flow;
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library ieee,std;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.accelerator_pkg.all;
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entity accelerator is
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port(
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clock : in std_logic;
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reset_n : in std_logic;
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bus_addr : in std_logic_vector(31 downto 0);
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bus_data_p2a : in std_logic_vector(31 downto 0);
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bus_data_a2p : out std_logic_vector(31 downto 0);
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bus_rd : in std_logic;
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bus_wr : in std_logic
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);
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end accelerator;
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architecture rtl of accelerator is
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type regs_t is record
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a, b, res : std_logic_vector(31 downto 0);
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ctrl : std_logic;
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status : std_logic_vector(1 downto 0); --busy,done
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end record;
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constant INIT_REGS : regs_t := (
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(others => '0'),
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(others => '0'),
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(others => '0'),
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'0',
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"00"
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);
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signal ifregs : regs_t;
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type state_t is (idle, running);
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signal state, state_c : state_t;
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type vars_t is record
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go : std_logic;
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a, b : unsigned(31 downto 0);
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done : std_logic;
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end record;
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-- constant VARS_INIT : vars_t := (
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-- '0',
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-- to_unsigned(0, 32),
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-- to_unsigned(0, 32),
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-- '0');
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signal vars, vars_c : vars_t;
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begin
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--========================================
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-- Bus interface
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--========================================
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bus_wr_proc : process(clk, reset_n)
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begin
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if reset_n = '0' then
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ifregs <= INIT_REGS;
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elsif rising_edge(clk) then
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ifregs.ctrl <= '0'; --autoreset
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if bus_wr = '1' then
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case bus_addr is
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when ADDR_A =>
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ifregs.a <= bus_data_p2a;
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when ADDR_B =>
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ifregs.b <= bus_data_p2a;
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when ADDR_CTRL =>
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ifregs.ctrl <= bus_data_p2a(0); --write/clear a go
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when ADDR_STATUS =>
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ifregs.status <= bus_data_p2a(1 downto 0); --clear rdy
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when others => null;
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end case;
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elsif vars.done = '1' then
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ifregs.res <= std_logic_vector(vars.a); --BUG : vars.a ne passait pas
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--=> FIX lexer : selected_name
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--ifregs.status(0) <= vars.done; --BUG : (0) ne passe pas
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ifregs.status <= vars.done; --BUG : (0) ne passe pas
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end if;
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end if;
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end process;
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bus_rd_proc : process(reset_n, clk)
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begin
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if reset_n = '0' then
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bus_data_a2p <= (others => '0');
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elsif rising_edge(clk) then
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if bus_rd = '1' then
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case bus_addr is
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when ADDR_A =>
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|
-
bus_data_a2p <= ifregs.a;
|
93
|
-
when ADDR_B =>
|
94
|
-
bus_data_a2p <= ifregs.b;
|
95
|
-
when ADDR_CTRL =>
|
96
|
-
null;
|
97
|
-
--bus_data_a2p <= X"0000000" & "000" & ifregs.ctrl; --write/clear a go
|
98
|
-
when ADDR_STATUS =>
|
99
|
-
null;
|
100
|
-
bus_data_a2p <= X"0000000" & "00" & ifregs.status;
|
101
|
-
when ADDR_RES =>
|
102
|
-
bus_data_a2p <= ifregs.res;
|
103
|
-
when others => null;
|
104
|
-
end case;
|
105
|
-
end if;
|
106
|
-
end if;
|
107
|
-
end process;
|
108
|
-
|
109
|
-
--=============================================
|
110
|
-
-- BUG
|
111
|
-
--=============================================
|
112
|
-
|
113
|
-
reg : process(clk, reset_n)
|
114
|
-
begin
|
115
|
-
if reset_n = '0' then
|
116
|
-
state <= idle;
|
117
|
-
vars <= VARS_INIT;
|
118
|
-
elsif rising_edge(clk) then
|
119
|
-
state <= state_c;
|
120
|
-
vars <= vars_c;
|
121
|
-
if ifregs.ctrl = '1' then
|
122
|
-
vars.a <= unsigned(ifregs.a);
|
123
|
-
vars.b <= unsigned(ifregs.b);
|
124
|
-
vars.go <= '1';
|
125
|
-
end if;
|
126
|
-
end if;
|
127
|
-
end process;
|
128
|
-
|
129
|
-
comb : process (state, vars)
|
130
|
-
variable state_v : state_t;
|
131
|
-
variable vars_v : vars_t;
|
132
|
-
begin
|
133
|
-
state_v := state;
|
134
|
-
vars_v := vars;
|
135
|
-
case state_v is
|
136
|
-
when idle =>
|
137
|
-
if vars_v.go = '1' then
|
138
|
-
state_v := running;
|
139
|
-
vars_v.go := '0';
|
140
|
-
else
|
141
|
-
vars_v := VARS_INIT;
|
142
|
-
end if;
|
143
|
-
when running =>
|
144
|
-
if vars_v.a /= vars_v.b then
|
145
|
-
if vars_v.a > vars_v.b then
|
146
|
-
vars_v.a := vars_v.a-vars_v.b;
|
147
|
-
else
|
148
|
-
vars_v.b := vars_v.b-vars_v.a;
|
149
|
-
end if;
|
150
|
-
else
|
151
|
-
vars_v.done := '1';
|
152
|
-
state_v := idle;
|
153
|
-
end if;
|
154
|
-
when others => null;
|
155
|
-
end case;
|
156
|
-
state_c <= state_v;
|
157
|
-
vars_c <= vars_v;
|
158
|
-
end process;
|
159
|
-
|
160
|
-
end rtl;
|