vertigo_vhdl 0.8.9 → 0.8.10

data/tests/parser_tests/test_microwatt_dmi_dtm_xilinx_pp.vhd

@@ -1,139 +0,0 @@
--- generated by Vertigo VHDL tool
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.math_real.all;
-library work;
-use work.wishbone_types.all;
-library unisim;
-use unisim.vcomponents.all;
- 
-entity dmi_dtm is
-  generic(
-    abits : integer8 := 8;
-    dbits : integer32 := 32);
-  port(
-    sys_clk : in std_ulogic;
-    sys_reset : in std_ulogic;
-    dmi_addr : out std_ulogic_vector(abits - 1 downto 0);
-    dmi_din : in std_ulogic_vector(dbits - 1 downto 0);
-    dmi_dout : out std_ulogic_vector(dbits - 1 downto 0);
-    dmi_req : out std_ulogic;
-    dmi_wr : out std_ulogic;
-    dmi_ack : in std_ulogic);
-end entity dmi_dtm;
- 
-architecture behaviour of dmi_dtm is
-  signal jtag_reset : std_ulogic;
-  signal capture : std_ulogic;
-  signal update : std_ulogic;
-  signal drck : std_ulogic;
-  signal jtag_clk : std_ulogic;
-  signal sel : std_ulogic;
-  signal shift : std_ulogic;
-  signal tdi : std_ulogic;
-  signal tdo : std_ulogic;
-  signal tck : std_ulogic;
-  signal shiftr : std_ulogic_vector(abits + dbits + 1 downto 0);
-  signal request : std_ulogic_vector(abits + dbits + 1 downto 0);
-  signal jtag_req : std_ulogic;
-  signal dmi_ack_0 : std_ulogic;
-  signal dmi_ack_1 : std_ulogic;
-  signal jtag_req_0 : std_ulogic;
-  signal jtag_req_1 : std_ulogic;
-  signal jtag_bsy : std_ulogic;
-  signal op_valid : std_ulogic;
-  signal rsp_op : std_ulogic_vector(1 downto 0);
-  constant dmi_req_nop : std_ulogic_vector(1 downto 0) := "00";
-  constant dmi_req_rd : std_ulogic_vector(1 downto 0) := "01";
-  constant dmi_req_wr : std_ulogic_vector(1 downto 0) := "10";
-  constant dmi_rsp_ok : std_ulogic_vector(1 downto 0) := "00";
-  constant dmi_rsp_bsy : std_ulogic_vector(1 downto 0) := "11";
-begin
- 
-  bscan : component bscane2
-    generic map(
-      jtag_chain => 2);
-    port map(
-      capture => capture,
-      drck => drck,
-      reset => jtag_reset,
-      runtest => open,
-      sel => sel,
-      shift => shift,
-      tck => tck,
-      tdi => tdi,
-      tms => open,
-      update => update,
-      tdo => tdo);
-   
-  clkbuf : component bufg
-    port map(
-      i => tck,
-      o => jtag_clk);
-   
-   
-  dmi_req_sync : process(sys_clk)
-  begin
-    if rising_edge(sys_clk) then
-      if (sys_reset = '1') then
-        jtag_req_0 <= '0';
-        jtag_req_1 <= '0';
-      else
-        jtag_req_0 <= jtag_req;
-        jtag_req_1 <= jtag_req_0;
-      end if;
-    end if;
-  end process;
-  dmi_req <= jtag_req_1;
-   
-  dmi_ack_sync : process(jtag_clk,jtag_reset)
-  begin
-    if jtag_reset = '1' then
-      dmi_ack_0 <= '0';
-      dmi_ack_1 <= '0';
-    elsif rising_edge(jtag_clk) then
-      dmi_ack_0 <= dmi_ack;
-      dmi_ack_1 <= dmi_ack_0;
-    end if;
-  end process;
-  jtag_bsy <= jtag_req or dmi_ack_1;
-  with shiftr(1 downto 0) select op_valid <=
-    '1' when dmi_req_rd,
-    '1' when dmi_req_wr,
-    '0' when others,;
-  rsp_op <= dmi_rsp_bsy when jtag_bsy = '1' else  dmi_rsp_ok;
-  dmi_addr <= request(abits + dbits + 1 downto dbits + 2);
-  dmi_dout <= request(dbits + 1 downto 2);
-  dmi_wr <= '1' when request(1 downto 0) = dmi_req_wr else  '0';
-  tdo <= shiftr(0);
-   
-  shifter : process(jtag_clk,jtag_reset)
-  begin
-    if jtag_reset = '1' then
-      shiftr <= (others => '0');
-      jtag_req <= '0';
-    elsif rising_edge(jtag_clk) then
-      if sel = '1' then
-        if shift = '1' then
-          shiftr <= tdi & shiftr(abits + dbits + 1 downto 1);
-        end if;
-        if update = '1' and op_valid = '1' then
-          if jtag_bsy = '0' then
-            request <= shiftr;
-            jtag_req <= '1';
-          end if;
-          shiftr(1 downto 0) <= dmi_rsp_bsy;
-        end if;
-        if jtag_req = '1' and dmi_ack_1 = '1' then
-          jtag_req <= '0';
-          if request(1 downto 0) = dmi_req_rd then
-            request(dbits + 1 downto 2) <= dmi_din;
-          end if;
-        end if;
-        if capture = '1' then
-          shiftr <= request(abits + dbits + 1 downto 2) & rsp_op;
-        end if;
-      end if;
-    end if;
-  end process;
-end behaviour;

data/tests/parser_tests/test_microwatt_execute1_pp.vhd

@@ -1,689 +0,0 @@
--- generated by Vertigo VHDL tool
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-library work;
-use work.decode_types.all;
-use work.common.all;
-use work.helpers.all;
-use work.crhelpers.all;
-use work.insn_helpers.all;
-use work.ppc_fx_insns.all;
- 
-entity execute1 is
-  generic(
-    ex1_bypass : booleantrue := true);
-  port(
-    clk : in std_ulogic;
-    rst : in std_ulogic;
-    flush_out : out std_ulogic;
-    stall_out : out std_ulogic;
-    e_in : in decode2toexecute1type;
-    l_out : out execute1toloadstore1type;
-    f_out : out execute1tofetch1type;
-    e_out : out execute1towritebacktype;
-    icache_inval : out std_ulogic;
-    terminate_out : out std_ulogic);
-end entity execute1;
- 
-architecture behaviour of execute1 is
-   
-  type reg_type is record
-    e : execute1towritebacktype;
-    lr_update : std_ulogic;
-    next_lr : std_ulogic_vector(63 downto 0);
-    mul_in_progress : std_ulogic;
-    div_in_progress : std_ulogic;
-    cntz_in_progress : std_ulogic;
-    slow_op_dest : gpr_index_t;
-    slow_op_rc : std_ulogic;
-    slow_op_oe : std_ulogic;
-    slow_op_xerc : xer_common_t;
-  end record;
-  signal r : reg_type;
-  signal rin : reg_type;
-  signal a_in : std_ulogic_vector(63 downto 0);
-  signal b_in : std_ulogic_vector(63 downto 0);
-  signal c_in : std_ulogic_vector(63 downto 0);
-  signal ctrl : ctrl_t := (irq_state => write_srr0,others => (others => '0'));
-  signal ctrl_tmp : ctrl_t := (irq_state => write_srr0,others => (others => '0'));
-  signal right_shift : std_ulogic;
-  signal rot_clear_left : std_ulogic;
-  signal rot_clear_right : std_ulogic;
-  signal rotator_result : std_ulogic_vector(63 downto 0);
-  signal rotator_carry : std_ulogic;
-  signal logical_result : std_ulogic_vector(63 downto 0);
-  signal countzero_result : std_ulogic_vector(63 downto 0);
-  signal popcnt_result : std_ulogic_vector(63 downto 0);
-  signal parity_result : std_ulogic_vector(63 downto 0);
-  signal x_to_multiply : execute1tomultiplytype;
-  signal multiply_to_x : multiplytoexecute1type;
-  signal x_to_divider : execute1todividertype;
-  signal divider_to_x : dividertoexecute1type;
-   
-  procedure set_carry(
-    e : inout execute1towritebacktype;
-    carry32 : in std_ulogic;
-    carry : in std_ulogic) is
-  begin
-    e.xerc.ca32 := carry32;
-    e.xerc.ca := carry;
-    e.write_xerc_enable := '1';
-  end set_carry;
-   
-  procedure set_ov(
-    e : inout execute1towritebacktype;
-    ov : in std_ulogic;
-    ov32 : in std_ulogic) is
-  begin
-    e.xerc.ov32 := ov32;
-    e.xerc.ov := ov;
-    if ov = '1' then
-      e.xerc.so := '1';
-    end if;
-    e.write_xerc_enable := '1';
-  end set_ov;
-   
-  function calc_ov(msb_a : std_ulogic;msb_b : std_ulogic;ca : std_ulogic;msb_r : std_ulogic) return std_ulogic is
-  begin
-    return (ca xor msb_r) and (msb_a xor msb_b);
-  end function calc_ov;
-   
-  function decode_input_carry(ic : carry_in_t;xerc : xer_common_t) return std_ulogic is
-  begin
-    case ic is
-      when zero =>
-        return '0';
-      when ca =>
-        return xerc.ca;
-      when one =>
-        return '1';
-    end case;
-  end function decode_input_carry;
-   
-  function msr_copy(msr : std_ulogic_vector(63 downto 0)) return std_ulogic_vector is
-    variable msr_out : std_ulogic_vector(63 downto 0);
-  begin
-    msr_out := (others => '0');
-    msr_out(32 downto 0) := msr(32 downto 0);
-    msr_out(41 downto 37) := msr(41 downto 37);
-    msr_out(63 downto 48) := msr(63 downto 48);
-    return msr_out;
-  end function msr_copy;
-begin
- 
-  rotator_0 : entity work.rotator
-    port map(
-      rs => c_in,
-      ra => a_in,
-      shift => b_in(6 downto 0),
-      insn => e_in.insn,
-      is_32bit => e_in.is_32bit,
-      right_shift => right_shift,
-      arith => e_in.is_signed,
-      clear_left => rot_clear_left,
-      clear_right => rot_clear_right,
-      result => rotator_result,
-      carry_out => rotator_carry);
-   
-  logical_0 : entity work.logical
-    port map(
-      rs => c_in,
-      rb => b_in,
-      op => e_in.insn_type,
-      invert_in => e_in.invert_a,
-      invert_out => e_in.invert_out,
-      result => logical_result,
-      datalen => e_in.data_len,
-      popcnt => popcnt_result,
-      parity => parity_result);
-   
-  countzero_0 : entity work.zero_counter
-    port map(
-      clk => clk,
-      rs => c_in,
-      count_right => e_in.insn(10),
-      is_32bit => e_in.is_32bit,
-      result => countzero_result);
-   
-  multiply_0 : entity work.multiply
-    port map(
-      clk => clk,
-      m_in => x_to_multiply,
-      m_out => multiply_to_x);
-   
-  divider_0 : entity work.divider
-    port map(
-      clk => clk,
-      rst => rst,
-      d_in => x_to_divider,
-      d_out => divider_to_x);
-   
-  a_in <= r.e.write_data when ex1_bypass and e_in.bypass_data1 = '1' else  e_in.read_data1;
-  b_in <= r.e.write_data when ex1_bypass and e_in.bypass_data2 = '1' else  e_in.read_data2;
-  c_in <= r.e.write_data when ex1_bypass and e_in.bypass_data3 = '1' else  e_in.read_data3;
-   
-  execute1_0 : process(clk)
-  begin
-    if rising_edge(clk) then
-      r <= rin;
-      ctrl <= ctrl_tmp;
-      assert (r.lr_update = '1' and e_in.valid = '1')
-        report "lr update collision with valid in ex1" severity failure;
-      if r.lr_update = '1' then
-        report "lr update to " & to_hstring(r.next_lr);
-      end if;
-    end if;
-  end process;
-   
-  execute1_1 : process(all)
-    variable v : reg_type;
-    variable a_inv : std_ulogic_vector(63 downto 0);
-    variable result : std_ulogic_vector(63 downto 0);
-    variable newcrf : std_ulogic_vector(3 downto 0);
-    variable result_with_carry : std_ulogic_vector(64 downto 0);
-    variable result_en : std_ulogic;
-    variable crnum : crnum_t;
-    variable crbit : integer range 0 to 31;
-    variable scrnum : crnum_t;
-    variable lo : integer;
-    variable hi : integer;
-    variable sh : std_ulogic_vector(5 downto 0);
-    variable mb : std_ulogic_vector(5 downto 0);
-    variable me : std_ulogic_vector(5 downto 0);
-    variable sh32 : std_ulogic_vector(4 downto 0);
-    variable mb32 : std_ulogic_vector(4 downto 0);
-    variable me32 : std_ulogic_vector(4 downto 0);
-    variable bo : std_ulogic_vector(4 downto 0);
-    variable bi : std_ulogic_vector(4 downto 0);
-    variable bf : std_ulogic_vector(2 downto 0);
-    variable bfa : std_ulogic_vector(2 downto 0);
-    variable cr_op : std_ulogic_vector(9 downto 0);
-    variable cr_operands : std_ulogic_vector(1 downto 0);
-    variable bt : std_ulogic_vector(4 downto 0);
-    variable ba : std_ulogic_vector(4 downto 0);
-    variable bb : std_ulogic_vector(4 downto 0);
-    variable btnum : integer range 0 to 31;
-    variable banum : integer range 0 to 31;
-    variable bbnum : integer range 0 to 31;
-    variable crresult : std_ulogic;
-    variable l : std_ulogic;
-    variable next_nia : std_ulogic_vector(63 downto 0);
-    variable carry_32 : std_ulogic;
-    variable carry_64 : std_ulogic;
-    variable sign1 : std_ulogic;
-    variable sign2 : std_ulogic;
-    variable abs1 : signed(63 downto 0);
-    variable abs2 : signed(63 downto 0);
-    variable overflow : std_ulogic;
-    variable negative : std_ulogic;
-    variable zerohi : std_ulogic;
-    variable zerolo : std_ulogic;
-    variable msb_a : std_ulogic;
-    variable msb_b : std_ulogic;
-    variable a_lt : std_ulogic;
-    variable lv : execute1toloadstore1type;
-    variable irq_valid : std_ulogic;
-    variable exception : std_ulogic;
-  begin
-    result := (others => '0');
-    result_with_carry := (others => '0');
-    result_en := '0';
-    newcrf := (others => '0');
-    v := r;
-    v.e := execute1towritebackinit;
-    if r.e.write_xerc_enable = '1' then
-      v.e.xerc := r.e.xerc;
-    else
-      v.e.xerc := e_in.xerc;
-    end if;
-    v.lr_update := '0';
-    v.mul_in_progress := '0';
-    v.div_in_progress := '0';
-    v.cntz_in_progress := '0';
-    x_to_multiply <= execute1tomultiplyinit;
-    x_to_multiply.insn_type <= e_in.insn_type;
-    x_to_multiply.is_32bit <= e_in.is_32bit;
-    if e_in.is_32bit = '1' then
-      if e_in.is_signed = '1' then
-        x_to_multiply.data1 <= (others => a_in(31));
-        x_to_multiply.data1(31 downto 0) <= a_in(31 downto 0);
-        x_to_multiply.data2 <= (others => b_in(31));
-        x_to_multiply.data2(31 downto 0) <= b_in(31 downto 0);
-      else
-        x_to_multiply.data1 <= '0' & x"00000000" & a_in(31 downto 0);
-        x_to_multiply.data2 <= '0' & x"00000000" & b_in(31 downto 0);
-      end if;
-    else
-      if e_in.is_signed = '1' then
-        x_to_multiply.data1 <= a_in(63) & a_in;
-        x_to_multiply.data2 <= b_in(63) & b_in;
-      else
-        x_to_multiply.data1 <= '0' & a_in;
-        x_to_multiply.data2 <= '0' & b_in;
-      end if;
-    end if;
-    sign1 := '0';
-    sign2 := '0';
-    if e_in.is_signed = '1' then
-      if e_in.is_32bit = '1' then
-        sign1 := a_in(31);
-        sign2 := b_in(31);
-      else
-        sign1 := a_in(63);
-        sign2 := b_in(63);
-      end if;
-    end if;
-    if sign1 = '0' then
-      abs1 := signed(a_in);
-    else
-      abs1 := signed(a_in);
-    end if;
-    if sign2 = '0' then
-      abs2 := signed(b_in);
-    else
-      abs2 := signed(b_in);
-    end if;
-    x_to_divider <= execute1todividerinit;
-    x_to_divider.is_signed <= e_in.is_signed;
-    x_to_divider.is_32bit <= e_in.is_32bit;
-    if e_in.insn_type = op_mod then
-      x_to_divider.is_modulus <= '1';
-    end if;
-    x_to_divider.neg_result <= sign1 xor (sign2 and x_to_divider.is_modulus);
-    if e_in.is_32bit = '0' then
-      if e_in.insn_type = op_dive then
-        x_to_divider.is_extended <= '1';
-      end if;
-      x_to_divider.dividend <= std_ulogic_vector(abs1);
-      x_to_divider.divisor <= std_ulogic_vector(abs2);
-    else
-      x_to_divider.is_extended <= '0';
-      if e_in.insn_type = op_dive then
-        x_to_divider.dividend <= std_ulogic_vector(abs1(31 downto 0)) & x"00000000";
-      else
-        x_to_divider.dividend <= x"00000000" & std_ulogic_vector(abs1(31 downto 0));
-      end if;
-      x_to_divider.divisor <= x"00000000" & std_ulogic_vector(abs2(31 downto 0));
-    end if;
-    ctrl_tmp <= ctrl;
-    ctrl_tmp.tb <= std_ulogic_vector(unsigned(ctrl.tb) + 1);
-    ctrl_tmp.dec <= std_ulogic_vector(unsigned(ctrl.dec) - 1);
-    irq_valid := '0';
-    if ctrl.msr(63 - 48) = '1' and ctrl.dec(63) = '1' then
-      report "irq valid";
-      irq_valid := '1';
-    end if;
-    terminate_out <= '0';
-    icache_inval <= '0';
-    stall_out <= '0';
-    f_out <= execute1tofetch1typeinit;
-    next_nia := std_ulogic_vector(unsigned(e_in.nia) + 4);
-    right_shift <= '1' when e_in.insn_type = op_shr else  '0';
-    rot_clear_left <= '1' when e_in.insn_type = op_rlc or e_in.insn_type = op_rlcl else  '0';
-    rot_clear_right <= '1' when e_in.insn_type = op_rlc or e_in.insn_type = op_rlcr else  '0';
-    ctrl_tmp.irq_state <= write_srr0;
-    exception := '0';
-    if ctrl.irq_state = write_srr1 then
-      v.e.write_reg := fast_spr_num(spr_srr1);
-      result := ctrl.srr1;
-      result_en := '1';
-      ctrl_tmp.msr(63 - 48) <= '0';
-      f_out.redirect <= '1';
-      f_out.redirect_nia <= ctrl.irq_nia;
-      v.e.valid := '1';
-      report "writing srr1: " & to_hstring(ctrl.srr1);
-    elsif irq_valid = '1' then
-      exception := '1';
-      ctrl_tmp.irq_nia <= std_logic_vector(to_unsigned(16#900#,64));
-      ctrl_tmp.srr1 <= msr_copy(ctrl.msr);
-      result := e_in.nia;
-    elsif e_in.valid = '1' then
-      v.e.valid := '1';
-      v.e.write_reg := e_in.write_reg;
-      v.slow_op_dest := gspr_to_gpr(e_in.write_reg);
-      v.slow_op_rc := e_in.rc;
-      v.slow_op_oe := e_in.oe;
-      v.slow_op_xerc := v.e.xerc;
-      case e_in.insn_type is
-        when op_illegal =>
-          exception := '1';
-          ctrl_tmp.irq_nia <= std_logic_vector(to_unsigned(16#700#,64));
-          ctrl_tmp.srr1 <= msr_copy(ctrl.msr);
-          ctrl_tmp.srr1(63 - 44) <= '1';
-          result := e_in.nia;
-          report "illegal";
-        when op_sc =>
-          exception := '1';
-          ctrl_tmp.irq_nia <= std_logic_vector(to_unsigned(16#c00#,64));
-          ctrl_tmp.srr1 <= msr_copy(ctrl.msr);
-          result := std_logic_vector(unsigned(e_in.nia) + 4);
-          report "sc";
-        when op_attn =>
-          terminate_out <= '1';
-          report "attn";
-        when op_nop =>
-        when op_add | op_cmp =>
-          if e_in.invert_a = '0' then
-            a_inv := a_in;
-          else
-            a_inv := a_in;
-          end if;
-          result_with_carry := ppc_adde(a_inv,b_in,decode_input_carry(e_in.input_carry,v.e.xerc));
-          result := result_with_carry(63 downto 0);
-          carry_32 := result(32) xor a_inv(32) xor b_in(32);
-          carry_64 := result_with_carry(64);
-          if e_in.insn_type = op_add then
-            if e_in.output_carry = '1' then
-              ()
-            end if;
-            if e_in.oe = '1' then
-              ()
-            end if;
-            result_en := '1';
-          else
-            bf := insn_bf(e_in.insn);
-            l := insn_l(e_in.insn);
-            v.e.write_cr_enable := '1';
-            crnum := to_integer(unsigned(bf));
-            v.e.write_cr_mask := num_to_fxm(crnum);
-            zerolo := (or(a_in(31 downto 0) xor b_in(31 downto 0)));
-            zerohi := (or(a_in(63 downto 32) xor b_in(63 downto 32)));
-            if zerolo = '1' and (l = '0' or zerohi = '1') then
-              newcrf := "001" & v.e.xerc.so;
-            else
-              if l = '1' then
-                msb_a := a_in(63);
-                msb_b := b_in(63);
-              else
-                msb_a := a_in(31);
-                msb_b := b_in(31);
-              end if;
-              if msb_a /= msb_b then
-                a_lt := msb_a xnor e_in.is_signed;
-              else
-                a_lt := (l and carry_32) or (l and carry_64);
-              end if;
-              newcrf := a_lt & a_lt & '0' & v.e.xerc.so;
-            end if;
-          end if;
-        when op_and | op_or | op_xor =>
-          result := logical_result;
-          result_en := '1';
-        when op_b =>
-          f_out.redirect <= '1';
-          if (insn_aa(e_in.insn)) then
-            f_out.redirect_nia <= std_ulogic_vector(signed(b_in));
-          else
-            f_out.redirect_nia <= std_ulogic_vector(signed(e_in.nia) + signed(b_in));
-          end if;
-        when op_bc =>
-          bo := insn_bo(e_in.insn);
-          bi := insn_bi(e_in.insn);
-          if bo(4 - 2) = '0' then
-            result := std_ulogic_vector(unsigned(a_in) - 1);
-            result_en := '1';
-            v.e.write_reg := fast_spr_num(spr_ctr);
-          end if;
-          if ppc_bc_taken(bo,bi,e_in.cr,a_in) = 1 then
-            f_out.redirect <= '1';
-            if (insn_aa(e_in.insn)) then
-              f_out.redirect_nia <= std_ulogic_vector(signed(b_in));
-            else
-              f_out.redirect_nia <= std_ulogic_vector(signed(e_in.nia) + signed(b_in));
-            end if;
-          end if;
-        when op_bcreg =>
-          bo := insn_bo(e_in.insn);
-          bi := insn_bi(e_in.insn);
-          if bo(4 - 2) = '0' and e_in.insn(10) = '0' then
-            result := std_ulogic_vector(unsigned(a_in) - 1);
-            result_en := '1';
-            v.e.write_reg := fast_spr_num(spr_ctr);
-          end if;
-          if ppc_bc_taken(bo,bi,e_in.cr,a_in) = 1 then
-            f_out.redirect <= '1';
-            f_out.redirect_nia <= b_in(63 downto 2) & "00";
-          end if;
-        when op_rfid =>
-          f_out.redirect <= '1';
-          f_out.redirect_nia <= a_in(63 downto 2) & "00";
-          ctrl_tmp.msr <= msr_copy(std_ulogic_vector(signed(b_in)));
-        when op_cmpb =>
-          result := ppc_cmpb(c_in,b_in);
-          result_en := '1';
-        when op_cntz =>
-          v.e.valid := '0';
-          v.cntz_in_progress := '1';
-          stall_out <= '1';
-        when op_exts =>
-          negative := (e_in.data_len(0) and c_in(7)) or (e_in.data_len(1) and c_in(15)) or (e_in.data_len(2) and c_in(31));
-          result := (others => negative);
-          if e_in.data_len(2) = '1' then
-            result(31 downto 16) := c_in(31 downto 16);
-          end if;
-          if e_in.data_len(2) = '1' or e_in.data_len(1) = '1' then
-            result(15 downto 8) := c_in(15 downto 8);
-          end if;
-          result(7 downto 0) := c_in(7 downto 0);
-          result_en := '1';
-        when op_isel =>
-          crbit := to_integer(unsigned(insn_bc(e_in.insn)));
-          if e_in.cr(31 - crbit) = '1' then
-            result := a_in;
-          else
-            result := b_in;
-          end if;
-          result_en := '1';
-        when op_mcrf =>
-          cr_op := insn_cr(e_in.insn);
-          report "cr op " & to_hstring(cr_op);
-          if cr_op(0) = '0' then
-            bf := insn_bf(e_in.insn);
-            bfa := insn_bfa(e_in.insn);
-            v.e.write_cr_enable := '1';
-            crnum := to_integer(unsigned(bf));
-            scrnum := to_integer(unsigned(bfa));
-            v.e.write_cr_mask := num_to_fxm(crnum);
-            ;
-          else
-            v.e.write_cr_enable := '1';
-            bt := insn_bt(e_in.insn);
-            ba := insn_ba(e_in.insn);
-            bb := insn_bb(e_in.insn);
-            btnum := 31 - to_integer(unsigned(bt));
-            banum := 31 - to_integer(unsigned(ba));
-            bbnum := 31 - to_integer(unsigned(bb));
-            cr_operands := e_in.cr(banum) & e_in.cr(bbnum);
-            crresult := cr_op(5 + to_integer(unsigned(cr_operands)));
-            v.e.write_cr_mask := num_to_fxm((31 - btnum) / 4);
-          end if;
-        when op_mfmsr =>
-          result := msr_copy(ctrl.msr);
-          result_en := '1';
-        when op_mfspr =>
-          report "mfspr to spr " & integer'image(decode_spr_num(e_in.insn)) & "=" & to_hstring(a_in);
-          if is_fast_spr(e_in.read_reg1) then
-            result := a_in;
-            if decode_spr_num(e_in.insn) = spr_xer then
-              result(63 downto 32) := (others => '0');
-              result(63 - 32) := v.e.xerc.so;
-              result(63 - 33) := v.e.xerc.ov;
-              result(63 - 34) := v.e.xerc.ca;
-              result(63 - 35 downto 63 - 43) := "000000000";
-              result(63 - 44) := v.e.xerc.ov32;
-              result(63 - 45) := v.e.xerc.ca32;
-            end if;
-          else
-            case decode_spr_num(e_in.insn) is
-              when spr_tb =>
-                result := ctrl.tb;
-              when spr_dec =>
-                result := ctrl.dec;
-              when others =>
-                result := (others => '0');
-            end case;
-          end if;
-          result_en := '1';
-        when op_mfcr =>
-          if e_in.insn(20) = '0' then
-            result := x"00000000" & e_in.cr;
-          else
-            crnum := fxm_to_num(insn_fxm(e_in.insn));
-            result := (others => '0');
-          end if;
-          result_en := '1';
-        when op_mtcrf =>
-          v.e.write_cr_enable := '1';
-          if e_in.insn(20) = '0' then
-            v.e.write_cr_mask := insn_fxm(e_in.insn);
-          else
-            crnum := fxm_to_num(insn_fxm(e_in.insn));
-            v.e.write_cr_mask := num_to_fxm(crnum);
-          end if;
-          v.e.write_cr_data := c_in(31 downto 0);
-        when op_mtmsrd =>
-          ctrl_tmp.msr <= msr_copy(c_in);
-        when op_mtspr =>
-          report "mtspr to spr " & integer'image(decode_spr_num(e_in.insn)) & "=" & to_hstring(c_in);
-          if is_fast_spr(e_in.write_reg) then
-            result := c_in;
-            result_en := '1';
-            if decode_spr_num(e_in.insn) = spr_xer then
-              v.e.xerc.so := c_in(63 - 32);
-              v.e.xerc.ov := c_in(63 - 33);
-              v.e.xerc.ca := c_in(63 - 34);
-              v.e.xerc.ov32 := c_in(63 - 44);
-              v.e.xerc.ca32 := c_in(63 - 45);
-              v.e.write_xerc_enable := '1';
-            end if;
-          else
-            case decode_spr_num(e_in.insn) is
-              when spr_dec =>
-                ctrl_tmp.dec <= c_in;
-              when others =>
-            end case;
-          end if;
-        when op_popcnt =>
-          result := popcnt_result;
-          result_en := '1';
-        when op_prty =>
-          result := parity_result;
-          result_en := '1';
-        when op_rlc | op_rlcl | op_rlcr | op_shl | op_shr =>
-          result := rotator_result;
-          if e_in.output_carry = '1' then
-            ()
-          end if;
-          result_en := '1';
-        when op_sim_config =>
-          result := x"0000000000000000";
-          result_en := '1';
-        when op_tdi =>
-          report "op_tdi fixme";
-        when op_isync =>
-          f_out.redirect <= '1';
-          f_out.redirect_nia <= next_nia;
-        when op_icbi =>
-          icache_inval <= '1';
-        when op_mul_l64 | op_mul_h64 | op_mul_h32 =>
-          v.e.valid := '0';
-          v.mul_in_progress := '1';
-          stall_out <= '1';
-          x_to_multiply.valid <= '1';
-        when op_div | op_dive | op_mod =>
-          v.e.valid := '0';
-          v.div_in_progress := '1';
-          stall_out <= '1';
-          x_to_divider.valid <= '1';
-        when op_load | op_store =>
-          v.e.valid := '0';
-        when others =>
-          terminate_out <= '1';
-          report "illegal";
-      end case;
-      v.e.rc := e_in.rc and e_in.valid;
-      if e_in.lr = '1' then
-        v.lr_update := '1';
-        v.next_lr := next_nia;
-        v.e.valid := '0';
-        report "delayed lr update to " & to_hstring(next_nia);
-        stall_out <= '1';
-      end if;
-    elsif r.lr_update = '1' then
-      result_en := '1';
-      result := r.next_lr;
-      v.e.write_reg := fast_spr_num(spr_lr);
-      v.e.valid := '1';
-    elsif r.cntz_in_progress = '1' then
-      result := countzero_result;
-      result_en := '1';
-      v.e.write_reg := gpr_to_gspr(v.slow_op_dest);
-      v.e.rc := v.slow_op_rc;
-      v.e.xerc := v.slow_op_xerc;
-      v.e.valid := '1';
-    elsif r.mul_in_progress = '1' or r.div_in_progress = '1' then
-      if (r.mul_in_progress = '1' and multiply_to_x.valid = '1') or (r.div_in_progress = '1' and divider_to_x.valid = '1') then
-        if r.mul_in_progress = '1' then
-          result := multiply_to_x.write_reg_data;
-          overflow := multiply_to_x.overflow;
-        else
-          result := divider_to_x.write_reg_data;
-          overflow := divider_to_x.overflow;
-        end if;
-        result_en := '1';
-        v.e.write_reg := gpr_to_gspr(v.slow_op_dest);
-        v.e.rc := v.slow_op_rc;
-        v.e.xerc := v.slow_op_xerc;
-        v.e.write_xerc_enable := v.slow_op_oe;
-        if v.slow_op_oe = '1' then
-          v.e.xerc.ov := overflow;
-          v.e.xerc.ov32 := overflow;
-          v.e.xerc.so := v.slow_op_xerc.so or overflow;
-        end if;
-        v.e.valid := '1';
-      else
-        stall_out <= '1';
-        v.mul_in_progress := r.mul_in_progress;
-        v.div_in_progress := r.div_in_progress;
-      end if;
-    end if;
-    if exception = '1' then
-      v.e.write_reg := fast_spr_num(spr_srr0);
-      if e_in.valid = '1' then
-        result_en := '1';
-        ctrl_tmp.irq_state <= write_srr1;
-        stall_out <= '1';
-        v.e.valid := '0';
-      end if;
-    end if;
-    v.e.write_data := result;
-    v.e.write_enable := result_en;
-    lv := execute1toloadstore1init;
-    if e_in.valid = '1' and (e_in.insn_type = op_load or e_in.insn_type = op_store) then
-      lv.valid := '1';
-    end if;
-    if e_in.insn_type = op_load then
-      lv.load := '1';
-    end if;
-    lv.addr1 := a_in;
-    lv.addr2 := b_in;
-    lv.data := c_in;
-    lv.write_reg := gspr_to_gpr(e_in.write_reg);
-    lv.length := e_in.data_len;
-    lv.byte_reverse := e_in.byte_reverse;
-    lv.sign_extend := e_in.sign_extend;
-    lv.update := e_in.update;
-    lv.update_reg := gspr_to_gpr(e_in.read_reg1);
-    lv.xerc := v.e.xerc;
-    lv.reserve := e_in.reserve;
-    lv.rc := e_in.rc;
-    if e_in.insn(31 downto 26) = "011111" and e_in.insn(10 downto 9) = "11" and e_in.insn(5 downto 1) = "10101" then
-      lv.ci := '1';
-    end if;
-    rin <= v;
-    l_out <= lv;
-    e_out <= r.e;
-    flush_out <= f_out.redirect;
-  end process;
-end behaviour;