vertigo_vhdl 0.8.9 → 0.8.10
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- checksums.yaml +4 -4
- data/lib/vertigo/parser.rb +28 -5
- data/lib/vertigo/tb_generator.rb +1 -1
- data/lib/vertigo/version.rb +1 -1
- data/tests/parser_tests/test_adder_rca_vhdl93.vhd +37 -0
- metadata +4 -85
- data/tests/ghdl_tests/test_fsm.vhd +0 -162
- data/tests/parser_tests/else.vhd +0 -64
- data/tests/parser_tests/pingpong.vhd +0 -34
- data/tests/parser_tests/test_accelerator_pp.vhd +0 -144
- data/tests/parser_tests/test_aggregate_pp.vhd +0 -15
- data/tests/parser_tests/test_archi_1_pp.vhd +0 -41
- data/tests/parser_tests/test_array_array_00_pp.vhd +0 -25
- data/tests/parser_tests/test_array_urange_pp.vhd +0 -25
- data/tests/parser_tests/test_chu-1_pp.vhd +0 -104
- data/tests/parser_tests/test_concat_pp.vhd +0 -14
- data/tests/parser_tests/test_counter_pp.vhd +0 -35
- data/tests/parser_tests/test_de2_pp.vhd +0 -274
- data/tests/parser_tests/test_encode_pp.vhd +0 -2549
- data/tests/parser_tests/test_fsm_pp.vhd +0 -125
- data/tests/parser_tests/test_fsm_synth_pp.vhd +0 -197
- data/tests/parser_tests/test_function-01_pp.vhd +0 -18
- data/tests/parser_tests/test_lfsr_pp.vhd +0 -44
- data/tests/parser_tests/test_microwatt_cache_ram_pp.vhd +0 -68
- data/tests/parser_tests/test_microwatt_common_pp.vhd +0 -336
- data/tests/parser_tests/test_microwatt_control_pp.vhd +0 -187
- data/tests/parser_tests/test_microwatt_core_debug_pp.vhd +0 -104
- data/tests/parser_tests/test_microwatt_core_pp.vhd +0 -231
- data/tests/parser_tests/test_microwatt_core_tb_pp.vhd +0 -43
- data/tests/parser_tests/test_microwatt_countzero_pp.vhd +0 -120
- data/tests/parser_tests/test_microwatt_countzero_tb_pp.vhd +0 -70
- data/tests/parser_tests/test_microwatt_cr_file_pp.vhd +0 -74
- data/tests/parser_tests/test_microwatt_cr_hazard_pp.vhd +0 -51
- data/tests/parser_tests/test_microwatt_crhelpers_pp.vhd +0 -48
- data/tests/parser_tests/test_microwatt_dcache_pp.vhd +0 -481
- data/tests/parser_tests/test_microwatt_dcache_tb_pp.vhd +0 -98
- data/tests/parser_tests/test_microwatt_decode1_pp.vhd +0 -138
- data/tests/parser_tests/test_microwatt_decode2_pp.vhd +0 -300
- data/tests/parser_tests/test_microwatt_decode_types_pp.vhd +0 -67
- data/tests/parser_tests/test_microwatt_divider_pp.vhd +0 -132
- data/tests/parser_tests/test_microwatt_divider_tb_pp.vhd +0 -95
- data/tests/parser_tests/test_microwatt_dmi_dtm_dummy_pp.vhd +0 -29
- data/tests/parser_tests/test_microwatt_dmi_dtm_tb_pp.vhd +0 -197
- data/tests/parser_tests/test_microwatt_dmi_dtm_xilinx_pp.vhd +0 -139
- data/tests/parser_tests/test_microwatt_execute1_pp.vhd +0 -689
- data/tests/parser_tests/test_microwatt_fetch1_pp.vhd +0 -88
- data/tests/parser_tests/test_microwatt_fetch2_pp.vhd +0 -79
- data/tests/parser_tests/test_microwatt_glibc_random_helpers_pp.vhd +0 -25
- data/tests/parser_tests/test_microwatt_glibc_random_pp.vhd +0 -41
- data/tests/parser_tests/test_microwatt_gpr_hazard_pp.vhd +0 -68
- data/tests/parser_tests/test_microwatt_helpers_pp.vhd +0 -153
- data/tests/parser_tests/test_microwatt_icache_pp.vhd +0 -337
- data/tests/parser_tests/test_microwatt_icache_tb_pp.vhd +0 -104
- data/tests/parser_tests/test_microwatt_insn_helpers_pp.vhd +0 -208
- data/tests/parser_tests/test_microwatt_loadstore1_pp.vhd +0 -222
- data/tests/parser_tests/test_microwatt_logical_pp.vhd +0 -87
- data/tests/parser_tests/test_microwatt_multiply_pp.vhd +0 -84
- data/tests/parser_tests/test_microwatt_multiply_tb_pp.vhd +0 -75
- data/tests/parser_tests/test_microwatt_plru_pp.vhd +0 -46
- data/tests/parser_tests/test_microwatt_plru_tb_pp.vhd +0 -93
- data/tests/parser_tests/test_microwatt_ppc_fx_insns_pp.vhd +0 -665
- data/tests/parser_tests/test_microwatt_register_file_pp.vhd +0 -86
- data/tests/parser_tests/test_microwatt_rotator_pp.vhd +0 -149
- data/tests/parser_tests/test_microwatt_rotator_tb_pp.vhd +0 -134
- data/tests/parser_tests/test_microwatt_sim_bram_helpers_pp.vhd +0 -52
- data/tests/parser_tests/test_microwatt_sim_bram_pp.vhd +0 -53
- data/tests/parser_tests/test_microwatt_sim_console_pp.vhd +0 -43
- data/tests/parser_tests/test_microwatt_sim_jtag_pp.vhd +0 -64
- data/tests/parser_tests/test_microwatt_sim_jtag_socket_pp.vhd +0 -36
- data/tests/parser_tests/test_microwatt_sim_uart_pp.vhd +0 -90
- data/tests/parser_tests/test_microwatt_soc_pp.vhd +0 -195
- data/tests/parser_tests/test_microwatt_utils_pp.vhd +0 -39
- data/tests/parser_tests/test_microwatt_wishbone_arbiter_pp.vhd +0 -54
- data/tests/parser_tests/test_microwatt_wishbone_bram_tb_pp.vhd +0 -157
- data/tests/parser_tests/test_microwatt_wishbone_bram_wrapper_pp.vhd +0 -62
- data/tests/parser_tests/test_microwatt_wishbone_debug_master_pp.vhd +0 -124
- data/tests/parser_tests/test_microwatt_wishbone_types_pp.vhd +0 -38
- data/tests/parser_tests/test_microwatt_writeback_pp.vhd +0 -87
- data/tests/parser_tests/test_package-1_pp.vhd +0 -53
- data/tests/parser_tests/test_precedence_pp.vhd +0 -16
- data/tests/parser_tests/test_selected_sig_pp.vhd +0 -10
- data/tests/parser_tests/test_slice_pp.vhd +0 -16
- data/tests/parser_tests/test_tb-00_pp.vhd +0 -71
- data/tests/parser_tests/test_type_decl_02_pp.vhd +0 -11
- data/tests/parser_tests/test_use_pp.vhd +0 -10
- data/tests/parser_tests/test_while_1_pp.vhd +0 -26
- data/tests/parser_tests/test_with-00_pp.vhd +0 -12
- data/tests/tb_gen_tests/test_accelerator.vhd +0 -160
@@ -1,337 +0,0 @@
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-- generated by Vertigo VHDL tool
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.utils.all;
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use work.common.all;
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use work.wishbone_types.all;
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entity icache is
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generic(
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sim : booleanfalse := false;
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line_size : positive64 := 64;
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num_lines : positive32 := 32;
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num_ways : positive4 := 4);
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port(
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clk : in std_ulogic;
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rst : in std_ulogic;
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i_in : in fetch1toicachetype;
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i_out : out icachetofetch2type;
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stall_out : out std_ulogic;
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flush_in : in std_ulogic;
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wishbone_out : out wishbone_master_out;
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wishbone_in : in wishbone_slave_out);
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end entity icache;
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architecture rtl of icache is
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constant row_size : natural := wishbone_data_bits / 8;
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constant row_per_line : natural := line_size / row_size;
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constant bram_rows : natural := num_lines * row_per_line;
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constant insn_per_row : natural := wishbone_data_bits / 32;
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constant insn_bits : natural := log2(insn_per_row);
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constant row_bits : natural := log2(bram_rows);
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constant row_linebits : natural := log2(row_per_line);
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constant line_off_bits : natural := log2(line_size);
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constant row_off_bits : natural := log2(row_size);
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constant index_bits : natural := log2(num_lines);
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constant tag_bits : natural := 64 - line_off_bits - index_bits;
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constant way_bits : natural := log2(num_ways);
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subtype row_t is integer range 0 to bram_rows - 1;
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subtype index_t is integer range 0 to num_lines - 1;
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subtype way_t is integer range 0 to num_ways - 1;
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subtype cache_row_t is std_ulogic_vector(wishbone_data_bits - 1 downto 0);
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subtype cache_tag_t is std_logic_vector(tag_bits - 1 downto 0);
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constant tag_ram_width : natural := tag_bits * num_ways;
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subtype cache_tags_set_t is std_logic_vector(tag_ram_width - 1 downto 0);
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type cache_tags_array_t is array(range index_t) of cache_tags_set_t;
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subtype cache_way_valids_t is std_ulogic_vector(num_ways - 1 downto 0);
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type cache_valids_t is array(range index_t) of cache_way_valids_t;
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signal cache_tags : cache_tags_array_t;
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signal cache_valids : cache_valids_t;
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attribute ram_style : string;
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attribute ram_style of cache_tags : signal is "distributed";
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type state_t is (idle,wait_ack);
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type reg_internal_t is record
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hit_way : way_t;
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hit_nia : std_ulogic_vector(63 downto 0);
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hit_smark : std_ulogic;
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hit_valid : std_ulogic;
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state : state_t;
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wb : wishbone_master_out;
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store_way : way_t;
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store_index : index_t;
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store_row : row_t;
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end record;
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signal r : reg_internal_t;
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signal req_index : index_t;
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signal req_row : row_t;
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signal req_hit_way : way_t;
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signal req_tag : cache_tag_t;
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signal req_is_hit : std_ulogic;
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signal req_is_miss : std_ulogic;
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signal req_laddr : std_ulogic_vector(63 downto 0);
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type cache_ram_out_t is array(range way_t) of cache_row_t;
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signal cache_out : cache_ram_out_t;
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type plru_out_t is array(range index_t) of std_ulogic_vector(way_bits - 1 downto 0);
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signal plru_victim : plru_out_t;
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signal replace_way : way_t;
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function get_index(addr : std_ulogic_vector(63 downto 0)) return index_t is
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begin
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return to_integer(unsigned(addr(63 - tag_bits downto line_off_bits)));
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end function get_index;
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function get_row(addr : std_ulogic_vector(63 downto 0)) return row_t is
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begin
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return to_integer(unsigned(addr(63 - tag_bits downto row_off_bits)));
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end function get_row;
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function is_last_row_addr(addr : wishbone_addr_type) return boolean is
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constant ones : std_ulogic_vector(row_linebits - 1 downto 0) := (others => '1');
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begin
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return addr(line_off_bits - 1 downto row_off_bits) = ones;
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end function is_last_row_addr;
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function is_last_row(row : row_t) return boolean is
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variable row_v : std_ulogic_vector(row_bits - 1 downto 0);
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constant ones : std_ulogic_vector(row_linebits - 1 downto 0) := (others => '1');
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begin
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row_v := std_ulogic_vector(to_unsigned(row,row_bits));
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return row_v(row_linebits - 1 downto 0) = ones;
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end function is_last_row;
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function next_row_addr(addr : wishbone_addr_type) return std_ulogic_vector is
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variable row_idx : std_ulogic_vector(row_linebits - 1 downto 0);
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variable result : wishbone_addr_type;
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begin
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row_idx := addr(line_off_bits - 1 downto row_off_bits);
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row_idx := std_ulogic_vector(unsigned(row_idx) + 1);
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result := addr;
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result(line_off_bits - 1 downto row_off_bits) := row_idx;
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return result;
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end function next_row_addr;
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function next_row(row : row_t) return row_t is
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variable row_v : std_ulogic_vector(row_bits - 1 downto 0);
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variable row_idx : std_ulogic_vector(row_linebits - 1 downto 0);
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variable result : std_ulogic_vector(row_bits - 1 downto 0);
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begin
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row_v := std_ulogic_vector(to_unsigned(row,row_bits));
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row_idx := row_v(row_linebits - 1 downto 0);
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row_v(row_linebits - 1 downto 0) := std_ulogic_vector(unsigned(row_idx) + 1);
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return to_integer(unsigned(row_v));
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end function next_row;
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function read_insn_word(addr : std_ulogic_vector(63 downto 0);data : cache_row_t) return std_ulogic_vector is
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variable word : integer range 0 to insn_per_row - 1;
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begin
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word := to_integer(unsigned(addr(insn_bits + 2 - 1 downto 2)));
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return data(31 + word * 32 downto word * 32);
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end function read_insn_word;
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function get_tag(addr : std_ulogic_vector(63 downto 0)) return cache_tag_t is
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begin
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return addr(63 downto 64 - tag_bits);
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end function get_tag;
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function read_tag(way : way_t;tagset : cache_tags_set_t) return cache_tag_t is
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begin
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return tagset((way + 1) * tag_bits - 1 downto way * tag_bits);
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end function read_tag;
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procedure write_tag(
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way : in way_t;
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tagset : inout cache_tags_set_t;
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tag : cache_tag_t) is
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begin
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tagset((way + 1) * tag_bits - 1 downto way * tag_bits) := tag;
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end write_tag;
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begin
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assert line_size mod row_size = 0;
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assert ispow2(line_size)
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report "line_size not power of 2" severity failure;
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assert ispow2(num_lines)
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report "num_lines not power of 2" severity failure;
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assert ispow2(row_per_line)
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report "row_per_line not power of 2" severity failure;
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assert ispow2(insn_per_row)
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report "insn_per_row not power of 2" severity failure;
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assert (row_bits = index_bits + row_linebits)
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report "geometry bits don't add up" severity failure;
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assert (line_off_bits = row_off_bits + row_linebits)
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report "geometry bits don't add up" severity failure;
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assert (64 = tag_bits + index_bits + line_off_bits)
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report "geometry bits don't add up" severity failure;
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assert (64 = tag_bits + row_bits + row_off_bits)
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report "geometry bits don't add up" severity failure;
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if sim generate
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debug : process
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begin
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report "row_size = " & natural'image(row_size);
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report "row_per_line = " & natural'image(row_per_line);
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report "bram_rows = " & natural'image(bram_rows);
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report "insn_per_row = " & natural'image(insn_per_row);
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report "insn_bits = " & natural'image(insn_bits);
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report "row_bits = " & natural'image(row_bits);
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report "row_linebits = " & natural'image(row_linebits);
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report "line_off_bits = " & natural'image(line_off_bits);
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report "row_off_bits = " & natural'image(row_off_bits);
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report "index_bits = " & natural'image(index_bits);
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report "tag_bits = " & natural'image(tag_bits);
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report "way_bits = " & natural'image(way_bits);
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wait ;
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end process;
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end generate;
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for i in 0 to num_ways - 1 generate
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way : entity work.cache_ram
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port map(
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clk => clk,
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rd_en => do_read,
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rd_addr => rd_addr,
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rd_data => dout,
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wr_en => do_write,
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wr_sel => (others => '1'),
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wr_addr => wr_addr,
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wr_data => wishbone_in.dat);
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process(all)
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begin
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do_read <= '1';
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do_write <= '0';
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if wishbone_in.ack = '1' and r.store_way = i then
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do_write <= '1';
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end if;
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cache_out(i) <= dout;
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rd_addr <= std_ulogic_vector(to_unsigned(req_row,row_bits));
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wr_addr <= std_ulogic_vector(to_unsigned(r.store_row,row_bits));
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end process;
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end generate;
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if num_ways > 1 generate
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for i in 0 to num_lines - 1 generate
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plru : entity work.plru
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port map(
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clk => clk,
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rst => rst,
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acc => plru_acc,
|
233
|
-
acc_en => plru_acc_en,
|
234
|
-
lru => plru_out);
|
235
|
-
|
236
|
-
|
237
|
-
process(req_index,req_is_hit,req_hit_way,req_is_hit,plru_out)
|
238
|
-
begin
|
239
|
-
if req_is_hit = '1' and req_index = i then
|
240
|
-
plru_acc_en <= req_is_hit;
|
241
|
-
else
|
242
|
-
plru_acc_en <= '0';
|
243
|
-
end if;
|
244
|
-
plru_acc <= std_ulogic_vector(to_unsigned(req_hit_way,way_bits));
|
245
|
-
plru_victim(i) <= plru_out;
|
246
|
-
end process;
|
247
|
-
end generate;
|
248
|
-
end generate;
|
249
|
-
|
250
|
-
icache_comb : process(all)
|
251
|
-
variable is_hit : std_ulogic;
|
252
|
-
variable hit_way : way_t;
|
253
|
-
begin
|
254
|
-
req_index <= get_index(i_in.nia);
|
255
|
-
req_row <= get_row(i_in.nia);
|
256
|
-
req_tag <= get_tag(i_in.nia);
|
257
|
-
req_laddr <= i_in.nia(63 downto line_off_bits) & (line_off_bits - 1 downto 0 => '0');
|
258
|
-
hit_way := 0;
|
259
|
-
is_hit := '0';
|
260
|
-
req_is_hit <= i_in.req and is_hit and flush_in;
|
261
|
-
req_is_miss <= i_in.req and is_hit and flush_in;
|
262
|
-
req_hit_way <= hit_way;
|
263
|
-
replace_way <= to_integer(unsigned(plru_victim(req_index)));
|
264
|
-
i_out.insn <= read_insn_word(r.hit_nia,cache_out(r.hit_way));
|
265
|
-
i_out.valid <= r.hit_valid;
|
266
|
-
i_out.nia <= r.hit_nia;
|
267
|
-
i_out.stop_mark <= r.hit_smark;
|
268
|
-
stall_out <= is_hit;
|
269
|
-
wishbone_out <= r.wb;
|
270
|
-
end process;
|
271
|
-
|
272
|
-
icache_hit : process(clk)
|
273
|
-
begin
|
274
|
-
if rising_edge(clk) then
|
275
|
-
if req_is_hit = '1' then
|
276
|
-
r.hit_way <= req_hit_way;
|
277
|
-
r.hit_nia <= i_in.nia;
|
278
|
-
r.hit_smark <= i_in.stop_mark;
|
279
|
-
r.hit_valid <= '1';
|
280
|
-
report "cache hit nia:" & to_hstring(i_in.nia) & " sm:" & std_ulogic'image(i_in.stop_mark) & " idx:" & integer'image(req_index) & " tag:" & to_hstring(req_tag) & " way: " & integer'image(req_hit_way);
|
281
|
-
else
|
282
|
-
r.hit_valid <= '0';
|
283
|
-
r.hit_smark <= i_in.stop_mark;
|
284
|
-
end if;
|
285
|
-
end if;
|
286
|
-
end process;
|
287
|
-
|
288
|
-
icache_miss : process(clk)
|
289
|
-
variable tagset : cache_tags_set_t;
|
290
|
-
variable stbs_done : boolean;
|
291
|
-
begin
|
292
|
-
if rising_edge(clk) then
|
293
|
-
if rst = '1' then
|
294
|
-
;
|
295
|
-
r.state <= idle;
|
296
|
-
r.wb.cyc <= '0';
|
297
|
-
r.wb.stb <= '0';
|
298
|
-
r.wb.dat <= (others => '0');
|
299
|
-
r.wb.sel <= "11111111";
|
300
|
-
r.wb.we <= '0';
|
301
|
-
r.wb.adr <= (others => '0');
|
302
|
-
else
|
303
|
-
case r.state is
|
304
|
-
when idle =>
|
305
|
-
if req_is_miss = '1' then
|
306
|
-
report "cache miss nia:" & to_hstring(i_in.nia) & " sm:" & std_ulogic'image(i_in.stop_mark) & " idx:" & integer'image(req_index) & " way:" & integer'image(replace_way) & " tag:" & to_hstring(req_tag);
|
307
|
-
cache_valids(req_index)(replace_way) <= '0';
|
308
|
-
r.store_index <= req_index;
|
309
|
-
r.store_way <= replace_way;
|
310
|
-
r.store_row <= get_row(req_laddr);
|
311
|
-
r.wb.adr <= req_laddr(r.wb.adr'left downto 0);
|
312
|
-
r.wb.cyc <= '1';
|
313
|
-
r.wb.stb <= '1';
|
314
|
-
r.state <= wait_ack;
|
315
|
-
end if;
|
316
|
-
when wait_ack =>
|
317
|
-
stbs_done := r.wb.stb = '0';
|
318
|
-
if wishbone_in.stall = '0' and stbs_done then
|
319
|
-
if is_last_row_addr(r.wb.adr) then
|
320
|
-
r.wb.stb <= '0';
|
321
|
-
stbs_done := true;
|
322
|
-
end if;
|
323
|
-
r.wb.adr <= next_row_addr(r.wb.adr);
|
324
|
-
end if;
|
325
|
-
if wishbone_in.ack = '1' then
|
326
|
-
if stbs_done and is_last_row(r.store_row) then
|
327
|
-
r.wb.cyc <= '0';
|
328
|
-
cache_valids(r.store_index)(r.store_way) <= '1';
|
329
|
-
r.state <= idle;
|
330
|
-
end if;
|
331
|
-
r.store_row <= next_row(r.store_row);
|
332
|
-
end if;
|
333
|
-
end case;
|
334
|
-
end if;
|
335
|
-
end if;
|
336
|
-
end process;
|
337
|
-
end rtl;
|
@@ -1,104 +0,0 @@
|
|
1
|
-
-- generated by Vertigo VHDL tool
|
2
|
-
library ieee;
|
3
|
-
use ieee.std_logic_1164.all;
|
4
|
-
library work;
|
5
|
-
use work.common.all;
|
6
|
-
use work.wishbone_types.all;
|
7
|
-
|
8
|
-
entity icache_tb is
|
9
|
-
end entity icache_tb;
|
10
|
-
|
11
|
-
architecture behave of icache_tb is
|
12
|
-
signal clk : std_ulogic;
|
13
|
-
signal rst : std_ulogic;
|
14
|
-
signal i_out : fetch1toicachetype;
|
15
|
-
signal i_in : icachetofetch2type;
|
16
|
-
signal wb_bram_in : wishbone_master_out;
|
17
|
-
signal wb_bram_out : wishbone_slave_out;
|
18
|
-
constant clk_period : time := 10 ns;
|
19
|
-
begin
|
20
|
-
|
21
|
-
icache0 : entity work.icache
|
22
|
-
port map(
|
23
|
-
clk => clk,
|
24
|
-
rst => rst,
|
25
|
-
i_in => i_out,
|
26
|
-
i_out => i_in,
|
27
|
-
flush_in => '0',
|
28
|
-
wishbone_out => wb_bram_in,
|
29
|
-
wishbone_in => wb_bram_out);
|
30
|
-
|
31
|
-
bram0 : entity work.wishbone_bram_wrapper
|
32
|
-
port map(
|
33
|
-
clk => clk,
|
34
|
-
rst => rst,
|
35
|
-
wishbone_in => wb_bram_in,
|
36
|
-
wishbone_out => wb_bram_out);
|
37
|
-
|
38
|
-
|
39
|
-
clk_process : process
|
40
|
-
begin
|
41
|
-
clk <= '0';
|
42
|
-
wait clk_period / 2;
|
43
|
-
clk <= '1';
|
44
|
-
wait clk_period / 2;
|
45
|
-
end process;
|
46
|
-
|
47
|
-
rst_process : process
|
48
|
-
begin
|
49
|
-
rst <= '1';
|
50
|
-
wait 2 * clk_period;
|
51
|
-
rst <= '0';
|
52
|
-
wait ;
|
53
|
-
end process;
|
54
|
-
|
55
|
-
stim : process
|
56
|
-
begin
|
57
|
-
i_out.req <= '0';
|
58
|
-
i_out.nia <= (others => '0');
|
59
|
-
i_out.stop_mark <= '0';
|
60
|
-
wait rising_edge(clk);
|
61
|
-
wait rising_edge(clk);
|
62
|
-
wait rising_edge(clk);
|
63
|
-
wait rising_edge(clk);
|
64
|
-
i_out.req <= '1';
|
65
|
-
i_out.nia <= x"0000000000000004";
|
66
|
-
wait 30 * clk_period;
|
67
|
-
wait rising_edge(clk);
|
68
|
-
assert i_in.valid = '1';
|
69
|
-
assert i_in.insn = x"00000001"
|
70
|
-
report "insn @" & to_hstring(i_out.nia) & "=" & to_hstring(i_in.insn) & " expected 00000001" severity failure;
|
71
|
-
i_out.req <= '0';
|
72
|
-
wait rising_edge(clk);
|
73
|
-
i_out.req <= '1';
|
74
|
-
i_out.nia <= x"0000000000000008";
|
75
|
-
wait rising_edge(clk);
|
76
|
-
wait rising_edge(clk);
|
77
|
-
assert i_in.valid = '1';
|
78
|
-
assert i_in.insn = x"00000002"
|
79
|
-
report "insn @" & to_hstring(i_out.nia) & "=" & to_hstring(i_in.insn) & " expected 00000002" severity failure;
|
80
|
-
wait rising_edge(clk);
|
81
|
-
i_out.req <= '1';
|
82
|
-
i_out.nia <= x"0000000000000040";
|
83
|
-
wait 30 * clk_period;
|
84
|
-
wait rising_edge(clk);
|
85
|
-
assert i_in.valid = '1';
|
86
|
-
assert i_in.insn = x"00000010"
|
87
|
-
report "insn @" & to_hstring(i_out.nia) & "=" & to_hstring(i_in.insn) & " expected 00000010" severity failure;
|
88
|
-
i_out.req <= '1';
|
89
|
-
i_out.nia <= x"0000000000000100";
|
90
|
-
wait rising_edge(clk);
|
91
|
-
wait rising_edge(clk);
|
92
|
-
assert i_in.valid = '0';
|
93
|
-
wait rising_edge(clk);
|
94
|
-
wait 30 * clk_period;
|
95
|
-
wait rising_edge(clk);
|
96
|
-
assert i_in.valid = '1';
|
97
|
-
assert i_in.insn = x"00000040"
|
98
|
-
report "insn @" & to_hstring(i_out.nia) & "=" & to_hstring(i_in.insn) & " expected 00000040" severity failure;
|
99
|
-
i_out.req <= '0';
|
100
|
-
assert false
|
101
|
-
report "end of test" severity failure;
|
102
|
-
wait ;
|
103
|
-
end process;
|
104
|
-
end behave;
|
@@ -1,208 +0,0 @@
|
|
1
|
-
-- generated by Vertigo VHDL tool
|
2
|
-
library ieee;
|
3
|
-
use ieee.std_logic_1164.all;
|
4
|
-
|
5
|
-
package insn_helpers is
|
6
|
-
function insn_rs(insn_in : std_ulogic_vector) return std_ulogic_vector
|
7
|
-
function insn_rt(insn_in : std_ulogic_vector) return std_ulogic_vector
|
8
|
-
function insn_ra(insn_in : std_ulogic_vector) return std_ulogic_vector
|
9
|
-
function insn_rb(insn_in : std_ulogic_vector) return std_ulogic_vector
|
10
|
-
function insn_si(insn_in : std_ulogic_vector) return std_ulogic_vector
|
11
|
-
function insn_ui(insn_in : std_ulogic_vector) return std_ulogic_vector
|
12
|
-
function insn_l(insn_in : std_ulogic_vector) return std_ulogic
|
13
|
-
function insn_sh32(insn_in : std_ulogic_vector) return std_ulogic_vector
|
14
|
-
function insn_mb32(insn_in : std_ulogic_vector) return std_ulogic_vector
|
15
|
-
function insn_me32(insn_in : std_ulogic_vector) return std_ulogic_vector
|
16
|
-
function insn_li(insn_in : std_ulogic_vector) return std_ulogic_vector
|
17
|
-
function insn_lk(insn_in : std_ulogic_vector) return std_ulogic
|
18
|
-
function insn_aa(insn_in : std_ulogic_vector) return std_ulogic
|
19
|
-
function insn_rc(insn_in : std_ulogic_vector) return std_ulogic
|
20
|
-
function insn_oe(insn_in : std_ulogic_vector) return std_ulogic
|
21
|
-
function insn_bd(insn_in : std_ulogic_vector) return std_ulogic_vector
|
22
|
-
function insn_bf(insn_in : std_ulogic_vector) return std_ulogic_vector
|
23
|
-
function insn_bfa(insn_in : std_ulogic_vector) return std_ulogic_vector
|
24
|
-
function insn_cr(insn_in : std_ulogic_vector) return std_ulogic_vector
|
25
|
-
function insn_bt(insn_in : std_ulogic_vector) return std_ulogic_vector
|
26
|
-
function insn_ba(insn_in : std_ulogic_vector) return std_ulogic_vector
|
27
|
-
function insn_bb(insn_in : std_ulogic_vector) return std_ulogic_vector
|
28
|
-
function insn_fxm(insn_in : std_ulogic_vector) return std_ulogic_vector
|
29
|
-
function insn_bo(insn_in : std_ulogic_vector) return std_ulogic_vector
|
30
|
-
function insn_bi(insn_in : std_ulogic_vector) return std_ulogic_vector
|
31
|
-
function insn_bh(insn_in : std_ulogic_vector) return std_ulogic_vector
|
32
|
-
function insn_d(insn_in : std_ulogic_vector) return std_ulogic_vector
|
33
|
-
function insn_ds(insn_in : std_ulogic_vector) return std_ulogic_vector
|
34
|
-
function insn_to(insn_in : std_ulogic_vector) return std_ulogic_vector
|
35
|
-
function insn_bc(insn_in : std_ulogic_vector) return std_ulogic_vector
|
36
|
-
function insn_sh(insn_in : std_ulogic_vector) return std_ulogic_vector
|
37
|
-
function insn_me(insn_in : std_ulogic_vector) return std_ulogic_vector
|
38
|
-
function insn_mb(insn_in : std_ulogic_vector) return std_ulogic_vector
|
39
|
-
|
40
|
-
end insn_helpers;
|
41
|
-
|
42
|
-
package body insn_helpers is
|
43
|
-
|
44
|
-
function insn_rs(insn_in : std_ulogic_vector) return std_ulogic_vector is
|
45
|
-
begin
|
46
|
-
return insn_in(25 downto 21);
|
47
|
-
end function insn_rs;
|
48
|
-
|
49
|
-
function insn_rt(insn_in : std_ulogic_vector) return std_ulogic_vector is
|
50
|
-
begin
|
51
|
-
return insn_in(25 downto 21);
|
52
|
-
end function insn_rt;
|
53
|
-
|
54
|
-
function insn_ra(insn_in : std_ulogic_vector) return std_ulogic_vector is
|
55
|
-
begin
|
56
|
-
return insn_in(20 downto 16);
|
57
|
-
end function insn_ra;
|
58
|
-
|
59
|
-
function insn_rb(insn_in : std_ulogic_vector) return std_ulogic_vector is
|
60
|
-
begin
|
61
|
-
return insn_in(15 downto 11);
|
62
|
-
end function insn_rb;
|
63
|
-
|
64
|
-
function insn_si(insn_in : std_ulogic_vector) return std_ulogic_vector is
|
65
|
-
begin
|
66
|
-
return insn_in(15 downto 0);
|
67
|
-
end function insn_si;
|
68
|
-
|
69
|
-
function insn_ui(insn_in : std_ulogic_vector) return std_ulogic_vector is
|
70
|
-
begin
|
71
|
-
return insn_in(15 downto 0);
|
72
|
-
end function insn_ui;
|
73
|
-
|
74
|
-
function insn_l(insn_in : std_ulogic_vector) return std_ulogic is
|
75
|
-
begin
|
76
|
-
return insn_in(21);
|
77
|
-
end function insn_l;
|
78
|
-
|
79
|
-
function insn_sh32(insn_in : std_ulogic_vector) return std_ulogic_vector is
|
80
|
-
begin
|
81
|
-
return insn_in(15 downto 11);
|
82
|
-
end function insn_sh32;
|
83
|
-
|
84
|
-
function insn_mb32(insn_in : std_ulogic_vector) return std_ulogic_vector is
|
85
|
-
begin
|
86
|
-
return insn_in(10 downto 6);
|
87
|
-
end function insn_mb32;
|
88
|
-
|
89
|
-
function insn_me32(insn_in : std_ulogic_vector) return std_ulogic_vector is
|
90
|
-
begin
|
91
|
-
return insn_in(5 downto 1);
|
92
|
-
end function insn_me32;
|
93
|
-
|
94
|
-
function insn_li(insn_in : std_ulogic_vector) return std_ulogic_vector is
|
95
|
-
begin
|
96
|
-
return insn_in(25 downto 2);
|
97
|
-
end function insn_li;
|
98
|
-
|
99
|
-
function insn_lk(insn_in : std_ulogic_vector) return std_ulogic is
|
100
|
-
begin
|
101
|
-
return insn_in(0);
|
102
|
-
end function insn_lk;
|
103
|
-
|
104
|
-
function insn_aa(insn_in : std_ulogic_vector) return std_ulogic is
|
105
|
-
begin
|
106
|
-
return insn_in(1);
|
107
|
-
end function insn_aa;
|
108
|
-
|
109
|
-
function insn_rc(insn_in : std_ulogic_vector) return std_ulogic is
|
110
|
-
begin
|
111
|
-
return insn_in(0);
|
112
|
-
end function insn_rc;
|
113
|
-
|
114
|
-
function insn_oe(insn_in : std_ulogic_vector) return std_ulogic is
|
115
|
-
begin
|
116
|
-
return insn_in(10);
|
117
|
-
end function insn_oe;
|
118
|
-
|
119
|
-
function insn_bd(insn_in : std_ulogic_vector) return std_ulogic_vector is
|
120
|
-
begin
|
121
|
-
return insn_in(15 downto 2);
|
122
|
-
end function insn_bd;
|
123
|
-
|
124
|
-
function insn_bf(insn_in : std_ulogic_vector) return std_ulogic_vector is
|
125
|
-
begin
|
126
|
-
return insn_in(25 downto 23);
|
127
|
-
end function insn_bf;
|
128
|
-
|
129
|
-
function insn_bfa(insn_in : std_ulogic_vector) return std_ulogic_vector is
|
130
|
-
begin
|
131
|
-
return insn_in(20 downto 18);
|
132
|
-
end function insn_bfa;
|
133
|
-
|
134
|
-
function insn_cr(insn_in : std_ulogic_vector) return std_ulogic_vector is
|
135
|
-
begin
|
136
|
-
return insn_in(10 downto 1);
|
137
|
-
end function insn_cr;
|
138
|
-
|
139
|
-
function insn_bb(insn_in : std_ulogic_vector) return std_ulogic_vector is
|
140
|
-
begin
|
141
|
-
return insn_in(15 downto 11);
|
142
|
-
end function insn_bb;
|
143
|
-
|
144
|
-
function insn_ba(insn_in : std_ulogic_vector) return std_ulogic_vector is
|
145
|
-
begin
|
146
|
-
return insn_in(20 downto 16);
|
147
|
-
end function insn_ba;
|
148
|
-
|
149
|
-
function insn_bt(insn_in : std_ulogic_vector) return std_ulogic_vector is
|
150
|
-
begin
|
151
|
-
return insn_in(25 downto 21);
|
152
|
-
end function insn_bt;
|
153
|
-
|
154
|
-
function insn_fxm(insn_in : std_ulogic_vector) return std_ulogic_vector is
|
155
|
-
begin
|
156
|
-
return insn_in(19 downto 12);
|
157
|
-
end function insn_fxm;
|
158
|
-
|
159
|
-
function insn_bo(insn_in : std_ulogic_vector) return std_ulogic_vector is
|
160
|
-
begin
|
161
|
-
return insn_in(25 downto 21);
|
162
|
-
end function insn_bo;
|
163
|
-
|
164
|
-
function insn_bi(insn_in : std_ulogic_vector) return std_ulogic_vector is
|
165
|
-
begin
|
166
|
-
return insn_in(20 downto 16);
|
167
|
-
end function insn_bi;
|
168
|
-
|
169
|
-
function insn_bh(insn_in : std_ulogic_vector) return std_ulogic_vector is
|
170
|
-
begin
|
171
|
-
return insn_in(12 downto 11);
|
172
|
-
end function insn_bh;
|
173
|
-
|
174
|
-
function insn_d(insn_in : std_ulogic_vector) return std_ulogic_vector is
|
175
|
-
begin
|
176
|
-
return insn_in(15 downto 0);
|
177
|
-
end function insn_d;
|
178
|
-
|
179
|
-
function insn_ds(insn_in : std_ulogic_vector) return std_ulogic_vector is
|
180
|
-
begin
|
181
|
-
return insn_in(15 downto 2);
|
182
|
-
end function insn_ds;
|
183
|
-
|
184
|
-
function insn_to(insn_in : std_ulogic_vector) return std_ulogic_vector is
|
185
|
-
begin
|
186
|
-
return insn_in(25 downto 21);
|
187
|
-
end function insn_to;
|
188
|
-
|
189
|
-
function insn_bc(insn_in : std_ulogic_vector) return std_ulogic_vector is
|
190
|
-
begin
|
191
|
-
return insn_in(10 downto 6);
|
192
|
-
end function insn_bc;
|
193
|
-
|
194
|
-
function insn_sh(insn_in : std_ulogic_vector) return std_ulogic_vector is
|
195
|
-
begin
|
196
|
-
return insn_in(1) & insn_in(15 downto 11);
|
197
|
-
end function insn_sh;
|
198
|
-
|
199
|
-
function insn_me(insn_in : std_ulogic_vector) return std_ulogic_vector is
|
200
|
-
begin
|
201
|
-
return insn_in(5) & insn_in(10 downto 6);
|
202
|
-
end function insn_me;
|
203
|
-
|
204
|
-
function insn_mb(insn_in : std_ulogic_vector) return std_ulogic_vector is
|
205
|
-
begin
|
206
|
-
return insn_in(5) & insn_in(10 downto 6);
|
207
|
-
end function insn_mb;
|
208
|
-
end insn_helpers;
|