soc_maker 0.1.1

This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
Files changed (116) hide show
  1. checksums.yaml +7 -0
  2. data/.gitignore +5 -0
  3. data/History.txt +4 -0
  4. data/LICENSE +678 -0
  5. data/README.rdoc +228 -0
  6. data/Rakefile +46 -0
  7. data/bin/soc_maker_cli +80 -0
  8. data/bin/soc_maker_parser +85 -0
  9. data/core_lib/cores/adv_debug_sys/01_adv_debug_sys.yaml +245 -0
  10. data/core_lib/cores/or1200_rel2/01_or1200.yaml +208 -0
  11. data/core_lib/cores/or1200_rel2/02_or1200_files.yaml +421 -0
  12. data/core_lib/cores/or1200_rel2/03_or1200_sparam.yaml +188 -0
  13. data/core_lib/cores/or1200_rel2/or1200_defines.v.in +1799 -0
  14. data/core_lib/cores/ram_wb/ram_wb.yaml +102 -0
  15. data/core_lib/cores/ram_wb/ram_wb_b3.v.in +259 -0
  16. data/core_lib/cores/uart16550/01_uart16550.yaml +99 -0
  17. data/core_lib/cores/uart16550/02_uart16550_files.yaml +70 -0
  18. data/core_lib/cores/wb_connect/minsoc_tc_top.v +1802 -0
  19. data/core_lib/cores/wb_connect/wb_connect.yaml +733 -0
  20. data/core_lib/inc.yaml +13 -0
  21. data/core_lib/interfaces/clk_rst/clk.yaml +9 -0
  22. data/core_lib/interfaces/clk_rst/rst.yaml +9 -0
  23. data/core_lib/interfaces/clk_rst/single.yaml +7 -0
  24. data/core_lib/interfaces/debug/debug.yaml +32 -0
  25. data/core_lib/interfaces/jtag/jtag.yaml +13 -0
  26. data/core_lib/interfaces/jtag/jtag_tap.yaml +22 -0
  27. data/core_lib/interfaces/power/or_power.yaml +25 -0
  28. data/core_lib/interfaces/uart/uart.yaml +21 -0
  29. data/core_lib/interfaces/wishbone/wishbone_ma_b3.yaml +54 -0
  30. data/core_lib/interfaces/wishbone/wishbone_sl_b3.yaml +51 -0
  31. data/doc/class_arch.uml +5113 -0
  32. data/doc/fig/hierarchical.svg +273 -0
  33. data/examples/or1200_test/or1200_test.cmd +78 -0
  34. data/examples/or1200_test/or1200_test.rb +136 -0
  35. data/examples/or1200_test/rtl/or1200_test_top.vhd +274 -0
  36. data/examples/or1200_test/rtl/s3astarter.ucf +10 -0
  37. data/examples/or1200_test/rtl/xilinx_internal_jtag.v +438 -0
  38. data/examples/or1200_test/rtl/xilinx_internal_jtag_options.v +12 -0
  39. data/examples/or1200_test/sw/README.txt +35 -0
  40. data/examples/or1200_test/sw/bin2vmem.c +159 -0
  41. data/examples/or1200_test/sw/board.h +24 -0
  42. data/examples/or1200_test/sw/compile.sh +18 -0
  43. data/examples/or1200_test/sw/except.S +152 -0
  44. data/examples/or1200_test/sw/int.c +79 -0
  45. data/examples/or1200_test/sw/int.h +14 -0
  46. data/examples/or1200_test/sw/interconnect.h +17 -0
  47. data/examples/or1200_test/sw/interrupts.c +14 -0
  48. data/examples/or1200_test/sw/main.c +16 -0
  49. data/examples/or1200_test/sw/or1200.h +454 -0
  50. data/examples/or1200_test/sw/orp.ld +60 -0
  51. data/examples/or1200_test/sw/reset.S +112 -0
  52. data/examples/or1200_test/sw/support.c +123 -0
  53. data/examples/or1200_test/sw/support.h +33 -0
  54. data/examples/or1200_test/sw/tick.c +30 -0
  55. data/examples/or1200_test/sw/tick.h +2 -0
  56. data/examples/or1200_test/sw/uart.c +136 -0
  57. data/examples/or1200_test/sw/uart.h +126 -0
  58. data/lib/soc_maker.rb +324 -0
  59. data/lib/soc_maker/cli.rb +544 -0
  60. data/lib/soc_maker/conf.rb +310 -0
  61. data/lib/soc_maker/core_def.rb +579 -0
  62. data/lib/soc_maker/core_inst.rb +305 -0
  63. data/lib/soc_maker/err.rb +211 -0
  64. data/lib/soc_maker/hdl_coder.rb +500 -0
  65. data/lib/soc_maker/hdl_file.rb +166 -0
  66. data/lib/soc_maker/hdl_parser.rb +431 -0
  67. data/lib/soc_maker/ifc_def.rb +193 -0
  68. data/lib/soc_maker/ifc_port.rb +133 -0
  69. data/lib/soc_maker/ifc_spc.rb +180 -0
  70. data/lib/soc_maker/lib.rb +289 -0
  71. data/lib/soc_maker/lib_inc.rb +109 -0
  72. data/lib/soc_maker/parameter.rb +149 -0
  73. data/lib/soc_maker/soc_def.rb +847 -0
  74. data/lib/soc_maker/sparameter.rb +289 -0
  75. data/lib/soc_maker/version.rb +8 -0
  76. data/lib/soc_maker/ypp.rb +130 -0
  77. data/soc_maker.gemspec +28 -0
  78. data/spec/cli_cmds1.txt +39 -0
  79. data/spec/cli_spec.rb +49 -0
  80. data/spec/conf_spec.rb +44 -0
  81. data/spec/core_def_spec.rb +503 -0
  82. data/spec/core_inst_spec.rb +169 -0
  83. data/spec/hdl_file_spec.rb +154 -0
  84. data/spec/hdl_parser_spec.rb +201 -0
  85. data/spec/ifc_def_spec.rb +121 -0
  86. data/spec/ifc_port_spec.rb +92 -0
  87. data/spec/ifc_spc_spec.rb +196 -0
  88. data/spec/lib_inc_spec.rb +99 -0
  89. data/spec/lib_spec.rb +209 -0
  90. data/spec/parameter_spec.rb +86 -0
  91. data/spec/soc_def_spec.rb +611 -0
  92. data/spec/soc_maker_spec.rb +7 -0
  93. data/spec/sparameter_spec.rb +182 -0
  94. data/spec/spec_helper.rb +78 -0
  95. data/spec/test_soc.yaml +105 -0
  96. data/spec/test_soc2.yaml +60 -0
  97. data/spec/test_soc_lib/cores/core_A_rel1/00_core_a.yaml +75 -0
  98. data/spec/test_soc_lib/cores/core_A_rel1/01_core_a.yaml +57 -0
  99. data/spec/test_soc_lib/cores/core_A_rel1/core_a.vhd +29 -0
  100. data/spec/test_soc_lib/cores/core_A_rel1/core_a_pkg.vhd.src +3 -0
  101. data/spec/test_soc_lib/cores/core_A_rel1/core_a_pkg2.vhd.src +4 -0
  102. data/spec/test_soc_lib/cores/core_A_rel1/core_a_pkg3.v.src +6 -0
  103. data/spec/test_soc_lib/cores/core_B_rel1/core_b.vhd +25 -0
  104. data/spec/test_soc_lib/cores/core_B_rel1/core_b.yaml +36 -0
  105. data/spec/test_soc_lib/cores/core_C_v1/core_C.vhd +57 -0
  106. data/spec/test_soc_lib/cores/core_C_v1/core_c.yaml +42 -0
  107. data/spec/test_soc_lib/cores/soc_A/soc_A.yaml +12 -0
  108. data/spec/test_soc_lib/cores/soc_maker_include.yaml +6 -0
  109. data/spec/test_soc_lib/ifcs/core_AB_ifc/bidir_ifc.yaml +19 -0
  110. data/spec/test_soc_lib/ifcs/core_AB_ifc/core_AB_ifc.yaml +15 -0
  111. data/spec/test_soc_lib/ifcs/core_AB_ifc/top_ifc.yaml +9 -0
  112. data/spec/test_soc_lib/soc_maker_include.yaml +4 -0
  113. data/spec/yaml_examples.rb +367 -0
  114. data/spec/ypp_spec.rb +156 -0
  115. data/test/test_soc_maker.rb +0 -0
  116. metadata +255 -0
data/core_lib/cores/wb_connect/wb_connect.yaml ADDED
@@ -0,0 +1,733 @@
1
+ SOCM_CORE
2
+ name: wb_connect
3
+ description: A block to connect RISC and peripheral controllers together
4
+ id: wb_connect,1
5
+ license: LGPL
6
+ licensefile:
7
+ author: Damjan Lampret
8
+ authormail: lampret@opencores.org
9
+ toplevel: minsoc_tc_top
10
+
11
+
12
+ inst_parameters:
13
+ :t0_addr_w: SOCM_PARAM
14
+ type: integer
15
+ default: 8
16
+ :t0_addr: SOCM_PARAM
17
+ type: integer
18
+ default: 0x00
19
+ :t1_addr_w: SOCM_PARAM
20
+ type: integer
21
+ default: 8
22
+ :t1_addr: SOCM_PARAM
23
+ type: integer
24
+ default: 0x04
25
+ :t28c_addr_w: SOCM_PARAM
26
+ type: integer
27
+ default: 4
28
+ :t28_addr: SOCM_PARAM
29
+ type: integer
30
+ default: 0x9
31
+ :t28i_addr_w: SOCM_PARAM
32
+ type: integer
33
+ default: 8
34
+ :t2_addr: SOCM_PARAM
35
+ type: integer
36
+ default: 0x97
37
+ :t3_addr: SOCM_PARAM
38
+ type: integer
39
+ default: 0x92
40
+ :t4_addr: SOCM_PARAM
41
+ type: integer
42
+ default: 0x9d
43
+ :t5_addr: SOCM_PARAM
44
+ type: integer
45
+ default: 0x90
46
+ :t6_addr: SOCM_PARAM
47
+ type: integer
48
+ default: 0x94
49
+ :t7_addr: SOCM_PARAM
50
+ type: integer
51
+ default: 0x9e
52
+ :t8_addr: SOCM_PARAM
53
+ type: integer
54
+ default: 0x9f
55
+
56
+
57
+
58
+ interfaces:
59
+
60
+ :clk: SOCM_IFC
61
+ name: clk
62
+ dir: 1
63
+ id: clk,1
64
+ ports:
65
+ :wb_clk_i: SOCM_PORT
66
+ len: 1
67
+ spc_ref: clk
68
+
69
+ :rst: SOCM_IFC
70
+ name: rst
71
+ dir: 1
72
+ id: rst,1
73
+ ports:
74
+ :wb_rst_i: SOCM_PORT
75
+ len: 1
76
+ spc_ref: rst
77
+
78
+ :i0: SOCM_IFC
79
+ name: wishbone_ma
80
+ dir: 0
81
+ id: wishbone_ma,b3
82
+ ports:
83
+ :i0_wb_clk_o: SOCM_PORT
84
+ spc_ref: clk
85
+ len: 1
86
+ :i0_wb_rst_o: SOCM_PORT
87
+ spc_ref: rst
88
+ len: 1
89
+ :i0_wb_cyc_i: SOCM_PORT
90
+ spc_ref: cyc
91
+ len: 1
92
+ :i0_wb_stb_i: SOCM_PORT
93
+ spc_ref: stb
94
+ len: 1
95
+ :i0_wb_adr_i: SOCM_PORT
96
+ spc_ref: adr
97
+ len: 32
98
+ :i0_wb_sel_i: SOCM_PORT
99
+ spc_ref: sel
100
+ len: 4
101
+ :i0_wb_we_i: SOCM_PORT
102
+ spc_ref: we
103
+ len: 1
104
+ :i0_wb_dat_i: SOCM_PORT
105
+ spc_ref: dat_i
106
+ len: 32
107
+ :i0_wb_dat_o: SOCM_PORT
108
+ spc_ref: dat_o
109
+ len: 32
110
+ :i0_wb_ack_o: SOCM_PORT
111
+ spc_ref: ack
112
+ len: 1
113
+ :i0_wb_err_o: SOCM_PORT
114
+ spc_ref: err
115
+ len: 1
116
+ :i1: SOCM_IFC
117
+ name: wishbone_ma
118
+ dir: 0
119
+ id: wishbone_ma,b3
120
+ ports:
121
+ :i1_wb_clk_o: SOCM_PORT
122
+ spc_ref: clk
123
+ len: 1
124
+ :i1_wb_rst_o: SOCM_PORT
125
+ spc_ref: rst
126
+ len: 1
127
+ :i1_wb_cyc_i: SOCM_PORT
128
+ spc_ref: cyc
129
+ len: 1
130
+ :i1_wb_stb_i: SOCM_PORT
131
+ spc_ref: stb
132
+ len: 1
133
+ :i1_wb_adr_i: SOCM_PORT
134
+ spc_ref: adr
135
+ len: 32
136
+ :i1_wb_sel_i: SOCM_PORT
137
+ spc_ref: sel
138
+ len: 4
139
+ :i1_wb_we_i: SOCM_PORT
140
+ spc_ref: we
141
+ len: 1
142
+ :i1_wb_dat_i: SOCM_PORT
143
+ spc_ref: dat_i
144
+ len: 32
145
+ :i1_wb_dat_o: SOCM_PORT
146
+ spc_ref: dat_o
147
+ len: 32
148
+ :i1_wb_ack_o: SOCM_PORT
149
+ spc_ref: ack
150
+ len: 1
151
+ :i1_wb_err_o: SOCM_PORT
152
+ spc_ref: err
153
+ len: 1
154
+ :i2: SOCM_IFC
155
+ name: wishbone_ma
156
+ dir: 0
157
+ id: wishbone_ma,b3
158
+ ports:
159
+ :i2_wb_clk_o: SOCM_PORT
160
+ spc_ref: clk
161
+ len: 1
162
+ :i2_wb_rst_o: SOCM_PORT
163
+ spc_ref: rst
164
+ len: 1
165
+ :i2_wb_cyc_i: SOCM_PORT
166
+ spc_ref: cyc
167
+ len: 1
168
+ :i2_wb_stb_i: SOCM_PORT
169
+ spc_ref: stb
170
+ len: 1
171
+ :i2_wb_adr_i: SOCM_PORT
172
+ spc_ref: adr
173
+ len: 32
174
+ :i2_wb_sel_i: SOCM_PORT
175
+ spc_ref: sel
176
+ len: 4
177
+ :i2_wb_we_i: SOCM_PORT
178
+ spc_ref: we
179
+ len: 1
180
+ :i2_wb_dat_i: SOCM_PORT
181
+ spc_ref: dat_i
182
+ len: 32
183
+ :i2_wb_dat_o: SOCM_PORT
184
+ spc_ref: dat_o
185
+ len: 32
186
+ :i2_wb_ack_o: SOCM_PORT
187
+ spc_ref: ack
188
+ len: 1
189
+ :i2_wb_err_o: SOCM_PORT
190
+ spc_ref: err
191
+ len: 1
192
+ :i3: SOCM_IFC
193
+ name: wishbone_ma
194
+ dir: 0
195
+ id: wishbone_ma,b3
196
+ ports:
197
+ :i3_wb_clk_o: SOCM_PORT
198
+ spc_ref: clk
199
+ len: 1
200
+ :i3_wb_rst_o: SOCM_PORT
201
+ spc_ref: rst
202
+ len: 1
203
+ :i3_wb_cyc_i: SOCM_PORT
204
+ spc_ref: cyc
205
+ len: 1
206
+ :i3_wb_stb_i: SOCM_PORT
207
+ spc_ref: stb
208
+ len: 1
209
+ :i3_wb_adr_i: SOCM_PORT
210
+ spc_ref: adr
211
+ len: 32
212
+ :i3_wb_sel_i: SOCM_PORT
213
+ spc_ref: sel
214
+ len: 4
215
+ :i3_wb_we_i: SOCM_PORT
216
+ spc_ref: we
217
+ len: 1
218
+ :i3_wb_dat_i: SOCM_PORT
219
+ spc_ref: dat_i
220
+ len: 32
221
+ :i3_wb_dat_o: SOCM_PORT
222
+ spc_ref: dat_o
223
+ len: 32
224
+ :i3_wb_ack_o: SOCM_PORT
225
+ spc_ref: ack
226
+ len: 1
227
+ :i3_wb_err_o: SOCM_PORT
228
+ spc_ref: err
229
+ len: 1
230
+ :i4: SOCM_IFC
231
+ name: wishbone_ma
232
+ dir: 0
233
+ id: wishbone_ma,b3
234
+ ports:
235
+ :i4_wb_clk_o: SOCM_PORT
236
+ spc_ref: clk
237
+ len: 1
238
+ :i4_wb_rst_o: SOCM_PORT
239
+ spc_ref: rst
240
+ len: 1
241
+ :i4_wb_cyc_i: SOCM_PORT
242
+ spc_ref: cyc
243
+ len: 1
244
+ :i4_wb_stb_i: SOCM_PORT
245
+ spc_ref: stb
246
+ len: 1
247
+ :i4_wb_adr_i: SOCM_PORT
248
+ spc_ref: adr
249
+ len: 32
250
+ :i4_wb_sel_i: SOCM_PORT
251
+ spc_ref: sel
252
+ len: 4
253
+ :i4_wb_we_i: SOCM_PORT
254
+ spc_ref: we
255
+ len: 1
256
+ :i4_wb_dat_i: SOCM_PORT
257
+ spc_ref: dat_i
258
+ len: 32
259
+ :i4_wb_dat_o: SOCM_PORT
260
+ spc_ref: dat_o
261
+ len: 32
262
+ :i4_wb_ack_o: SOCM_PORT
263
+ spc_ref: ack
264
+ len: 1
265
+ :i4_wb_err_o: SOCM_PORT
266
+ spc_ref: err
267
+ len: 1
268
+ :i5: SOCM_IFC
269
+ name: wishbone_ma
270
+ dir: 0
271
+ id: wishbone_ma,b3
272
+ ports:
273
+ :i5_wb_clk_o: SOCM_PORT
274
+ spc_ref: clk
275
+ len: 1
276
+ :i5_wb_rst_o: SOCM_PORT
277
+ spc_ref: rst
278
+ len: 1
279
+ :i5_wb_cyc_i: SOCM_PORT
280
+ spc_ref: cyc
281
+ len: 1
282
+ :i5_wb_stb_i: SOCM_PORT
283
+ spc_ref: stb
284
+ len: 1
285
+ :i5_wb_adr_i: SOCM_PORT
286
+ spc_ref: adr
287
+ len: 32
288
+ :i5_wb_sel_i: SOCM_PORT
289
+ spc_ref: sel
290
+ len: 4
291
+ :i5_wb_we_i: SOCM_PORT
292
+ spc_ref: we
293
+ len: 1
294
+ :i5_wb_dat_i: SOCM_PORT
295
+ spc_ref: dat_i
296
+ len: 32
297
+ :i5_wb_dat_o: SOCM_PORT
298
+ spc_ref: dat_o
299
+ len: 32
300
+ :i5_wb_ack_o: SOCM_PORT
301
+ spc_ref: ack
302
+ len: 1
303
+ :i5_wb_err_o: SOCM_PORT
304
+ spc_ref: err
305
+ len: 1
306
+ :i6: SOCM_IFC
307
+ name: wishbone_ma
308
+ dir: 0
309
+ id: wishbone_ma,b3
310
+ ports:
311
+ :i6_wb_clk_o: SOCM_PORT
312
+ spc_ref: clk
313
+ len: 1
314
+ :i6_wb_rst_o: SOCM_PORT
315
+ spc_ref: rst
316
+ len: 1
317
+ :i6_wb_cyc_i: SOCM_PORT
318
+ spc_ref: cyc
319
+ len: 1
320
+ :i6_wb_stb_i: SOCM_PORT
321
+ spc_ref: stb
322
+ len: 1
323
+ :i6_wb_adr_i: SOCM_PORT
324
+ spc_ref: adr
325
+ len: 32
326
+ :i6_wb_sel_i: SOCM_PORT
327
+ spc_ref: sel
328
+ len: 4
329
+ :i6_wb_we_i: SOCM_PORT
330
+ spc_ref: we
331
+ len: 1
332
+ :i6_wb_dat_i: SOCM_PORT
333
+ spc_ref: dat_i
334
+ len: 32
335
+ :i6_wb_dat_o: SOCM_PORT
336
+ spc_ref: dat_o
337
+ len: 32
338
+ :i6_wb_ack_o: SOCM_PORT
339
+ spc_ref: ack
340
+ len: 1
341
+ :i6_wb_err_o: SOCM_PORT
342
+ spc_ref: err
343
+ len: 1
344
+ :i7: SOCM_IFC
345
+ name: wishbone_ma
346
+ dir: 0
347
+ id: wishbone_ma,b3
348
+ ports:
349
+ :i7_wb_clk_o: SOCM_PORT
350
+ spc_ref: clk
351
+ len: 1
352
+ :i7_wb_rst_o: SOCM_PORT
353
+ spc_ref: rst
354
+ len: 1
355
+ :i7_wb_cyc_i: SOCM_PORT
356
+ spc_ref: cyc
357
+ len: 1
358
+ :i7_wb_stb_i: SOCM_PORT
359
+ spc_ref: stb
360
+ len: 1
361
+ :i7_wb_adr_i: SOCM_PORT
362
+ spc_ref: adr
363
+ len: 32
364
+ :i7_wb_sel_i: SOCM_PORT
365
+ spc_ref: sel
366
+ len: 4
367
+ :i7_wb_we_i: SOCM_PORT
368
+ spc_ref: we
369
+ len: 1
370
+ :i7_wb_dat_i: SOCM_PORT
371
+ spc_ref: dat_i
372
+ len: 32
373
+ :i7_wb_dat_o: SOCM_PORT
374
+ spc_ref: dat_o
375
+ len: 32
376
+ :i7_wb_ack_o: SOCM_PORT
377
+ spc_ref: ack
378
+ len: 1
379
+ :i7_wb_err_o: SOCM_PORT
380
+ spc_ref: err
381
+ len: 1
382
+ :t0: SOCM_IFC
383
+ name: wishbone_sl
384
+ dir: 0
385
+ id: wishbone_sl,b3
386
+ ports:
387
+ :t0_wb_clk_o: SOCM_PORT
388
+ spc_ref: clk
389
+ len: 1
390
+ :t0_wb_rst_o: SOCM_PORT
391
+ spc_ref: rst
392
+ len: 1
393
+ :t0_wb_cyc_o: SOCM_PORT
394
+ spc_ref: cyc
395
+ len: 1
396
+ :t0_wb_stb_o: SOCM_PORT
397
+ spc_ref: stb
398
+ len: 1
399
+ :t0_wb_adr_o: SOCM_PORT
400
+ spc_ref: adr
401
+ len: 32
402
+ :t0_wb_sel_o: SOCM_PORT
403
+ spc_ref: sel
404
+ len: 4
405
+ :t0_wb_we_o: SOCM_PORT
406
+ spc_ref: we
407
+ len: 1
408
+ :t0_wb_dat_o: SOCM_PORT
409
+ spc_ref: dat_o
410
+ len: 32
411
+ :t0_wb_dat_i: SOCM_PORT
412
+ spc_ref: dat_i
413
+ len: 32
414
+ :t0_wb_ack_i: SOCM_PORT
415
+ spc_ref: ack
416
+ len: 1
417
+ :t0_wb_err_i: SOCM_PORT
418
+ spc_ref: err
419
+ len: 1
420
+ :t1: SOCM_IFC
421
+ name: wishbone_sl
422
+ dir: 0
423
+ id: wishbone_sl,b3
424
+ ports:
425
+ :t1_wb_clk_o: SOCM_PORT
426
+ spc_ref: clk
427
+ len: 1
428
+ :t1_wb_rst_o: SOCM_PORT
429
+ spc_ref: rst
430
+ len: 1
431
+ :t1_wb_cyc_o: SOCM_PORT
432
+ spc_ref: cyc
433
+ len: 1
434
+ :t1_wb_stb_o: SOCM_PORT
435
+ spc_ref: stb
436
+ len: 1
437
+ :t1_wb_adr_o: SOCM_PORT
438
+ spc_ref: adr
439
+ len: 32
440
+ :t1_wb_sel_o: SOCM_PORT
441
+ spc_ref: sel
442
+ len: 4
443
+ :t1_wb_we_o: SOCM_PORT
444
+ spc_ref: we
445
+ len: 1
446
+ :t1_wb_dat_o: SOCM_PORT
447
+ spc_ref: dat_o
448
+ len: 32
449
+ :t1_wb_dat_i: SOCM_PORT
450
+ spc_ref: dat_i
451
+ len: 32
452
+ :t1_wb_ack_i: SOCM_PORT
453
+ spc_ref: ack
454
+ len: 1
455
+ :t1_wb_err_i: SOCM_PORT
456
+ spc_ref: err
457
+ len: 1
458
+ :t2: SOCM_IFC
459
+ name: wishbone_sl
460
+ dir: 0
461
+ id: wishbone_sl,b3
462
+ ports:
463
+ :t2_wb_clk_o: SOCM_PORT
464
+ spc_ref: clk
465
+ len: 1
466
+ :t2_wb_rst_o: SOCM_PORT
467
+ spc_ref: rst
468
+ len: 1
469
+ :t2_wb_cyc_o: SOCM_PORT
470
+ spc_ref: cyc
471
+ len: 1
472
+ :t2_wb_stb_o: SOCM_PORT
473
+ spc_ref: stb
474
+ len: 1
475
+ :t2_wb_adr_o: SOCM_PORT
476
+ spc_ref: adr
477
+ len: 32
478
+ :t2_wb_sel_o: SOCM_PORT
479
+ spc_ref: sel
480
+ len: 4
481
+ :t2_wb_we_o: SOCM_PORT
482
+ spc_ref: we
483
+ len: 1
484
+ :t2_wb_dat_o: SOCM_PORT
485
+ spc_ref: dat_o
486
+ len: 32
487
+ :t2_wb_dat_i: SOCM_PORT
488
+ spc_ref: dat_i
489
+ len: 32
490
+ :t2_wb_ack_i: SOCM_PORT
491
+ spc_ref: ack
492
+ len: 1
493
+ :t2_wb_err_i: SOCM_PORT
494
+ spc_ref: err
495
+ len: 1
496
+ :t3: SOCM_IFC
497
+ name: wishbone_sl
498
+ dir: 0
499
+ id: wishbone_sl,b3
500
+ ports:
501
+ :t3_wb_clk_o: SOCM_PORT
502
+ spc_ref: clk
503
+ len: 1
504
+ :t3_wb_rst_o: SOCM_PORT
505
+ spc_ref: rst
506
+ len: 1
507
+ :t3_wb_cyc_o: SOCM_PORT
508
+ spc_ref: cyc
509
+ len: 1
510
+ :t3_wb_stb_o: SOCM_PORT
511
+ spc_ref: stb
512
+ len: 1
513
+ :t3_wb_adr_o: SOCM_PORT
514
+ spc_ref: adr
515
+ len: 32
516
+ :t3_wb_sel_o: SOCM_PORT
517
+ spc_ref: sel
518
+ len: 4
519
+ :t3_wb_we_o: SOCM_PORT
520
+ spc_ref: we
521
+ len: 1
522
+ :t3_wb_dat_o: SOCM_PORT
523
+ spc_ref: dat_o
524
+ len: 32
525
+ :t3_wb_dat_i: SOCM_PORT
526
+ spc_ref: dat_i
527
+ len: 32
528
+ :t3_wb_ack_i: SOCM_PORT
529
+ spc_ref: ack
530
+ len: 1
531
+ :t3_wb_err_i: SOCM_PORT
532
+ spc_ref: err
533
+ len: 1
534
+ :t4: SOCM_IFC
535
+ name: wishbone_sl
536
+ dir: 0
537
+ id: wishbone_sl,b3
538
+ ports:
539
+ :t4_wb_clk_o: SOCM_PORT
540
+ spc_ref: clk
541
+ len: 1
542
+ :t4_wb_rst_o: SOCM_PORT
543
+ spc_ref: rst
544
+ len: 1
545
+ :t4_wb_cyc_o: SOCM_PORT
546
+ spc_ref: cyc
547
+ len: 1
548
+ :t4_wb_stb_o: SOCM_PORT
549
+ spc_ref: stb
550
+ len: 1
551
+ :t4_wb_adr_o: SOCM_PORT
552
+ spc_ref: adr
553
+ len: 32
554
+ :t4_wb_sel_o: SOCM_PORT
555
+ spc_ref: sel
556
+ len: 4
557
+ :t4_wb_we_o: SOCM_PORT
558
+ spc_ref: we
559
+ len: 1
560
+ :t4_wb_dat_o: SOCM_PORT
561
+ spc_ref: dat_o
562
+ len: 32
563
+ :t4_wb_dat_i: SOCM_PORT
564
+ spc_ref: dat_i
565
+ len: 32
566
+ :t4_wb_ack_i: SOCM_PORT
567
+ spc_ref: ack
568
+ len: 1
569
+ :t4_wb_err_i: SOCM_PORT
570
+ spc_ref: err
571
+ len: 1
572
+ :t5: SOCM_IFC
573
+ name: wishbone_sl
574
+ dir: 0
575
+ id: wishbone_sl,b3
576
+ ports:
577
+ :t5_wb_clk_o: SOCM_PORT
578
+ spc_ref: clk
579
+ len: 1
580
+ :t5_wb_rst_o: SOCM_PORT
581
+ spc_ref: rst
582
+ len: 1
583
+ :t5_wb_cyc_o: SOCM_PORT
584
+ spc_ref: cyc
585
+ len: 1
586
+ :t5_wb_stb_o: SOCM_PORT
587
+ spc_ref: stb
588
+ len: 1
589
+ :t5_wb_adr_o: SOCM_PORT
590
+ spc_ref: adr
591
+ len: 32
592
+ :t5_wb_sel_o: SOCM_PORT
593
+ spc_ref: sel
594
+ len: 4
595
+ :t5_wb_we_o: SOCM_PORT
596
+ spc_ref: we
597
+ len: 1
598
+ :t5_wb_dat_o: SOCM_PORT
599
+ spc_ref: dat_o
600
+ len: 32
601
+ :t5_wb_dat_i: SOCM_PORT
602
+ spc_ref: dat_i
603
+ len: 32
604
+ :t5_wb_ack_i: SOCM_PORT
605
+ spc_ref: ack
606
+ len: 1
607
+ :t5_wb_err_i: SOCM_PORT
608
+ spc_ref: err
609
+ len: 1
610
+ :t6: SOCM_IFC
611
+ name: wishbone_sl
612
+ dir: 0
613
+ id: wishbone_sl,b3
614
+ ports:
615
+ :t6_wb_clk_o: SOCM_PORT
616
+ spc_ref: clk
617
+ len: 1
618
+ :t6_wb_rst_o: SOCM_PORT
619
+ spc_ref: rst
620
+ len: 1
621
+ :t6_wb_cyc_o: SOCM_PORT
622
+ spc_ref: cyc
623
+ len: 1
624
+ :t6_wb_stb_o: SOCM_PORT
625
+ spc_ref: stb
626
+ len: 1
627
+ :t6_wb_adr_o: SOCM_PORT
628
+ spc_ref: adr
629
+ len: 32
630
+ :t6_wb_sel_o: SOCM_PORT
631
+ spc_ref: sel
632
+ len: 4
633
+ :t6_wb_we_o: SOCM_PORT
634
+ spc_ref: we
635
+ len: 1
636
+ :t6_wb_dat_o: SOCM_PORT
637
+ spc_ref: dat_o
638
+ len: 32
639
+ :t6_wb_dat_i: SOCM_PORT
640
+ spc_ref: dat_i
641
+ len: 32
642
+ :t6_wb_ack_i: SOCM_PORT
643
+ spc_ref: ack
644
+ len: 1
645
+ :t6_wb_err_i: SOCM_PORT
646
+ spc_ref: err
647
+ len: 1
648
+ :t7: SOCM_IFC
649
+ name: wishbone_sl
650
+ dir: 0
651
+ id: wishbone_sl,b3
652
+ ports:
653
+ :t7_wb_clk_o: SOCM_PORT
654
+ spc_ref: clk
655
+ len: 1
656
+ :t7_wb_rst_o: SOCM_PORT
657
+ spc_ref: rst
658
+ len: 1
659
+ :t7_wb_cyc_o: SOCM_PORT
660
+ spc_ref: cyc
661
+ len: 1
662
+ :t7_wb_stb_o: SOCM_PORT
663
+ spc_ref: stb
664
+ len: 1
665
+ :t7_wb_adr_o: SOCM_PORT
666
+ spc_ref: adr
667
+ len: 32
668
+ :t7_wb_sel_o: SOCM_PORT
669
+ spc_ref: sel
670
+ len: 4
671
+ :t7_wb_we_o: SOCM_PORT
672
+ spc_ref: we
673
+ len: 1
674
+ :t7_wb_dat_o: SOCM_PORT
675
+ spc_ref: dat_o
676
+ len: 32
677
+ :t7_wb_dat_i: SOCM_PORT
678
+ spc_ref: dat_i
679
+ len: 32
680
+ :t7_wb_ack_i: SOCM_PORT
681
+ spc_ref: ack
682
+ len: 1
683
+ :t7_wb_err_i: SOCM_PORT
684
+ spc_ref: err
685
+ len: 1
686
+ :t8: SOCM_IFC
687
+ name: wishbone_sl
688
+ dir: 0
689
+ id: wishbone_sl,b3
690
+ ports:
691
+ :t8_wb_clk_o: SOCM_PORT
692
+ spc_ref: clk
693
+ len: 1
694
+ :t8_wb_rst_o: SOCM_PORT
695
+ spc_ref: rst
696
+ len: 1
697
+ :t8_wb_cyc_o: SOCM_PORT
698
+ spc_ref: cyc
699
+ len: 1
700
+ :t8_wb_stb_o: SOCM_PORT
701
+ spc_ref: stb
702
+ len: 1
703
+ :t8_wb_adr_o: SOCM_PORT
704
+ spc_ref: adr
705
+ len: 32
706
+ :t8_wb_sel_o: SOCM_PORT
707
+ spc_ref: sel
708
+ len: 4
709
+ :t8_wb_we_o: SOCM_PORT
710
+ spc_ref: we
711
+ len: 1
712
+ :t8_wb_dat_o: SOCM_PORT
713
+ spc_ref: dat_o
714
+ len: 32
715
+ :t8_wb_dat_i: SOCM_PORT
716
+ spc_ref: dat_i
717
+ len: 32
718
+ :t8_wb_ack_i: SOCM_PORT
719
+ spc_ref: ack
720
+ len: 1
721
+ :t8_wb_err_i: SOCM_PORT
722
+ spc_ref: err
723
+ len: 1
724
+
725
+
726
+
727
+
728
+ hdlfiles:
729
+ :minsoc_tc_top: SOCM_HDL_FILE
730
+ use_syn: true
731
+ use_sim: true
732
+ type: verilog
733
+ path: minsoc_tc_top.v