soc_maker 0.1.1
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- checksums.yaml +7 -0
- data/.gitignore +5 -0
- data/History.txt +4 -0
- data/LICENSE +678 -0
- data/README.rdoc +228 -0
- data/Rakefile +46 -0
- data/bin/soc_maker_cli +80 -0
- data/bin/soc_maker_parser +85 -0
- data/core_lib/cores/adv_debug_sys/01_adv_debug_sys.yaml +245 -0
- data/core_lib/cores/or1200_rel2/01_or1200.yaml +208 -0
- data/core_lib/cores/or1200_rel2/02_or1200_files.yaml +421 -0
- data/core_lib/cores/or1200_rel2/03_or1200_sparam.yaml +188 -0
- data/core_lib/cores/or1200_rel2/or1200_defines.v.in +1799 -0
- data/core_lib/cores/ram_wb/ram_wb.yaml +102 -0
- data/core_lib/cores/ram_wb/ram_wb_b3.v.in +259 -0
- data/core_lib/cores/uart16550/01_uart16550.yaml +99 -0
- data/core_lib/cores/uart16550/02_uart16550_files.yaml +70 -0
- data/core_lib/cores/wb_connect/minsoc_tc_top.v +1802 -0
- data/core_lib/cores/wb_connect/wb_connect.yaml +733 -0
- data/core_lib/inc.yaml +13 -0
- data/core_lib/interfaces/clk_rst/clk.yaml +9 -0
- data/core_lib/interfaces/clk_rst/rst.yaml +9 -0
- data/core_lib/interfaces/clk_rst/single.yaml +7 -0
- data/core_lib/interfaces/debug/debug.yaml +32 -0
- data/core_lib/interfaces/jtag/jtag.yaml +13 -0
- data/core_lib/interfaces/jtag/jtag_tap.yaml +22 -0
- data/core_lib/interfaces/power/or_power.yaml +25 -0
- data/core_lib/interfaces/uart/uart.yaml +21 -0
- data/core_lib/interfaces/wishbone/wishbone_ma_b3.yaml +54 -0
- data/core_lib/interfaces/wishbone/wishbone_sl_b3.yaml +51 -0
- data/doc/class_arch.uml +5113 -0
- data/doc/fig/hierarchical.svg +273 -0
- data/examples/or1200_test/or1200_test.cmd +78 -0
- data/examples/or1200_test/or1200_test.rb +136 -0
- data/examples/or1200_test/rtl/or1200_test_top.vhd +274 -0
- data/examples/or1200_test/rtl/s3astarter.ucf +10 -0
- data/examples/or1200_test/rtl/xilinx_internal_jtag.v +438 -0
- data/examples/or1200_test/rtl/xilinx_internal_jtag_options.v +12 -0
- data/examples/or1200_test/sw/README.txt +35 -0
- data/examples/or1200_test/sw/bin2vmem.c +159 -0
- data/examples/or1200_test/sw/board.h +24 -0
- data/examples/or1200_test/sw/compile.sh +18 -0
- data/examples/or1200_test/sw/except.S +152 -0
- data/examples/or1200_test/sw/int.c +79 -0
- data/examples/or1200_test/sw/int.h +14 -0
- data/examples/or1200_test/sw/interconnect.h +17 -0
- data/examples/or1200_test/sw/interrupts.c +14 -0
- data/examples/or1200_test/sw/main.c +16 -0
- data/examples/or1200_test/sw/or1200.h +454 -0
- data/examples/or1200_test/sw/orp.ld +60 -0
- data/examples/or1200_test/sw/reset.S +112 -0
- data/examples/or1200_test/sw/support.c +123 -0
- data/examples/or1200_test/sw/support.h +33 -0
- data/examples/or1200_test/sw/tick.c +30 -0
- data/examples/or1200_test/sw/tick.h +2 -0
- data/examples/or1200_test/sw/uart.c +136 -0
- data/examples/or1200_test/sw/uart.h +126 -0
- data/lib/soc_maker.rb +324 -0
- data/lib/soc_maker/cli.rb +544 -0
- data/lib/soc_maker/conf.rb +310 -0
- data/lib/soc_maker/core_def.rb +579 -0
- data/lib/soc_maker/core_inst.rb +305 -0
- data/lib/soc_maker/err.rb +211 -0
- data/lib/soc_maker/hdl_coder.rb +500 -0
- data/lib/soc_maker/hdl_file.rb +166 -0
- data/lib/soc_maker/hdl_parser.rb +431 -0
- data/lib/soc_maker/ifc_def.rb +193 -0
- data/lib/soc_maker/ifc_port.rb +133 -0
- data/lib/soc_maker/ifc_spc.rb +180 -0
- data/lib/soc_maker/lib.rb +289 -0
- data/lib/soc_maker/lib_inc.rb +109 -0
- data/lib/soc_maker/parameter.rb +149 -0
- data/lib/soc_maker/soc_def.rb +847 -0
- data/lib/soc_maker/sparameter.rb +289 -0
- data/lib/soc_maker/version.rb +8 -0
- data/lib/soc_maker/ypp.rb +130 -0
- data/soc_maker.gemspec +28 -0
- data/spec/cli_cmds1.txt +39 -0
- data/spec/cli_spec.rb +49 -0
- data/spec/conf_spec.rb +44 -0
- data/spec/core_def_spec.rb +503 -0
- data/spec/core_inst_spec.rb +169 -0
- data/spec/hdl_file_spec.rb +154 -0
- data/spec/hdl_parser_spec.rb +201 -0
- data/spec/ifc_def_spec.rb +121 -0
- data/spec/ifc_port_spec.rb +92 -0
- data/spec/ifc_spc_spec.rb +196 -0
- data/spec/lib_inc_spec.rb +99 -0
- data/spec/lib_spec.rb +209 -0
- data/spec/parameter_spec.rb +86 -0
- data/spec/soc_def_spec.rb +611 -0
- data/spec/soc_maker_spec.rb +7 -0
- data/spec/sparameter_spec.rb +182 -0
- data/spec/spec_helper.rb +78 -0
- data/spec/test_soc.yaml +105 -0
- data/spec/test_soc2.yaml +60 -0
- data/spec/test_soc_lib/cores/core_A_rel1/00_core_a.yaml +75 -0
- data/spec/test_soc_lib/cores/core_A_rel1/01_core_a.yaml +57 -0
- data/spec/test_soc_lib/cores/core_A_rel1/core_a.vhd +29 -0
- data/spec/test_soc_lib/cores/core_A_rel1/core_a_pkg.vhd.src +3 -0
- data/spec/test_soc_lib/cores/core_A_rel1/core_a_pkg2.vhd.src +4 -0
- data/spec/test_soc_lib/cores/core_A_rel1/core_a_pkg3.v.src +6 -0
- data/spec/test_soc_lib/cores/core_B_rel1/core_b.vhd +25 -0
- data/spec/test_soc_lib/cores/core_B_rel1/core_b.yaml +36 -0
- data/spec/test_soc_lib/cores/core_C_v1/core_C.vhd +57 -0
- data/spec/test_soc_lib/cores/core_C_v1/core_c.yaml +42 -0
- data/spec/test_soc_lib/cores/soc_A/soc_A.yaml +12 -0
- data/spec/test_soc_lib/cores/soc_maker_include.yaml +6 -0
- data/spec/test_soc_lib/ifcs/core_AB_ifc/bidir_ifc.yaml +19 -0
- data/spec/test_soc_lib/ifcs/core_AB_ifc/core_AB_ifc.yaml +15 -0
- data/spec/test_soc_lib/ifcs/core_AB_ifc/top_ifc.yaml +9 -0
- data/spec/test_soc_lib/soc_maker_include.yaml +4 -0
- data/spec/yaml_examples.rb +367 -0
- data/spec/ypp_spec.rb +156 -0
- data/test/test_soc_maker.rb +0 -0
- metadata +255 -0
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// Xilinx has a different HDL entity for the internal JTAG in each of these.
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// How thoughtful.
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//`define SPARTAN2
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//`define SPARTAN3 // This is also used for SPARTAN 3E devices
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`define SPARTAN3A
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//`define VIRTEX
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//`define VIRTEX2 // Also used for the VIRTEX 2P
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//`define VIRTEX4
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//`define VIRTEX5
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!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
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Please note: this software is taken from the
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minsoc project: http://www.minsoc.com and is just
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used for prove of concept.
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!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
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Prerequisites:
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- Synthesized FPGA design
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- Advanced debug system compiled
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and working (same revision than for HDL sources)
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- Spartan-3an starter kit
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Do the following steps to run the SW
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1. Programm FPGA with impact
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2. Compile sources
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>> bash ./compile.sh
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3. Open serial output, for example with `kermit`
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4. Run advanced debug bridge:
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>> PATH_TO_BRIDGE/adv_jtag_bridge -t -b /PATH_TO_/Xilinx/bsdl -x 1 xpc_usb
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The result should show a successful test and "JTAG bridge ready!"
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5. Run GDB:
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>>or32-elf-gdb uart.or32
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(gdb) target remote localhost:9999
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(gdb) load
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(gdb) set $pc=0x100
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(gdb) continue
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The serial output should show "Hello World."
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/*$$HEADER*/
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/******************************************************************************/
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/* */
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/* H E A D E R I N F O R M A T I O N */
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/* */
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/******************************************************************************/
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// Project Name : ORPSoC v2
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// File Name : bin2vmem.c
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// Prepared By : jb, jb@orsoc.se
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// Project Start : 2009-05-13
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/*$$COPYRIGHT NOTICE*/
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/******************************************************************************/
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/* */
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/* C O P Y R I G H T N O T I C E */
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/* */
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/******************************************************************************/
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/*
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This library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation;
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version 2.1 of the License, a copy of which is available from
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http://www.gnu.org/licenses/old-licenses/lgpl-2.1.txt.
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This library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with this library; if not, write to the Free Software
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Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/*$$DESCRIPTION*/
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/******************************************************************************/
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/* */
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/* D E S C R I P T I O N */
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/* */
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/******************************************************************************/
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//
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// Generates VMEM output to stdout from binary images.
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// Use with redirection like: ./bin2vmem app.bin > app.vmem
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// To change either the number of bytes per word or word per line, change
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// the following defines.
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// Currently output is WORD addressed, NOT byte addressed
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// eg: @00000000 00000000 00000000 00000000 00000000
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// @00000004 00000000 00000000 00000000 00000000
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// @00000008 00000000 00000000 00000000 00000000
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// @0000000c 00000000 00000000 00000000 00000000
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// etc..
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//
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#define WORDS_PER_LINE 4
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#define BYTES_PER_WORD 4
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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int main(int argc, char **argv)
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{
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FILE *fd;
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int c;
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int i = 0;
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int write_size_word=0; // Disabled by default
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int filename_index=1;
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unsigned int image_size;
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// Counters keeping track of what we've printed
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int current_addr = 0;
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int word_counter = 0;
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int byte_counter = 0;
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if(argc < 2) {
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fprintf(stderr,"\n\tInsufficient options.\n");
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fprintf(stderr,"\tPlease specify a binary file to convert to VMEM\n");
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fprintf(stderr,"\n\tbin2vmem - creates vmem output to stdout from bin\n");
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exit(1);
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}
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fd = fopen( argv[filename_index], "r" );
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if (fd == NULL) {
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fprintf(stderr,"failed to open input file: %s\n",argv[1]);
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exit(1);
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}
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fseek(fd, 0, SEEK_END);
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image_size = ftell(fd);
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fseek(fd,0,SEEK_SET);
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if (write_size_word)
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{
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// or1200 startup method of determining size of boot image we're copying by reading out
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// the very first word in flash is used. Determine the length of this file
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fseek(fd, 0, SEEK_END);
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image_size = ftell(fd);
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fseek(fd,0,SEEK_SET);
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// Now we should have the size of the file in bytes. Let's ensure it's a word multiple
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image_size+=3;
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image_size &= 0xfffffffc;
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// Sanity check on image size
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if (image_size < 8){
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fprintf(stderr, "Bad binary image. Size too small\n");
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return 1;
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}
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// Now write out the image size
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printf("@%8x", current_addr);
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printf("%8x", image_size);
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current_addr += WORDS_PER_LINE * BYTES_PER_WORD;
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}
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else
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{
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}
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// Fix for the current bootloader software! Skip the first 4 bytes of application data. Hopefully it's not important. 030509 -- jb
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//for(i=0;i<4;i++)
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// c=fgetc(fd);
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i=0;
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int starting_new_line = 1;
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// Now write out the binary data to VMEM format: @ADDRESSS XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
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while ((c = fgetc(fd)) != EOF) {
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if (starting_new_line)
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{
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// New line - print the current addr and then increment it
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printf("@%.8x", current_addr);
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//current_addr += WORDS_PER_LINE * BYTES_PER_WORD;
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current_addr += WORDS_PER_LINE;
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starting_new_line = 0;
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}
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if (byte_counter == 0)
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printf(" ");
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printf("%.2x", (unsigned int) c); // now print the actual char
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byte_counter++;
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if (byte_counter == BYTES_PER_WORD)
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{
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word_counter++;
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byte_counter=0;
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}
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if (word_counter == WORDS_PER_LINE)
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{
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printf("\n");
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word_counter = 0;
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starting_new_line = 1;
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}
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}
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return 0;
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}
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#ifndef _BOARD_H_
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#define _BOARD_H_
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#define MC_ENABLED 0
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#define IC_ENABLE 0
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#define IC_SIZE 8192
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#define DC_ENABLE 0
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#define DC_SIZE 8192
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#define IN_CLK 50000000
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#define STACK_SIZE 0x00100
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#define UART_BAUD_RATE 115200
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//#define ETH_MACADDR0 0x00
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//#define ETH_MACADDR1 0x12
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//#define ETH_MACADDR2 0x34
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//#define ETH_MACADDR3 0x56
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//#define ETH_MACADDR4 0x78
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//#define ETH_MACADDR5 0x9a
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#endif
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#!/bin/bash
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gcc -o bin2vmem bin2vmem.c
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or32-elf-gcc -Wall -mhard-mul -mhard-div -nostdlib -g -O0 -c -I./ int.c -o int.o
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or32-elf-gcc -Wall -mhard-mul -mhard-div -nostdlib -g -O0 -c -I./ support.c -o support.o
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or32-elf-gcc -Wall -mhard-mul -mhard-div -nostdlib -g -O0 -c -I./ main.c -o main.o
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or32-elf-gcc -Wall -mhard-mul -mhard-div -nostdlib -g -O0 -c -I./ uart.c -o uart.o
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or32-elf-gcc -Wall -mhard-mul -mhard-div -nostdlib -g -O0 -c -I./ tick.c -o tick.o
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or32-elf-gcc -Wall -mhard-mul -mhard-div -nostdlib -g -O0 -c -I./ interrupts.c -o interrupts.o
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or32-elf-gcc -Wall -mhard-mul -mhard-div -nostdlib -g -O0 -I./ -c -o except.o except.S
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or32-elf-gcc -Wall -mhard-mul -mhard-div -nostdlib -g -O0 -I./ -c -DIC=0 -DDC=0 -o reset.o reset.S
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or32-elf-ld -T orp.ld main.o uart.o support.o int.o reset.o except.o tick.o interrupts.o -o uart.or32
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or32-elf-objcopy -O binary uart.or32 uart.bin
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./bin2vmem uart.bin > uart.vmem
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#include "or1200.h"
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2
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+
|
3
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+
// Linked from 0x200, so subtract 0x200 from each .org
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4
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+
.section .vectors, "ax"
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5
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+
|
6
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+
/*
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7
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+
.org 0x100
|
8
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+
|
9
|
+
_reset:
|
10
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+
l.nop
|
11
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+
l.j _reset_except
|
12
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+
l.nop
|
13
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+
*/
|
14
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+
|
15
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+
/* This cannot be a regular function because it would waste the return register r9 of the interrupted procedure. */
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16
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+
/* Furthermore, if this would be a function and l.j handler would be outside of this, the return register set here would be use upon return of this function. */
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17
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+
/* However, the desired behavior is to finish the handler and let the return of the service routine simply restore the registers and return to the interrupted procedure. */
|
18
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+
#define intr_handler(handler) \
|
19
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+
l.nop ;\
|
20
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+
l.addi r1,r1,-244 /*free 29 words (29 x 4 = 112) + 4 because stack points to contained data (stack is r1)*/;\
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21
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+
/*plus 128 bytes not to mess with the previous frame pointer (32 register x 4 bytes = 128 bytes ) (required by C++ multiple threading) */;\
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22
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+
l.sw 0x18(r1),r9 /*save register r9(return addr) to stack*/;\
|
23
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+
l.jal store_regs /*save registers r3-r31 (except r9) to stack (r9 is changed here)*/;\
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24
|
+
l.nop ;\
|
25
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+
;\
|
26
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+
l.movhi r9,hi(end_except) /*set return addr to end_except instruction*/;\
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27
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+
l.ori r9,r9,lo(end_except)/*set return addr to end_except instruction*/;\
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28
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+
l.j CLABEL(handler) ;\
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29
|
+
l.nop
|
30
|
+
|
31
|
+
.org 0x000
|
32
|
+
_except_200:
|
33
|
+
intr_handler(buserr_except)
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34
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+
|
35
|
+
.org 0x100
|
36
|
+
_except_300:
|
37
|
+
intr_handler(dpf_except)
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38
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+
|
39
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+
.org 0x200
|
40
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+
_except_400:
|
41
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+
intr_handler(ipf_except)
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42
|
+
|
43
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+
.org 0x300
|
44
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+
_except_500:
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45
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+
intr_handler(tick_except)
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46
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+
|
47
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+
.org 0x400
|
48
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+
_except_600:
|
49
|
+
intr_handler(align_except)
|
50
|
+
|
51
|
+
.org 0x500
|
52
|
+
_except_700:
|
53
|
+
intr_handler(illegal_except)
|
54
|
+
|
55
|
+
.org 0x600
|
56
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+
_except_800:
|
57
|
+
intr_handler(ext_except)
|
58
|
+
|
59
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+
.org 0x700
|
60
|
+
_except_900:
|
61
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+
intr_handler(dtlbmiss_except)
|
62
|
+
|
63
|
+
.org 0x800
|
64
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+
_except_a00:
|
65
|
+
intr_handler(itlbmiss_except)
|
66
|
+
|
67
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+
.org 0x900
|
68
|
+
_except_b00:
|
69
|
+
intr_handler(range_except)
|
70
|
+
|
71
|
+
.org 0xa00
|
72
|
+
_except_c00:
|
73
|
+
intr_handler(syscall_except)
|
74
|
+
|
75
|
+
.org 0xb00
|
76
|
+
_except_d00:
|
77
|
+
intr_handler(res1_except)
|
78
|
+
|
79
|
+
.org 0xc00
|
80
|
+
_except_e00:
|
81
|
+
intr_handler(trap_except)
|
82
|
+
|
83
|
+
.org 0xd00
|
84
|
+
_except_f00:
|
85
|
+
intr_handler(res2_except)
|
86
|
+
|
87
|
+
store_regs: //save registers r3-r31 (except r9) to stack
|
88
|
+
l.sw 0x00(r1),r3
|
89
|
+
l.sw 0x04(r1),r4
|
90
|
+
l.sw 0x08(r1),r5
|
91
|
+
l.sw 0x0c(r1),r6
|
92
|
+
l.sw 0x10(r1),r7
|
93
|
+
l.sw 0x14(r1),r8
|
94
|
+
l.sw 0x1c(r1),r10
|
95
|
+
l.sw 0x20(r1),r11
|
96
|
+
l.sw 0x24(r1),r12
|
97
|
+
l.sw 0x28(r1),r13
|
98
|
+
l.sw 0x2c(r1),r14
|
99
|
+
l.sw 0x30(r1),r15
|
100
|
+
l.sw 0x34(r1),r16
|
101
|
+
l.sw 0x38(r1),r17
|
102
|
+
l.sw 0x3c(r1),r18
|
103
|
+
l.sw 0x40(r1),r19
|
104
|
+
l.sw 0x44(r1),r20
|
105
|
+
l.sw 0x48(r1),r21
|
106
|
+
l.sw 0x4c(r1),r22
|
107
|
+
l.sw 0x50(r1),r23
|
108
|
+
l.sw 0x54(r1),r24
|
109
|
+
l.sw 0x58(r1),r25
|
110
|
+
l.sw 0x5c(r1),r26
|
111
|
+
l.sw 0x60(r1),r27
|
112
|
+
l.sw 0x64(r1),r28
|
113
|
+
l.sw 0x68(r1),r29
|
114
|
+
l.sw 0x6c(r1),r30
|
115
|
+
l.sw 0x70(r1),r31
|
116
|
+
l.jr r9
|
117
|
+
l.nop
|
118
|
+
|
119
|
+
end_except: //load back registers from stack r3-r31
|
120
|
+
l.lwz r3,0x00(r1)
|
121
|
+
l.lwz r4,0x04(r1)
|
122
|
+
l.lwz r5,0x08(r1)
|
123
|
+
l.lwz r6,0x0c(r1)
|
124
|
+
l.lwz r7,0x10(r1)
|
125
|
+
l.lwz r8,0x14(r1)
|
126
|
+
l.lwz r9,0x18(r1)
|
127
|
+
l.lwz r10,0x1c(r1)
|
128
|
+
l.lwz r11,0x20(r1)
|
129
|
+
l.lwz r12,0x24(r1)
|
130
|
+
l.lwz r13,0x28(r1)
|
131
|
+
l.lwz r14,0x2c(r1)
|
132
|
+
l.lwz r15,0x30(r1)
|
133
|
+
l.lwz r16,0x34(r1)
|
134
|
+
l.lwz r17,0x38(r1)
|
135
|
+
l.lwz r18,0x3c(r1)
|
136
|
+
l.lwz r19,0x40(r1)
|
137
|
+
l.lwz r20,0x44(r1)
|
138
|
+
l.lwz r21,0x48(r1)
|
139
|
+
l.lwz r22,0x4c(r1)
|
140
|
+
l.lwz r23,0x50(r1)
|
141
|
+
l.lwz r24,0x54(r1)
|
142
|
+
l.lwz r25,0x58(r1)
|
143
|
+
l.lwz r26,0x5c(r1)
|
144
|
+
l.lwz r27,0x60(r1)
|
145
|
+
l.lwz r28,0x64(r1)
|
146
|
+
l.lwz r29,0x68(r1)
|
147
|
+
l.lwz r30,0x6c(r1)
|
148
|
+
l.lwz r31,0x70(r1)
|
149
|
+
l.addi r1,r1,244 //free stack places
|
150
|
+
l.rfe //recover SR register and prior PC (jumps back to program)
|
151
|
+
l.nop
|
152
|
+
|
@@ -0,0 +1,79 @@
|
|
1
|
+
/* This file is part of test microkernel for OpenRISC 1000. */
|
2
|
+
/* (C) 2001 Simon Srot, srot@opencores.org */
|
3
|
+
|
4
|
+
#include "support.h"
|
5
|
+
#include "or1200.h"
|
6
|
+
#include "int.h"
|
7
|
+
|
8
|
+
/* Interrupt handlers table */
|
9
|
+
struct ihnd int_handlers[MAX_INT_HANDLERS];
|
10
|
+
|
11
|
+
/* Initialize routine */
|
12
|
+
int int_init()
|
13
|
+
{
|
14
|
+
int i;
|
15
|
+
|
16
|
+
for(i = 0; i < MAX_INT_HANDLERS; i++) {
|
17
|
+
int_handlers[i].handler = 0;
|
18
|
+
int_handlers[i].arg = 0;
|
19
|
+
}
|
20
|
+
mtspr(SPR_PICMR, 0x00000000);
|
21
|
+
|
22
|
+
//set OR1200 to accept exceptions
|
23
|
+
mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_IEE);
|
24
|
+
|
25
|
+
return 0;
|
26
|
+
}
|
27
|
+
|
28
|
+
/* Add interrupt handler */
|
29
|
+
int int_add(unsigned long vect, void (* handler)(void *), void *arg)
|
30
|
+
{
|
31
|
+
if(vect >= MAX_INT_HANDLERS)
|
32
|
+
return -1;
|
33
|
+
|
34
|
+
int_handlers[vect].handler = handler;
|
35
|
+
int_handlers[vect].arg = arg;
|
36
|
+
|
37
|
+
mtspr(SPR_PICMR, mfspr(SPR_PICMR) | (0x00000001L << vect));
|
38
|
+
|
39
|
+
return 0;
|
40
|
+
}
|
41
|
+
|
42
|
+
/* Disable interrupt */
|
43
|
+
int int_disable(unsigned long vect)
|
44
|
+
{
|
45
|
+
if(vect >= MAX_INT_HANDLERS)
|
46
|
+
return -1;
|
47
|
+
|
48
|
+
mtspr(SPR_PICMR, mfspr(SPR_PICMR) & ~(0x00000001L << vect));
|
49
|
+
|
50
|
+
return 0;
|
51
|
+
}
|
52
|
+
|
53
|
+
/* Enable interrupt */
|
54
|
+
int int_enable(unsigned long vect)
|
55
|
+
{
|
56
|
+
if(vect >= MAX_INT_HANDLERS)
|
57
|
+
return -1;
|
58
|
+
|
59
|
+
mtspr(SPR_PICMR, mfspr(SPR_PICMR) | (0x00000001L << vect));
|
60
|
+
|
61
|
+
return 0;
|
62
|
+
}
|
63
|
+
|
64
|
+
/* Main interrupt handler */
|
65
|
+
void int_main()
|
66
|
+
{
|
67
|
+
unsigned long picsr = mfspr(SPR_PICSR); //process only the interrupts asserted at signal catch, ignore all during process
|
68
|
+
unsigned long i = 0;
|
69
|
+
|
70
|
+
while(i < 32) {
|
71
|
+
if((picsr & (0x01L << i)) && (int_handlers[i].handler != 0)) {
|
72
|
+
(*int_handlers[i].handler)(int_handlers[i].arg);
|
73
|
+
}
|
74
|
+
i++;
|
75
|
+
}
|
76
|
+
|
77
|
+
mtspr(SPR_PICSR, 0); //clear interrupt status: all modules have level interrupts, which have to be cleared by software,
|
78
|
+
} //thus this is safe, since non processed interrupts will get re-asserted soon enough
|
79
|
+
|