soc_maker 0.1.1
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- checksums.yaml +7 -0
- data/.gitignore +5 -0
- data/History.txt +4 -0
- data/LICENSE +678 -0
- data/README.rdoc +228 -0
- data/Rakefile +46 -0
- data/bin/soc_maker_cli +80 -0
- data/bin/soc_maker_parser +85 -0
- data/core_lib/cores/adv_debug_sys/01_adv_debug_sys.yaml +245 -0
- data/core_lib/cores/or1200_rel2/01_or1200.yaml +208 -0
- data/core_lib/cores/or1200_rel2/02_or1200_files.yaml +421 -0
- data/core_lib/cores/or1200_rel2/03_or1200_sparam.yaml +188 -0
- data/core_lib/cores/or1200_rel2/or1200_defines.v.in +1799 -0
- data/core_lib/cores/ram_wb/ram_wb.yaml +102 -0
- data/core_lib/cores/ram_wb/ram_wb_b3.v.in +259 -0
- data/core_lib/cores/uart16550/01_uart16550.yaml +99 -0
- data/core_lib/cores/uart16550/02_uart16550_files.yaml +70 -0
- data/core_lib/cores/wb_connect/minsoc_tc_top.v +1802 -0
- data/core_lib/cores/wb_connect/wb_connect.yaml +733 -0
- data/core_lib/inc.yaml +13 -0
- data/core_lib/interfaces/clk_rst/clk.yaml +9 -0
- data/core_lib/interfaces/clk_rst/rst.yaml +9 -0
- data/core_lib/interfaces/clk_rst/single.yaml +7 -0
- data/core_lib/interfaces/debug/debug.yaml +32 -0
- data/core_lib/interfaces/jtag/jtag.yaml +13 -0
- data/core_lib/interfaces/jtag/jtag_tap.yaml +22 -0
- data/core_lib/interfaces/power/or_power.yaml +25 -0
- data/core_lib/interfaces/uart/uart.yaml +21 -0
- data/core_lib/interfaces/wishbone/wishbone_ma_b3.yaml +54 -0
- data/core_lib/interfaces/wishbone/wishbone_sl_b3.yaml +51 -0
- data/doc/class_arch.uml +5113 -0
- data/doc/fig/hierarchical.svg +273 -0
- data/examples/or1200_test/or1200_test.cmd +78 -0
- data/examples/or1200_test/or1200_test.rb +136 -0
- data/examples/or1200_test/rtl/or1200_test_top.vhd +274 -0
- data/examples/or1200_test/rtl/s3astarter.ucf +10 -0
- data/examples/or1200_test/rtl/xilinx_internal_jtag.v +438 -0
- data/examples/or1200_test/rtl/xilinx_internal_jtag_options.v +12 -0
- data/examples/or1200_test/sw/README.txt +35 -0
- data/examples/or1200_test/sw/bin2vmem.c +159 -0
- data/examples/or1200_test/sw/board.h +24 -0
- data/examples/or1200_test/sw/compile.sh +18 -0
- data/examples/or1200_test/sw/except.S +152 -0
- data/examples/or1200_test/sw/int.c +79 -0
- data/examples/or1200_test/sw/int.h +14 -0
- data/examples/or1200_test/sw/interconnect.h +17 -0
- data/examples/or1200_test/sw/interrupts.c +14 -0
- data/examples/or1200_test/sw/main.c +16 -0
- data/examples/or1200_test/sw/or1200.h +454 -0
- data/examples/or1200_test/sw/orp.ld +60 -0
- data/examples/or1200_test/sw/reset.S +112 -0
- data/examples/or1200_test/sw/support.c +123 -0
- data/examples/or1200_test/sw/support.h +33 -0
- data/examples/or1200_test/sw/tick.c +30 -0
- data/examples/or1200_test/sw/tick.h +2 -0
- data/examples/or1200_test/sw/uart.c +136 -0
- data/examples/or1200_test/sw/uart.h +126 -0
- data/lib/soc_maker.rb +324 -0
- data/lib/soc_maker/cli.rb +544 -0
- data/lib/soc_maker/conf.rb +310 -0
- data/lib/soc_maker/core_def.rb +579 -0
- data/lib/soc_maker/core_inst.rb +305 -0
- data/lib/soc_maker/err.rb +211 -0
- data/lib/soc_maker/hdl_coder.rb +500 -0
- data/lib/soc_maker/hdl_file.rb +166 -0
- data/lib/soc_maker/hdl_parser.rb +431 -0
- data/lib/soc_maker/ifc_def.rb +193 -0
- data/lib/soc_maker/ifc_port.rb +133 -0
- data/lib/soc_maker/ifc_spc.rb +180 -0
- data/lib/soc_maker/lib.rb +289 -0
- data/lib/soc_maker/lib_inc.rb +109 -0
- data/lib/soc_maker/parameter.rb +149 -0
- data/lib/soc_maker/soc_def.rb +847 -0
- data/lib/soc_maker/sparameter.rb +289 -0
- data/lib/soc_maker/version.rb +8 -0
- data/lib/soc_maker/ypp.rb +130 -0
- data/soc_maker.gemspec +28 -0
- data/spec/cli_cmds1.txt +39 -0
- data/spec/cli_spec.rb +49 -0
- data/spec/conf_spec.rb +44 -0
- data/spec/core_def_spec.rb +503 -0
- data/spec/core_inst_spec.rb +169 -0
- data/spec/hdl_file_spec.rb +154 -0
- data/spec/hdl_parser_spec.rb +201 -0
- data/spec/ifc_def_spec.rb +121 -0
- data/spec/ifc_port_spec.rb +92 -0
- data/spec/ifc_spc_spec.rb +196 -0
- data/spec/lib_inc_spec.rb +99 -0
- data/spec/lib_spec.rb +209 -0
- data/spec/parameter_spec.rb +86 -0
- data/spec/soc_def_spec.rb +611 -0
- data/spec/soc_maker_spec.rb +7 -0
- data/spec/sparameter_spec.rb +182 -0
- data/spec/spec_helper.rb +78 -0
- data/spec/test_soc.yaml +105 -0
- data/spec/test_soc2.yaml +60 -0
- data/spec/test_soc_lib/cores/core_A_rel1/00_core_a.yaml +75 -0
- data/spec/test_soc_lib/cores/core_A_rel1/01_core_a.yaml +57 -0
- data/spec/test_soc_lib/cores/core_A_rel1/core_a.vhd +29 -0
- data/spec/test_soc_lib/cores/core_A_rel1/core_a_pkg.vhd.src +3 -0
- data/spec/test_soc_lib/cores/core_A_rel1/core_a_pkg2.vhd.src +4 -0
- data/spec/test_soc_lib/cores/core_A_rel1/core_a_pkg3.v.src +6 -0
- data/spec/test_soc_lib/cores/core_B_rel1/core_b.vhd +25 -0
- data/spec/test_soc_lib/cores/core_B_rel1/core_b.yaml +36 -0
- data/spec/test_soc_lib/cores/core_C_v1/core_C.vhd +57 -0
- data/spec/test_soc_lib/cores/core_C_v1/core_c.yaml +42 -0
- data/spec/test_soc_lib/cores/soc_A/soc_A.yaml +12 -0
- data/spec/test_soc_lib/cores/soc_maker_include.yaml +6 -0
- data/spec/test_soc_lib/ifcs/core_AB_ifc/bidir_ifc.yaml +19 -0
- data/spec/test_soc_lib/ifcs/core_AB_ifc/core_AB_ifc.yaml +15 -0
- data/spec/test_soc_lib/ifcs/core_AB_ifc/top_ifc.yaml +9 -0
- data/spec/test_soc_lib/soc_maker_include.yaml +4 -0
- data/spec/yaml_examples.rb +367 -0
- data/spec/ypp_spec.rb +156 -0
- data/test/test_soc_maker.rb +0 -0
- metadata +255 -0
@@ -0,0 +1,60 @@
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MEMORY
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{
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reset : ORIGIN = 0x00000000, LENGTH = 0x00000200
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vectors : ORIGIN = 0x00000200, LENGTH = 0x00001000
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ram : ORIGIN = 0x00001200, LENGTH = 0x00006E00 /*0x8000 total*/
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}
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SECTIONS
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{
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.reset :
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{
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*(.reset)
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} > reset
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.vectors :
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{
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_vec_start = .;
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*(.vectors)
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_vec_end = .;
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} > vectors
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.text :
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{
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*(.text)
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} > ram
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.rodata :
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{
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*(.rodata)
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*(.rodata.*)
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} > ram
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.icm :
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{
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_icm_start = .;
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*(.icm)
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_icm_end = .;
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} > ram
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.data :
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{
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_dst_beg = .;
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*(.data)
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_dst_end = .;
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} > ram
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.bss :
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{
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*(.bss)
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} > ram
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.stack (NOLOAD) :
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{
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*(.stack)
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_src_addr = .;
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} > ram
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}
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/* Support file for c based tests */
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#include "or1200.h"
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#include <board.h>
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.section .stack
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.space STACK_SIZE
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_stack:
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.section .reset, "ax"
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.org 0x100
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_reset_vector:
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l.nop
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l.nop
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l.addi r2,r0,0x0
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l.addi r3,r0,0x0
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l.addi r4,r0,0x0
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l.addi r5,r0,0x0
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l.addi r6,r0,0x0
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l.addi r7,r0,0x0
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l.addi r8,r0,0x0
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l.addi r9,r0,0x0
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l.addi r10,r0,0x0
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l.addi r11,r0,0x0
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l.addi r12,r0,0x0
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l.addi r13,r0,0x0
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l.addi r14,r0,0x0
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l.addi r15,r0,0x0
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l.addi r16,r0,0x0
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l.addi r17,r0,0x0
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l.addi r18,r0,0x0
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l.addi r19,r0,0x0
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l.addi r20,r0,0x0
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l.addi r21,r0,0x0
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l.addi r22,r0,0x0
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l.addi r23,r0,0x0
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l.addi r24,r0,0x0
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l.addi r25,r0,0x0
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l.addi r26,r0,0x0
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l.addi r27,r0,0x0
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l.addi r28,r0,0x0
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l.addi r29,r0,0x0
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l.addi r30,r0,0x0
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l.addi r31,r0,0x0
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/*
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l.movhi r3,hi(MC_BASE_ADDR)
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l.ori r3,r3,MC_BA_MASK
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l.addi r5,r0,0x00
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l.sw 0(r3),r5
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*/
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l.movhi r3,hi(_start)
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l.ori r3,r3,lo(_start)
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l.jr r3
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l.nop
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.section .text
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_start:
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.if IC | DC
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/* Flush IC and/or DC */
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l.addi r10,r0,0
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l.addi r11,r0,0
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l.addi r12,r0,0
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.if IC
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l.addi r11,r0,IC_SIZE
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.endif
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.if DC
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l.addi r12,r0,DC_SIZE
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.endif
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l.sfleu r12,r11
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l.bf loop
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l.nop
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l.add r11,r0,r12
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loop:
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.if IC
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l.mtspr r0,r10,SPR_ICBIR
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.endif
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.if DC
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l.mtspr r0,r10,SPR_DCBIR
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.endif
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l.sfne r10,r11
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l.bf loop
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l.addi r10,r10,16
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/* Enable IC and/or DC */
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l.addi r10,r0,(SPR_SR_SM)
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.if IC
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l.ori r10,r10,(SPR_SR_ICE)
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.endif
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.if DC
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l.ori r10,r10,(SPR_SR_DCE)
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.endif
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l.mtspr r0,r10,SPR_SR
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l.nop
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l.nop
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l.nop
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l.nop
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l.nop
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.endif
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/* Set stack pointer */
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l.movhi r1,hi(_stack)
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l.ori r1,r1,lo(_stack)
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/* Jump to main */
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l.movhi r2,hi(CLABEL(reset))
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l.ori r2,r2,lo(CLABEL(reset))
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l.jr r2
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l.nop
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/* Support */
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#ifndef OR32
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#include <sys/time.h>
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#endif
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#include "or1200.h"
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#include "support.h"
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#include "int.h"
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#ifdef UART_PRINTF
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#include <uart.h>
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#endif
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#if OR32
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void int_main();
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void ext_except()
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{
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int_main();
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}
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/* Start function, called by reset exception handler. */
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void reset ()
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{
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int i = main();
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or32_exit (i);
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}
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/* return value by making a syscall */
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void or32_exit (int i)
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{
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asm("l.add r3,r0,%0": : "r" (i));
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asm("l.nop %0": :"K" (NOP_EXIT));
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while (1);
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}
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#ifdef UART_PRINTF
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static int uart_init_done = 0;
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#define PRINTFBUFFER_SIZE 512
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char PRINTFBUFFER[PRINTFBUFFER_SIZE]; // Declare a global printf buffer
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void minsoc_printf(const char *fmt, ...)
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{
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// init uart if not done already
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if (!uart_init_done)
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{
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uart_init();
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uart_init_done = 1;
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}
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va_list args;
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va_start(args, fmt);
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//int str_l = vsnprintf(PRINTFBUFFER, PRINTFBUFFER_SIZE, fmt, args);
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int str_l = vfnprintf(PRINTFBUFFER, PRINTFBUFFER_SIZE, fmt, args);
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if (!str_l) return; // no length string - just return
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int c=0;
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// now print each char via the UART
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while (c < str_l)
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uart_putc(PRINTFBUFFER[c++]);
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va_end(args);
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}
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#else
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/* activate printf support in simulator */
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void minsoc_printf(const char *fmt, ...)
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{
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va_list args;
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va_start(args, fmt);
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__asm__ __volatile__ (" l.addi\tr3,%1,0\n \
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l.addi\tr4,%2,0\n \
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l.nop %0": :"K" (NOP_PRINTF), "r" (fmt), "r" (args));
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}
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#endif
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/* print long */
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void report(unsigned long value)
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{
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asm("l.addi\tr3,%0,0": :"r" (value));
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asm("l.nop %0": :"K" (NOP_REPORT));
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}
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/* just to satisfy linker */
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void __main()
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{
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}
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/* start_TIMER */
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void start_timer(int x)
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{
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}
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/* For writing into SPR. */
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void mtspr(unsigned long spr, unsigned long value)
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{
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+
asm("l.mtspr\t\t%0,%1,0": : "r" (spr), "r" (value));
|
107
|
+
}
|
108
|
+
|
109
|
+
/* For reading SPR. */
|
110
|
+
unsigned long mfspr(unsigned long spr)
|
111
|
+
{
|
112
|
+
unsigned long value;
|
113
|
+
asm("l.mfspr\t\t%0,%1,0" : "=r" (value) : "r" (spr));
|
114
|
+
return value;
|
115
|
+
}
|
116
|
+
|
117
|
+
#else
|
118
|
+
void report(unsigned long value)
|
119
|
+
{
|
120
|
+
printf("report(0x%x);\n", (unsigned) value);
|
121
|
+
}
|
122
|
+
|
123
|
+
#endif
|
@@ -0,0 +1,33 @@
|
|
1
|
+
/* Support file for or32 tests. This file should is included
|
2
|
+
in each test. It calls main() function and add support for
|
3
|
+
basic functions */
|
4
|
+
|
5
|
+
#ifndef SUPPORT_H
|
6
|
+
#define SUPPORT_H
|
7
|
+
|
8
|
+
#include <stdarg.h>
|
9
|
+
#include <stddef.h>
|
10
|
+
#include <limits.h>
|
11
|
+
|
12
|
+
/* Register access macros */
|
13
|
+
#define REG8(add) *((volatile unsigned char *)(add))
|
14
|
+
#define REG16(add) *((volatile unsigned short *)(add))
|
15
|
+
#define REG32(add) *((volatile unsigned long *)(add))
|
16
|
+
|
17
|
+
/* For writing into SPR. */
|
18
|
+
void mtspr(unsigned long spr, unsigned long value);
|
19
|
+
|
20
|
+
/* For reading SPR. */
|
21
|
+
unsigned long mfspr(unsigned long spr);
|
22
|
+
|
23
|
+
/* Function to be called at entry point - not defined here. */
|
24
|
+
int main ();
|
25
|
+
|
26
|
+
/* Prints out a value */
|
27
|
+
void report(unsigned long value);
|
28
|
+
|
29
|
+
/* return value by making a syscall */
|
30
|
+
extern void or32_exit (int i) __attribute__ ((__noreturn__));
|
31
|
+
|
32
|
+
|
33
|
+
#endif /* SUPPORT_H */
|
@@ -0,0 +1,30 @@
|
|
1
|
+
#include "or1200.h"
|
2
|
+
#include "support.h"
|
3
|
+
#include "tick.h"
|
4
|
+
|
5
|
+
int tick_int;
|
6
|
+
|
7
|
+
void tick_ack(void)
|
8
|
+
{
|
9
|
+
tick_int--;
|
10
|
+
}
|
11
|
+
|
12
|
+
void tick_init(void)
|
13
|
+
{
|
14
|
+
mtspr(SPR_TTMR, 25000000 & SPR_TTMR_PERIOD); //1s
|
15
|
+
//mtspr(SPR_TTMR, 125000 & SPR_TTMR_PERIOD); //5ms
|
16
|
+
|
17
|
+
mtspr(SPR_TTMR, mfspr(SPR_TTMR) | SPR_TTMR_RT | SPR_TTMR_IE); //restart after match, enable interrupt
|
18
|
+
mtspr(SPR_TTMR, mfspr(SPR_TTMR) & ~(SPR_TTMR_IP)); //clears interrupt
|
19
|
+
|
20
|
+
//set OR1200 to accept exceptions
|
21
|
+
mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_TEE);
|
22
|
+
|
23
|
+
tick_int = 0;
|
24
|
+
}
|
25
|
+
|
26
|
+
void tick_except(void)
|
27
|
+
{
|
28
|
+
tick_int++;
|
29
|
+
mtspr(SPR_TTMR, mfspr(SPR_TTMR) & ~(SPR_TTMR_IP)); //clears interrupt
|
30
|
+
}
|
@@ -0,0 +1,136 @@
|
|
1
|
+
#include <board.h>
|
2
|
+
#include <support.h>
|
3
|
+
#include "uart.h"
|
4
|
+
|
5
|
+
#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
|
6
|
+
|
7
|
+
#define WAIT_FOR_XMITR \
|
8
|
+
do { \
|
9
|
+
lsr = REG8(uart_base + UART_LSR); \
|
10
|
+
} while ((lsr & BOTH_EMPTY) != BOTH_EMPTY)
|
11
|
+
|
12
|
+
#define WAIT_FOR_THRE \
|
13
|
+
do { \
|
14
|
+
lsr = REG8(uart_base + UART_LSR); \
|
15
|
+
} while ((lsr & UART_LSR_THRE) != UART_LSR_THRE)
|
16
|
+
|
17
|
+
#define CHECK_FOR_CHAR (REG8(uart_base + UART_LSR) & UART_LSR_DR)
|
18
|
+
|
19
|
+
#define WAIT_FOR_CHAR \
|
20
|
+
do { \
|
21
|
+
lsr = REG8(uart_base + UART_LSR); \
|
22
|
+
} while ((lsr & UART_LSR_DR) != UART_LSR_DR)
|
23
|
+
|
24
|
+
#define UART_TX_BUFF_LEN 32
|
25
|
+
#define UART_TX_BUFF_MASK (UART_TX_BUFF_LEN -1)
|
26
|
+
|
27
|
+
static unsigned long uart_base = 0;
|
28
|
+
|
29
|
+
char tx_buff[UART_TX_BUFF_LEN];
|
30
|
+
volatile int tx_level, rx_level;
|
31
|
+
|
32
|
+
void uart_init(unsigned long base)
|
33
|
+
{
|
34
|
+
int divisor;
|
35
|
+
uart_base = base;
|
36
|
+
/* Reset receiver and transmiter */
|
37
|
+
/* Set RX interrupt for each byte */
|
38
|
+
REG8(uart_base + UART_FCR) = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT | UART_FCR_TRIGGER_1;
|
39
|
+
|
40
|
+
/* Enable RX interrupt */
|
41
|
+
REG8(uart_base + UART_IER) = UART_IER_RDI | UART_IER_THRI;
|
42
|
+
|
43
|
+
/* Set 8 bit char, 1 stop bit, no parity */
|
44
|
+
REG8(uart_base + UART_LCR) = UART_LCR_WLEN8 & ~(UART_LCR_STOP | UART_LCR_PARITY);
|
45
|
+
|
46
|
+
/* Set baud rate */
|
47
|
+
divisor = IN_CLK/(16 * UART_BAUD_RATE);
|
48
|
+
REG8(uart_base + UART_LCR) |= UART_LCR_DLAB;
|
49
|
+
REG8(uart_base + UART_DLM) = (divisor >> 8) & 0x000000ff;
|
50
|
+
REG8(uart_base + UART_DLL) = divisor & 0x000000ff;
|
51
|
+
REG8(uart_base + UART_LCR) &= ~(UART_LCR_DLAB);
|
52
|
+
|
53
|
+
return;
|
54
|
+
}
|
55
|
+
|
56
|
+
void uart_putc(char c)
|
57
|
+
{
|
58
|
+
unsigned char lsr;
|
59
|
+
|
60
|
+
WAIT_FOR_THRE;
|
61
|
+
REG8(uart_base + UART_TX) = c;
|
62
|
+
WAIT_FOR_XMITR;
|
63
|
+
}
|
64
|
+
|
65
|
+
|
66
|
+
|
67
|
+
char uart_getc()
|
68
|
+
{
|
69
|
+
char c;
|
70
|
+
c = REG8(uart_base + UART_RX);
|
71
|
+
return c;
|
72
|
+
}
|
73
|
+
|
74
|
+
|
75
|
+
void uart_interrupt()
|
76
|
+
{
|
77
|
+
char lala;
|
78
|
+
unsigned char interrupt_id;
|
79
|
+
interrupt_id = REG8(uart_base + UART_IIR);
|
80
|
+
if ( interrupt_id & UART_IIR_RDI )
|
81
|
+
{
|
82
|
+
lala = uart_getc();
|
83
|
+
uart_putc(lala+1);
|
84
|
+
}
|
85
|
+
|
86
|
+
}
|
87
|
+
|
88
|
+
void uart_print_str(char *p)
|
89
|
+
{
|
90
|
+
while(*p != 0) {
|
91
|
+
uart_putc(*p);
|
92
|
+
p++;
|
93
|
+
}
|
94
|
+
}
|
95
|
+
|
96
|
+
void uart_print_long(unsigned long ul)
|
97
|
+
{
|
98
|
+
int i;
|
99
|
+
char c;
|
100
|
+
|
101
|
+
|
102
|
+
uart_print_str("0x");
|
103
|
+
for(i=0; i<8; i++) {
|
104
|
+
|
105
|
+
c = (char) (ul>>((7-i)*4)) & 0xf;
|
106
|
+
if(c >= 0x0 && c<=0x9)
|
107
|
+
c += '0';
|
108
|
+
else
|
109
|
+
c += 'a' - 10;
|
110
|
+
uart_putc(c);
|
111
|
+
}
|
112
|
+
|
113
|
+
}
|
114
|
+
|
115
|
+
void uart_print_short(unsigned long ul)
|
116
|
+
{
|
117
|
+
int i;
|
118
|
+
char c;
|
119
|
+
char flag=0;
|
120
|
+
|
121
|
+
|
122
|
+
uart_print_str("0x");
|
123
|
+
for(i=0; i<8; i++) {
|
124
|
+
|
125
|
+
c = (char) (ul>>((7-i)*4)) & 0xf;
|
126
|
+
if(c >= 0x0 && c<=0x9)
|
127
|
+
c += '0';
|
128
|
+
else
|
129
|
+
c += 'a' - 10;
|
130
|
+
if ((c != '0') || (i==7))
|
131
|
+
flag=1;
|
132
|
+
if(flag)
|
133
|
+
uart_putc(c);
|
134
|
+
}
|
135
|
+
|
136
|
+
}
|