soc_maker 0.1.1

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Files changed (116) hide show
  1. checksums.yaml +7 -0
  2. data/.gitignore +5 -0
  3. data/History.txt +4 -0
  4. data/LICENSE +678 -0
  5. data/README.rdoc +228 -0
  6. data/Rakefile +46 -0
  7. data/bin/soc_maker_cli +80 -0
  8. data/bin/soc_maker_parser +85 -0
  9. data/core_lib/cores/adv_debug_sys/01_adv_debug_sys.yaml +245 -0
  10. data/core_lib/cores/or1200_rel2/01_or1200.yaml +208 -0
  11. data/core_lib/cores/or1200_rel2/02_or1200_files.yaml +421 -0
  12. data/core_lib/cores/or1200_rel2/03_or1200_sparam.yaml +188 -0
  13. data/core_lib/cores/or1200_rel2/or1200_defines.v.in +1799 -0
  14. data/core_lib/cores/ram_wb/ram_wb.yaml +102 -0
  15. data/core_lib/cores/ram_wb/ram_wb_b3.v.in +259 -0
  16. data/core_lib/cores/uart16550/01_uart16550.yaml +99 -0
  17. data/core_lib/cores/uart16550/02_uart16550_files.yaml +70 -0
  18. data/core_lib/cores/wb_connect/minsoc_tc_top.v +1802 -0
  19. data/core_lib/cores/wb_connect/wb_connect.yaml +733 -0
  20. data/core_lib/inc.yaml +13 -0
  21. data/core_lib/interfaces/clk_rst/clk.yaml +9 -0
  22. data/core_lib/interfaces/clk_rst/rst.yaml +9 -0
  23. data/core_lib/interfaces/clk_rst/single.yaml +7 -0
  24. data/core_lib/interfaces/debug/debug.yaml +32 -0
  25. data/core_lib/interfaces/jtag/jtag.yaml +13 -0
  26. data/core_lib/interfaces/jtag/jtag_tap.yaml +22 -0
  27. data/core_lib/interfaces/power/or_power.yaml +25 -0
  28. data/core_lib/interfaces/uart/uart.yaml +21 -0
  29. data/core_lib/interfaces/wishbone/wishbone_ma_b3.yaml +54 -0
  30. data/core_lib/interfaces/wishbone/wishbone_sl_b3.yaml +51 -0
  31. data/doc/class_arch.uml +5113 -0
  32. data/doc/fig/hierarchical.svg +273 -0
  33. data/examples/or1200_test/or1200_test.cmd +78 -0
  34. data/examples/or1200_test/or1200_test.rb +136 -0
  35. data/examples/or1200_test/rtl/or1200_test_top.vhd +274 -0
  36. data/examples/or1200_test/rtl/s3astarter.ucf +10 -0
  37. data/examples/or1200_test/rtl/xilinx_internal_jtag.v +438 -0
  38. data/examples/or1200_test/rtl/xilinx_internal_jtag_options.v +12 -0
  39. data/examples/or1200_test/sw/README.txt +35 -0
  40. data/examples/or1200_test/sw/bin2vmem.c +159 -0
  41. data/examples/or1200_test/sw/board.h +24 -0
  42. data/examples/or1200_test/sw/compile.sh +18 -0
  43. data/examples/or1200_test/sw/except.S +152 -0
  44. data/examples/or1200_test/sw/int.c +79 -0
  45. data/examples/or1200_test/sw/int.h +14 -0
  46. data/examples/or1200_test/sw/interconnect.h +17 -0
  47. data/examples/or1200_test/sw/interrupts.c +14 -0
  48. data/examples/or1200_test/sw/main.c +16 -0
  49. data/examples/or1200_test/sw/or1200.h +454 -0
  50. data/examples/or1200_test/sw/orp.ld +60 -0
  51. data/examples/or1200_test/sw/reset.S +112 -0
  52. data/examples/or1200_test/sw/support.c +123 -0
  53. data/examples/or1200_test/sw/support.h +33 -0
  54. data/examples/or1200_test/sw/tick.c +30 -0
  55. data/examples/or1200_test/sw/tick.h +2 -0
  56. data/examples/or1200_test/sw/uart.c +136 -0
  57. data/examples/or1200_test/sw/uart.h +126 -0
  58. data/lib/soc_maker.rb +324 -0
  59. data/lib/soc_maker/cli.rb +544 -0
  60. data/lib/soc_maker/conf.rb +310 -0
  61. data/lib/soc_maker/core_def.rb +579 -0
  62. data/lib/soc_maker/core_inst.rb +305 -0
  63. data/lib/soc_maker/err.rb +211 -0
  64. data/lib/soc_maker/hdl_coder.rb +500 -0
  65. data/lib/soc_maker/hdl_file.rb +166 -0
  66. data/lib/soc_maker/hdl_parser.rb +431 -0
  67. data/lib/soc_maker/ifc_def.rb +193 -0
  68. data/lib/soc_maker/ifc_port.rb +133 -0
  69. data/lib/soc_maker/ifc_spc.rb +180 -0
  70. data/lib/soc_maker/lib.rb +289 -0
  71. data/lib/soc_maker/lib_inc.rb +109 -0
  72. data/lib/soc_maker/parameter.rb +149 -0
  73. data/lib/soc_maker/soc_def.rb +847 -0
  74. data/lib/soc_maker/sparameter.rb +289 -0
  75. data/lib/soc_maker/version.rb +8 -0
  76. data/lib/soc_maker/ypp.rb +130 -0
  77. data/soc_maker.gemspec +28 -0
  78. data/spec/cli_cmds1.txt +39 -0
  79. data/spec/cli_spec.rb +49 -0
  80. data/spec/conf_spec.rb +44 -0
  81. data/spec/core_def_spec.rb +503 -0
  82. data/spec/core_inst_spec.rb +169 -0
  83. data/spec/hdl_file_spec.rb +154 -0
  84. data/spec/hdl_parser_spec.rb +201 -0
  85. data/spec/ifc_def_spec.rb +121 -0
  86. data/spec/ifc_port_spec.rb +92 -0
  87. data/spec/ifc_spc_spec.rb +196 -0
  88. data/spec/lib_inc_spec.rb +99 -0
  89. data/spec/lib_spec.rb +209 -0
  90. data/spec/parameter_spec.rb +86 -0
  91. data/spec/soc_def_spec.rb +611 -0
  92. data/spec/soc_maker_spec.rb +7 -0
  93. data/spec/sparameter_spec.rb +182 -0
  94. data/spec/spec_helper.rb +78 -0
  95. data/spec/test_soc.yaml +105 -0
  96. data/spec/test_soc2.yaml +60 -0
  97. data/spec/test_soc_lib/cores/core_A_rel1/00_core_a.yaml +75 -0
  98. data/spec/test_soc_lib/cores/core_A_rel1/01_core_a.yaml +57 -0
  99. data/spec/test_soc_lib/cores/core_A_rel1/core_a.vhd +29 -0
  100. data/spec/test_soc_lib/cores/core_A_rel1/core_a_pkg.vhd.src +3 -0
  101. data/spec/test_soc_lib/cores/core_A_rel1/core_a_pkg2.vhd.src +4 -0
  102. data/spec/test_soc_lib/cores/core_A_rel1/core_a_pkg3.v.src +6 -0
  103. data/spec/test_soc_lib/cores/core_B_rel1/core_b.vhd +25 -0
  104. data/spec/test_soc_lib/cores/core_B_rel1/core_b.yaml +36 -0
  105. data/spec/test_soc_lib/cores/core_C_v1/core_C.vhd +57 -0
  106. data/spec/test_soc_lib/cores/core_C_v1/core_c.yaml +42 -0
  107. data/spec/test_soc_lib/cores/soc_A/soc_A.yaml +12 -0
  108. data/spec/test_soc_lib/cores/soc_maker_include.yaml +6 -0
  109. data/spec/test_soc_lib/ifcs/core_AB_ifc/bidir_ifc.yaml +19 -0
  110. data/spec/test_soc_lib/ifcs/core_AB_ifc/core_AB_ifc.yaml +15 -0
  111. data/spec/test_soc_lib/ifcs/core_AB_ifc/top_ifc.yaml +9 -0
  112. data/spec/test_soc_lib/soc_maker_include.yaml +4 -0
  113. data/spec/yaml_examples.rb +367 -0
  114. data/spec/ypp_spec.rb +156 -0
  115. data/test/test_soc_maker.rb +0 -0
  116. metadata +255 -0
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+ d="m 384.71029,360.06045 c 55.20857,-4.29122 68.73191,-54.40701 74.53031,-75.98241"
269
+ id="path3947"
270
+ inkscape:connector-curvature="0"
271
+ sodipodi:nodetypes="cc" />
272
+ </g>
273
+ </svg>
data/examples/or1200_test/or1200_test.cmd ADDED
@@ -0,0 +1,78 @@
1
+ #
2
+ #
3
+ # Please note: this code doesn't work at the moment, please use or1200_test.rb instead.
4
+ #
5
+ # run with ./bin/soc_maker_cli -l core_lib examples/or1200_test/or1200_test.cmd
6
+ #
7
+
8
+
9
+ list
10
+
11
+ new OR1200_Test_SOC or1200_test,v1 or1200_test
12
+
13
+ add_interface clk clk,1 1 clk 1
14
+ add_interface rst rst,1 1 rst 1
15
+
16
+ add_interface jtag_tap jtag_tap,1 1 tck 1 tdi 1 tdo 1 rst 1 shift 1 pause 1 update 1 capture 1 select 1
17
+ add_interface uart uart,1 1 stx_pad 1 srx_pad 1 rts_pad 1 cts_pad 1 dtr_pad 1 dsr_pad 1 ri_pad 1 dcd_pad 1
18
+
19
+ print
20
+
21
+ add or1200,rel2 cpu
22
+ add wb_connect,1 wb_bus
23
+ add adv_debug_sys,ads_3 dbg
24
+ add ram_wb,b3 ram1
25
+ add ram_wb,b3 ram2
26
+ add uart16550,rel4 uart
27
+
28
+
29
+
30
+ sparameter or1200,rel2 VCD_DUMP false
31
+ sparameter or1200,rel2 VERBOSE false
32
+ sparameter or1200,rel2 ASIC false
33
+ sparameter or1200,rel2 ASIC_MEM_CHOICE 0
34
+ sparameter or1200,rel2 ASIC_NO_DC true
35
+ sparameter or1200,rel2 ASIC_NO_IC true
36
+ sparameter or1200,rel2 ASIC_NO_DMMU true
37
+ sparameter or1200,rel2 ASIC_NO_IMMU true
38
+ sparameter or1200,rel2 ASIC_MUL_CHOICE 0
39
+ sparameter or1200,rel2 ASIC_IC_CHOICE 0
40
+ sparameter or1200,rel2 ASIC_DC_CHOICE 0
41
+ sparameter or1200,rel2 FPGA_MEM_CHOICE 2
42
+ sparameter or1200,rel2 FPGA_NO_DC true
43
+ sparameter or1200,rel2 FPGA_NO_IC true
44
+ sparameter or1200,rel2 FPGA_NO_DMMU true
45
+ sparameter or1200,rel2 FPGA_NO_IMMU true
46
+ sparameter or1200,rel2 FPGA_MUL_CHOICE 1
47
+ sparameter or1200,rel2 FPGA_IC_CHOICE 0
48
+ sparameter or1200,rel2 FPGA_DC_CHOICE 0
49
+
50
+ parameter ram1 mem_size_bytes 10240
51
+ parameter ram1 mem_adr_width 14
52
+ parameter ram2 mem_size_bytes 10240
53
+ parameter ram2 mem_adr_width 15
54
+
55
+
56
+
57
+ connect con_main_clk or1200_test clk cpu clk
58
+ connect con_main_rst or1200_test rst cpu rst
59
+
60
+ connect con_main_clk or1200_test clk wb_bus clk
61
+ connect con_main_rst or1200_test rst wb_bus rst
62
+
63
+ connect con_main_clk or1200_test clk dbg cpu0_dbg_clk
64
+
65
+ connect con_jtag_top or1200_test jtag_tap dbg jtag
66
+ connect con_uart_top or1200_test uart uart uart_ifc
67
+
68
+
69
+ connect con_wb_debug wb_bus i3 dbg wb_ifc
70
+ connect con_data wb_bus i4 cpu wb_data
71
+ connect con_instruction wb_bus i5 cpu wb_instruction
72
+ connect con_ram1 wb_bus t0 ram1 wb_ifc
73
+ connect con_ram2 wb_bus t1 ram2 wb_ifc
74
+ connect con_uart wb_bus t5 uart wb_ifc
75
+ connect con_debug dbg cpu0_dbg cpu ext_debug
76
+
77
+ generate
78
+ quit
data/examples/or1200_test/or1200_test.rb ADDED
@@ -0,0 +1,136 @@
1
+ require_relative '../../lib/soc_maker'
2
+
3
+ ##
4
+ # initialize SOCMaker core
5
+ # this sets up logging and parses all yaml files
6
+ # found in the configure path (see also soc_maker_conf.rb)
7
+ SOCMaker::load( libpath: './core_lib/' )
8
+
9
+
10
+ puts "Library Content:"
11
+
12
+
13
+ puts SOCMaker::lib
14
+
15
+
16
+ SOCMaker::lib.cores do |name_version, core|
17
+ # core.update_vcs
18
+ end
19
+
20
+ soc = SOCMaker::SOCDef.new( 'OR1200 Test SOC', 'or1200_test,v1', 'or1200_test' )
21
+ SOCMaker::lib.add_core( soc )
22
+ #soc_inst = SOCMaker::CoreInst.new( 'or1200_test,v1' )
23
+ #soc_inst.name = "soc_inst"
24
+
25
+
26
+ port = SOCMaker::IfcPort.new( 'clk', 1 )
27
+ ifc = SOCMaker::IfcDef.new( 'clk', 'clk,1', 1, { clk_i: port} )
28
+ soc.interfaces[ :clk_ifc ] = ifc
29
+
30
+ port = SOCMaker::IfcPort.new( 'rst', 1 )
31
+ ifc = SOCMaker::IfcDef.new( 'rst', 'rst,1', 1, { rst_i: port} )
32
+ soc.interfaces[ :rst_ifc ] = ifc
33
+
34
+ soc.interfaces[ 'jtag_ifc'.to_sym ] = SOCMaker::IfcDef.new( 'jtag_tap', 'jtag_tap,1', 1, {
35
+ tck_i: SOCMaker::IfcPort.new( 'tck', 1 ),
36
+ tdi_i: SOCMaker::IfcPort.new( 'tdi', 1 ),
37
+ tdo_o: SOCMaker::IfcPort.new( 'tdo' ,1 ),
38
+ debug_rst_i: SOCMaker::IfcPort.new( 'rst', 1 ),
39
+ shift_dr_i: SOCMaker::IfcPort.new( 'shift', 1 ),
40
+ pause_dr_i: SOCMaker::IfcPort.new( 'pause', 1 ),
41
+ update_dr_i: SOCMaker::IfcPort.new( 'update', 1 ),
42
+ capture_dr_i: SOCMaker::IfcPort.new( 'capture', 1 ),
43
+ debug_select_i: SOCMaker::IfcPort.new( 'select', 1 ) } )
44
+
45
+ soc.interfaces[ 'uart_ifc'.to_sym ] = SOCMaker::IfcDef.new( 'uart', 'uart,1', 1, {
46
+ stx_pad_o: SOCMaker::IfcPort.new( 'stx_pad', 1 ),
47
+ srx_pad_i: SOCMaker::IfcPort.new( 'srx_pad', 1 ),
48
+ rts_pad_o: SOCMaker::IfcPort.new( 'rts_pad', 1 ),
49
+ cts_pad_i: SOCMaker::IfcPort.new( 'cts_pad', 1 ),
50
+ dtr_pad_o: SOCMaker::IfcPort.new( 'dtr_pad', 1 ),
51
+ dsr_pad_i: SOCMaker::IfcPort.new( 'dsr_pad', 1 ),
52
+ ri_pad_i: SOCMaker::IfcPort.new( 'ri_pad' , 1 ),
53
+ dcd_pad_i: SOCMaker::IfcPort.new( 'dcd_pad', 1 ) } )
54
+
55
+
56
+ soc.add_core( :'or1200,rel2', :cpu )
57
+ soc.add_core( :'wb_connect,1', :wb_bus )
58
+ soc.add_core( :'adv_debug_sys,ads_3', :dbg )
59
+ soc.add_core( :'ram_wb,b3', :ram1 )
60
+ soc.add_core( :'ram_wb,b3', :ram2 )
61
+ soc.add_core( :'uart16550,rel4', :uart )
62
+ soc.consistence_check
63
+
64
+
65
+ #
66
+ # Setup the CPU
67
+ #
68
+ soc.set_sparam( :'or1200,rel2', :VCD_DUMP, false )
69
+ soc.set_sparam( :'or1200,rel2', :VERBOSE, false )
70
+ soc.set_sparam( :'or1200,rel2', :ASIC , false )
71
+
72
+ soc.set_sparam( :'or1200,rel2', :ASIC_MEM_CHOICE, 0 )
73
+ soc.set_sparam( :'or1200,rel2', :ASIC_NO_DC, true )
74
+ soc.set_sparam( :'or1200,rel2', :ASIC_NO_IC, true )
75
+ soc.set_sparam( :'or1200,rel2', :ASIC_NO_DMMU, true )
76
+ soc.set_sparam( :'or1200,rel2', :ASIC_NO_IMMU, true )
77
+ soc.set_sparam( :'or1200,rel2', :ASIC_MUL_CHOICE, 0 )
78
+ soc.set_sparam( :'or1200,rel2', :ASIC_IC_CHOICE, 0 )
79
+ soc.set_sparam( :'or1200,rel2', :ASIC_DC_CHOICE, 0 )
80
+
81
+ soc.set_sparam( :'or1200,rel2', :FPGA_MEM_CHOICE, 2 )
82
+ soc.set_sparam( :'or1200,rel2', :FPGA_NO_DC, true )
83
+ soc.set_sparam( :'or1200,rel2', :FPGA_NO_IC, true )
84
+ soc.set_sparam( :'or1200,rel2', :FPGA_NO_DMMU, true )
85
+ soc.set_sparam( :'or1200,rel2', :FPGA_NO_IMMU, true )
86
+ soc.set_sparam( :'or1200,rel2', :FPGA_MUL_CHOICE, 1 )
87
+ soc.set_sparam( :'or1200,rel2', :FPGA_IC_CHOICE, 0 )
88
+ soc.set_sparam( :'or1200,rel2', :FPGA_DC_CHOICE, 0 )
89
+
90
+ #
91
+ # Setup the on-chip memory
92
+ #
93
+ # soc.set_sparam( :'ram_wb,b3', :MEM_SIZE, 10 )
94
+ # soc.set_sparam( :'ram_wb,b3', :MEM_ADR_WIDTH, 14 )
95
+ soc.set_param( :ram1, :mem_size_bytes, 10*1024 )
96
+ soc.set_param( :ram1, :mem_adr_width, 14 )
97
+
98
+ soc.set_param( :ram2, :mem_size_bytes, 10*1024 )
99
+ soc.set_param( :ram2, :mem_adr_width, 15 )
100
+
101
+ ####
102
+ #
103
+ # connections to toplevel ports
104
+ #
105
+
106
+ # create connection for clk and rst
107
+ soc.add_connection( :con_main_clk, :or1200_test, :clk_ifc )
108
+ soc.add_connection( :con_main_rst, :or1200_test, :rst_ifc )
109
+
110
+ # connection clk and rst to cores
111
+ soc.add_connection( :con_main_clk, :cpu, :clk )
112
+ soc.add_connection( :con_main_rst, :cpu, :rst )
113
+ soc.add_connection( :con_main_clk, :wb_bus, :clk )
114
+ soc.add_connection( :con_main_rst, :wb_bus, :rst )
115
+ soc.add_connection( :con_main_clk, :dbg, :cpu0_dbg_clk )
116
+
117
+ # create and connect jtag as well as uart to cores
118
+ soc.add_connection( :con_jtag_top, :or1200_test, :jtag_ifc, :dbg, :jtag )
119
+ soc.add_connection( :con_uart_top, :or1200_test, :uart_ifc, :uart, :uart_ifc )
120
+
121
+
122
+
123
+ #
124
+ # core connections
125
+ #
126
+ soc.add_connection( :con_wb_debug , :wb_bus, :i3, :dbg, :wb_ifc )
127
+ soc.add_connection( :con_data , :wb_bus, :i4, :cpu, :wb_data )
128
+ soc.add_connection( :con_instruction, :wb_bus, :i5, :cpu, :wb_instruction )
129
+ soc.add_connection( :con_ram1 , :wb_bus, :t0, :ram1, :wb_ifc )
130
+ soc.add_connection( :con_ram2 , :wb_bus, :t1, :ram2, :wb_ifc )
131
+ soc.add_connection( :con_uart , :wb_bus, :t5, :uart, :wb_ifc )
132
+ soc.add_connection( :con_debug , :dbg, :cpu0_dbg, :cpu, :ext_debug )
133
+
134
+
135
+ SOCMaker::deploy_soc( soc )
136
+